drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c

   1 /*
   2  * Copyright 2015 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "ctxgf100.h"
  25
  26 /*******************************************************************************
  27  * PGRAPH context implementation
  28  ******************************************************************************/
  29
  30 void
  31 gm200_grctx_generate_tpcid(struct gf100_gr *gr)
  32 {
  33         struct nvkm_device *device = gr->base.engine.subdev.device;
  34         int gpc, tpc, id;
  35
  36         for (tpc = 0, id = 0; tpc < TPC_MAX_PER_GPC; tpc++) {
  37                 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
  38                         if (tpc < gr->tpc_nr[gpc]) {
  39                                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id);
  40                                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
  41                                 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id);
  42                                 id++;
  43                         }
  44                 }
  45         }
  46 }
  47
  48 void
  49 gm200_grctx_generate_405b60(struct gf100_gr *gr)
  50 {
  51         struct nvkm_device *device = gr->base.engine.subdev.device;
  52         const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
  53         u32 dist[TPC_MAX / 4] = {};
  54         u32 gpcs[GPC_MAX] = {};
  55         u8  tpcnr[GPC_MAX];
  56         int tpc, gpc, i;
  57
  58         memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
  59
  60         /* won't result in the same distribution as the binary driver where
  61          * some of the gpcs have more tpcs than others, but this shall do
  62          * for the moment.  the code for earlier gpus has this issue too.
  63          */
  64         for (gpc = -1, i = 0; i < gr->tpc_total; i++) {
  65                 do {
  66                         gpc = (gpc + 1) % gr->gpc_nr;
  67                 } while(!tpcnr[gpc]);
  68                 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
  69
  70                 dist[i / 4] |= ((gpc << 4) | tpc) << ((i % 4) * 8);
  71                 gpcs[gpc] |= i << (tpc * 8);
  72         }
  73
  74         for (i = 0; i < dist_nr; i++)
  75                 nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
  76         for (i = 0; i < gr->gpc_nr; i++)
  77                 nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
  78 }
  79
  80 static void
  81 gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
  82 {
  83         struct nvkm_device *device = gr->base.engine.subdev.device;
  84         const struct gf100_grctx_func *grctx = gr->func->grctx;
  85         u32 idle_timeout, tmp;
  86         int i;
  87
  88         gf100_gr_mmio(gr, gr->fuc_sw_ctx);
  89
  90         idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
  91
  92         grctx->bundle(info);
  93         grctx->pagepool(info);
  94         grctx->attrib(info);
  95         grctx->unkn(gr);
  96
  97         gm200_grctx_generate_tpcid(gr);
  98         gf100_grctx_generate_r406028(gr);
  99         gk104_grctx_generate_r418bb8(gr);
 100
 101         for (i = 0; i < 8; i++)
 102                 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
 103         nvkm_wr32(device, 0x406500, 0x00000000);
 104
 105         nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
 106
 107         for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
 108                 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
 109         nvkm_wr32(device, 0x4041c4, tmp);
 110
 111         gm200_grctx_generate_405b60(gr);
 112
 113         gf100_gr_icmd(gr, gr->fuc_bundle);
 114         nvkm_wr32(device, 0x404154, idle_timeout);
 115         gf100_gr_mthd(gr, gr->fuc_method);
 116
 117         nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000);
 118         nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000);
 119 }
 120
 121 const struct gf100_grctx_func
 122 gm200_grctx = {
 123         .main  = gm200_grctx_generate_main,
 124         .unkn  = gk104_grctx_generate_unkn,
 125         .bundle = gm107_grctx_generate_bundle,
 126         .bundle_size = 0x3000,
 127         .bundle_min_gpm_fifo_depth = 0x180,
 128         .bundle_token_limit = 0x780,
 129         .pagepool = gm107_grctx_generate_pagepool,
 130         .pagepool_size = 0x20000,
 131         .attrib = gm107_grctx_generate_attrib,
 132         .attrib_nr_max = 0x600,
 133         .attrib_nr = 0x400,
 134         .alpha_nr_max = 0x1800,
 135         .alpha_nr = 0x1000,
 136 };