drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

   1 /*
   2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "priv.h"
  23
  24 #include <core/msgqueue.h>
  25 #include <engine/falcon.h>
  26
  27 static void *
  28 nvkm_sec2_dtor(struct nvkm_engine *engine)
  29 {
  30         struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
  31         nvkm_msgqueue_del(&sec2->queue);
  32         nvkm_falcon_del(&sec2->falcon);
  33         return sec2;
  34 }
  35
  36 static void
  37 nvkm_sec2_intr(struct nvkm_engine *engine)
  38 {
  39         struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
  40         struct nvkm_subdev *subdev = &engine->subdev;
  41         struct nvkm_device *device = subdev->device;
  42         u32 disp = nvkm_rd32(device, 0x8701c);
  43         u32 intr = nvkm_rd32(device, 0x87008) & disp & ~(disp >> 16);
  44
  45         if (intr & 0x00000040) {
  46                 schedule_work(&sec2->work);
  47                 nvkm_wr32(device, 0x87004, 0x00000040);
  48                 intr &= ~0x00000040;
  49         }
  50
  51         if (intr) {
  52                 nvkm_error(subdev, "unhandled intr %08x\n", intr);
  53                 nvkm_wr32(device, 0x87004, intr);
  54
  55         }
  56 }
  57
  58 static void
  59 nvkm_sec2_recv(struct work_struct *work)
  60 {
  61         struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work);
  62
  63         if (!sec2->queue) {
  64                 nvkm_warn(&sec2->engine.subdev,
  65                           "recv function called while no firmware set!\n");
  66                 return;
  67         }
  68
  69         nvkm_msgqueue_recv(sec2->queue);
  70 }
  71
  72
  73 static int
  74 nvkm_sec2_oneinit(struct nvkm_engine *engine)
  75 {
  76         struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
  77         return nvkm_falcon_v1_new(&sec2->engine.subdev, "SEC2", 0x87000,
  78                                   &sec2->falcon);
  79 }
  80
  81 static int
  82 nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
  83 {
  84         struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
  85         flush_work(&sec2->work);
  86         return 0;
  87 }
  88
  89 static const struct nvkm_engine_func
  90 nvkm_sec2 = {
  91         .dtor = nvkm_sec2_dtor,
  92         .oneinit = nvkm_sec2_oneinit,
  93         .fini = nvkm_sec2_fini,
  94         .intr = nvkm_sec2_intr,
  95 };
  96
  97 int
  98 nvkm_sec2_new_(struct nvkm_device *device, int index,
  99                struct nvkm_sec2 **psec2)
 100 {
 101         struct nvkm_sec2 *sec2;
 102
 103         if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL)))
 104                 return -ENOMEM;
 105         INIT_WORK(&sec2->work, nvkm_sec2_recv);
 106
 107         return nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine);
 108 };