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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / gpu / drm / omapdrm / dss / dispc.c
blob4e8f68efd169ee1d24649a38d662c2619cdce392
1 /*
2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * Some code and ideas taken from drivers/video/omap/ driver
6 * by Imre Deak.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #define DSS_SUBSYS_NAME "DISPC"
22
23 #include <linux/kernel.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/vmalloc.h>
26 #include <linux/export.h>
27 #include <linux/clk.h>
28 #include <linux/io.h>
29 #include <linux/jiffies.h>
30 #include <linux/seq_file.h>
31 #include <linux/delay.h>
32 #include <linux/workqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/sizes.h>
37 #include <linux/mfd/syscon.h>
38 #include <linux/regmap.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/component.h>
42 #include <linux/sys_soc.h>
43 #include <drm/drm_fourcc.h>
44 #include <drm/drm_blend.h>
45
46 #include "omapdss.h"
47 #include "dss.h"
48 #include "dispc.h"
49
50 /* DISPC */
51 #define DISPC_SZ_REGS SZ_4K
52
53 enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57 };
58
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
65 /* DISPC has feature id */
66 enum dispc_feature_id {
67 FEAT_LCDENABLEPOL,
68 FEAT_LCDENABLESIGNAL,
69 FEAT_PCKFREEENABLE,
70 FEAT_FUNCGATED,
71 FEAT_MGR_LCD2,
72 FEAT_MGR_LCD3,
73 FEAT_LINEBUFFERSPLIT,
74 FEAT_ROWREPEATENABLE,
75 FEAT_RESIZECONF,
76 /* Independent core clk divider */
77 FEAT_CORE_CLK_DIV,
78 FEAT_HANDLE_UV_SEPARATE,
79 FEAT_ATTR2,
80 FEAT_CPR,
81 FEAT_PRELOAD,
82 FEAT_FIR_COEF_V,
83 FEAT_ALPHA_FIXED_ZORDER,
84 FEAT_ALPHA_FREE_ZORDER,
85 FEAT_FIFO_MERGE,
86 /* An unknown HW bug causing the normal FIFO thresholds not to work */
87 FEAT_OMAP3_DSI_FIFO_BUG,
88 FEAT_BURST_2D,
89 FEAT_MFLAG,
90 };
91
92 struct dispc_features {
93 u8 sw_start;
94 u8 fp_start;
95 u8 bp_start;
96 u16 sw_max;
97 u16 vp_max;
98 u16 hp_max;
99 u8 mgr_width_start;
100 u8 mgr_height_start;
101 u16 mgr_width_max;
102 u16 mgr_height_max;
103 unsigned long max_lcd_pclk;
104 unsigned long max_tv_pclk;
105 unsigned int max_downscale;
106 unsigned int max_line_width;
107 unsigned int min_pcd;
108 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
109 const struct videomode *vm,
110 u16 width, u16 height, u16 out_width, u16 out_height,
111 u32 fourcc, bool *five_taps,
112 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
113 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
114 unsigned long (*calc_core_clk) (unsigned long pclk,
115 u16 width, u16 height, u16 out_width, u16 out_height,
116 bool mem_to_mem);
117 u8 num_fifos;
118 const enum dispc_feature_id *features;
119 unsigned int num_features;
120 const struct dss_reg_field *reg_fields;
121 const unsigned int num_reg_fields;
122 const enum omap_overlay_caps *overlay_caps;
123 const u32 **supported_color_modes;
124 unsigned int num_mgrs;
125 unsigned int num_ovls;
126 unsigned int buffer_size_unit;
127 unsigned int burst_size_unit;
128
129 /* swap GFX & WB fifos */
130 bool gfx_fifo_workaround:1;
131
132 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
133 bool no_framedone_tv:1;
134
135 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
136 bool mstandby_workaround:1;
137
138 bool set_max_preload:1;
139
140 /* PIXEL_INC is not added to the last pixel of a line */
141 bool last_pixel_inc_missing:1;
142
143 /* POL_FREQ has ALIGN bit */
144 bool supports_sync_align:1;
145
146 bool has_writeback:1;
147
148 bool supports_double_pixel:1;
149
150 /*
151 * Field order for VENC is different than HDMI. We should handle this in
152 * some intelligent manner, but as the SoCs have either HDMI or VENC,
153 * never both, we can just use this flag for now.
154 */
155 bool reverse_ilace_field_order:1;
156
157 bool has_gamma_table:1;
158
159 bool has_gamma_i734_bug:1;
160 };
161
162 #define DISPC_MAX_NR_FIFOS 5
163 #define DISPC_MAX_CHANNEL_GAMMA 4
164
165 static struct {
166 struct platform_device *pdev;
167 void __iomem *base;
168
169 int irq;
170 irq_handler_t user_handler;
171 void *user_data;
172
173 unsigned long core_clk_rate;
174 unsigned long tv_pclk_rate;
175
176 u32 fifo_size[DISPC_MAX_NR_FIFOS];
177 /* maps which plane is using a fifo. fifo-id -> plane-id */
178 int fifo_assignment[DISPC_MAX_NR_FIFOS];
179
180 bool ctx_valid;
181 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
182
183 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
184
185 const struct dispc_features *feat;
186
187 bool is_enabled;
188
189 struct regmap *syscon_pol;
190 u32 syscon_pol_offset;
191
192 /* DISPC_CONTROL & DISPC_CONFIG lock*/
193 spinlock_t control_lock;
194 } dispc;
195
196 enum omap_color_component {
197 /* used for all color formats for OMAP3 and earlier
198 * and for RGB and Y color component on OMAP4
199 */
200 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
201 /* used for UV component for
202 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12
203 * color formats on OMAP4
204 */
205 DISPC_COLOR_COMPONENT_UV = 1 << 1,
206 };
207
208 enum mgr_reg_fields {
209 DISPC_MGR_FLD_ENABLE,
210 DISPC_MGR_FLD_STNTFT,
211 DISPC_MGR_FLD_GO,
212 DISPC_MGR_FLD_TFTDATALINES,
213 DISPC_MGR_FLD_STALLMODE,
214 DISPC_MGR_FLD_TCKENABLE,
215 DISPC_MGR_FLD_TCKSELECTION,
216 DISPC_MGR_FLD_CPR,
217 DISPC_MGR_FLD_FIFOHANDCHECK,
218 /* used to maintain a count of the above fields */
219 DISPC_MGR_FLD_NUM,
220 };
221
222 /* DISPC register field id */
223 enum dispc_feat_reg_field {
224 FEAT_REG_FIRHINC,
225 FEAT_REG_FIRVINC,
226 FEAT_REG_FIFOHIGHTHRESHOLD,
227 FEAT_REG_FIFOLOWTHRESHOLD,
228 FEAT_REG_FIFOSIZE,
229 FEAT_REG_HORIZONTALACCU,
230 FEAT_REG_VERTICALACCU,
231 };
232
233 struct dispc_reg_field {
234 u16 reg;
235 u8 high;
236 u8 low;
237 };
238
239 struct dispc_gamma_desc {
240 u32 len;
241 u32 bits;
242 u16 reg;
243 bool has_index;
244 };
245
246 static const struct {
247 const char *name;
248 u32 vsync_irq;
249 u32 framedone_irq;
250 u32 sync_lost_irq;
251 struct dispc_gamma_desc gamma;
252 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
253 } mgr_desc[] = {
254 [OMAP_DSS_CHANNEL_LCD] = {
255 .name = "LCD",
256 .vsync_irq = DISPC_IRQ_VSYNC,
257 .framedone_irq = DISPC_IRQ_FRAMEDONE,
258 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
259 .gamma = {
260 .len = 256,
261 .bits = 8,
262 .reg = DISPC_GAMMA_TABLE0,
263 .has_index = true,
264 },
265 .reg_desc = {
266 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
267 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
268 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
269 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
270 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
271 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
272 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
273 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
274 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
275 },
276 },
277 [OMAP_DSS_CHANNEL_DIGIT] = {
278 .name = "DIGIT",
279 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
280 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
281 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
282 .gamma = {
283 .len = 1024,
284 .bits = 10,
285 .reg = DISPC_GAMMA_TABLE2,
286 .has_index = false,
287 },
288 .reg_desc = {
289 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
290 [DISPC_MGR_FLD_STNTFT] = { },
291 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
292 [DISPC_MGR_FLD_TFTDATALINES] = { },
293 [DISPC_MGR_FLD_STALLMODE] = { },
294 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
295 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
296 [DISPC_MGR_FLD_CPR] = { },
297 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
298 },
299 },
300 [OMAP_DSS_CHANNEL_LCD2] = {
301 .name = "LCD2",
302 .vsync_irq = DISPC_IRQ_VSYNC2,
303 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
304 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
305 .gamma = {
306 .len = 256,
307 .bits = 8,
308 .reg = DISPC_GAMMA_TABLE1,
309 .has_index = true,
310 },
311 .reg_desc = {
312 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
313 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
314 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
315 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
316 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
317 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
318 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
319 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
320 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
321 },
322 },
323 [OMAP_DSS_CHANNEL_LCD3] = {
324 .name = "LCD3",
325 .vsync_irq = DISPC_IRQ_VSYNC3,
326 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
327 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
328 .gamma = {
329 .len = 256,
330 .bits = 8,
331 .reg = DISPC_GAMMA_TABLE3,
332 .has_index = true,
333 },
334 .reg_desc = {
335 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
336 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
337 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
338 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
339 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
340 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
341 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
342 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
343 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
344 },
345 },
346 };
347
348 struct color_conv_coef {
349 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
350 int full_range;
351 };
352
353 static unsigned long dispc_fclk_rate(void);
354 static unsigned long dispc_core_clk_rate(void);
355 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
356 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
357
358 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane);
359 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane);
360
361 static void dispc_clear_irqstatus(u32 mask);
362 static bool dispc_mgr_is_enabled(enum omap_channel channel);
363 static void dispc_clear_irqstatus(u32 mask);
364
365 static inline void dispc_write_reg(const u16 idx, u32 val)
366 {
367 __raw_writel(val, dispc.base + idx);
368 }
369
370 static inline u32 dispc_read_reg(const u16 idx)
371 {
372 return __raw_readl(dispc.base + idx);
373 }
374
375 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
376 {
377 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
378 return REG_GET(rfld.reg, rfld.high, rfld.low);
379 }
380
381 static void mgr_fld_write(enum omap_channel channel,
382 enum mgr_reg_fields regfld, int val) {
383 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
384 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
385 unsigned long flags;
386
387 if (need_lock)
388 spin_lock_irqsave(&dispc.control_lock, flags);
389
390 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
391
392 if (need_lock)
393 spin_unlock_irqrestore(&dispc.control_lock, flags);
394 }
395
396 static int dispc_get_num_ovls(void)
397 {
398 return dispc.feat->num_ovls;
399 }
400
401 static int dispc_get_num_mgrs(void)
402 {
403 return dispc.feat->num_mgrs;
404 }
405
406 static void dispc_get_reg_field(enum dispc_feat_reg_field id,
407 u8 *start, u8 *end)
408 {
409 if (id >= dispc.feat->num_reg_fields)
410 BUG();
411
412 *start = dispc.feat->reg_fields[id].start;
413 *end = dispc.feat->reg_fields[id].end;
414 }
415
416 static bool dispc_has_feature(enum dispc_feature_id id)
417 {
418 unsigned int i;
419
420 for (i = 0; i < dispc.feat->num_features; i++) {
421 if (dispc.feat->features[i] == id)
422 return true;
423 }
424
425 return false;
426 }
427
428 #define SR(reg) \
429 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
430 #define RR(reg) \
431 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
432
433 static void dispc_save_context(void)
434 {
435 int i, j;
436
437 DSSDBG("dispc_save_context\n");
438
439 SR(IRQENABLE);
440 SR(CONTROL);
441 SR(CONFIG);
442 SR(LINE_NUMBER);
443 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
444 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER))
445 SR(GLOBAL_ALPHA);
446 if (dispc_has_feature(FEAT_MGR_LCD2)) {
447 SR(CONTROL2);
448 SR(CONFIG2);
449 }
450 if (dispc_has_feature(FEAT_MGR_LCD3)) {
451 SR(CONTROL3);
452 SR(CONFIG3);
453 }
454
455 for (i = 0; i < dispc_get_num_mgrs(); i++) {
456 SR(DEFAULT_COLOR(i));
457 SR(TRANS_COLOR(i));
458 SR(SIZE_MGR(i));
459 if (i == OMAP_DSS_CHANNEL_DIGIT)
460 continue;
461 SR(TIMING_H(i));
462 SR(TIMING_V(i));
463 SR(POL_FREQ(i));
464 SR(DIVISORo(i));
465
466 SR(DATA_CYCLE1(i));
467 SR(DATA_CYCLE2(i));
468 SR(DATA_CYCLE3(i));
469
470 if (dispc_has_feature(FEAT_CPR)) {
471 SR(CPR_COEF_R(i));
472 SR(CPR_COEF_G(i));
473 SR(CPR_COEF_B(i));
474 }
475 }
476
477 for (i = 0; i < dispc_get_num_ovls(); i++) {
478 SR(OVL_BA0(i));
479 SR(OVL_BA1(i));
480 SR(OVL_POSITION(i));
481 SR(OVL_SIZE(i));
482 SR(OVL_ATTRIBUTES(i));
483 SR(OVL_FIFO_THRESHOLD(i));
484 SR(OVL_ROW_INC(i));
485 SR(OVL_PIXEL_INC(i));
486 if (dispc_has_feature(FEAT_PRELOAD))
487 SR(OVL_PRELOAD(i));
488 if (i == OMAP_DSS_GFX) {
489 SR(OVL_WINDOW_SKIP(i));
490 SR(OVL_TABLE_BA(i));
491 continue;
492 }
493 SR(OVL_FIR(i));
494 SR(OVL_PICTURE_SIZE(i));
495 SR(OVL_ACCU0(i));
496 SR(OVL_ACCU1(i));
497
498 for (j = 0; j < 8; j++)
499 SR(OVL_FIR_COEF_H(i, j));
500
501 for (j = 0; j < 8; j++)
502 SR(OVL_FIR_COEF_HV(i, j));
503
504 for (j = 0; j < 5; j++)
505 SR(OVL_CONV_COEF(i, j));
506
507 if (dispc_has_feature(FEAT_FIR_COEF_V)) {
508 for (j = 0; j < 8; j++)
509 SR(OVL_FIR_COEF_V(i, j));
510 }
511
512 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
513 SR(OVL_BA0_UV(i));
514 SR(OVL_BA1_UV(i));
515 SR(OVL_FIR2(i));
516 SR(OVL_ACCU2_0(i));
517 SR(OVL_ACCU2_1(i));
518
519 for (j = 0; j < 8; j++)
520 SR(OVL_FIR_COEF_H2(i, j));
521
522 for (j = 0; j < 8; j++)
523 SR(OVL_FIR_COEF_HV2(i, j));
524
525 for (j = 0; j < 8; j++)
526 SR(OVL_FIR_COEF_V2(i, j));
527 }
528 if (dispc_has_feature(FEAT_ATTR2))
529 SR(OVL_ATTRIBUTES2(i));
530 }
531
532 if (dispc_has_feature(FEAT_CORE_CLK_DIV))
533 SR(DIVISOR);
534
535 dispc.ctx_valid = true;
536
537 DSSDBG("context saved\n");
538 }
539
540 static void dispc_restore_context(void)
541 {
542 int i, j;
543
544 DSSDBG("dispc_restore_context\n");
545
546 if (!dispc.ctx_valid)
547 return;
548
549 /*RR(IRQENABLE);*/
550 /*RR(CONTROL);*/
551 RR(CONFIG);
552 RR(LINE_NUMBER);
553 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
554 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER))
555 RR(GLOBAL_ALPHA);
556 if (dispc_has_feature(FEAT_MGR_LCD2))
557 RR(CONFIG2);
558 if (dispc_has_feature(FEAT_MGR_LCD3))
559 RR(CONFIG3);
560
561 for (i = 0; i < dispc_get_num_mgrs(); i++) {
562 RR(DEFAULT_COLOR(i));
563 RR(TRANS_COLOR(i));
564 RR(SIZE_MGR(i));
565 if (i == OMAP_DSS_CHANNEL_DIGIT)
566 continue;
567 RR(TIMING_H(i));
568 RR(TIMING_V(i));
569 RR(POL_FREQ(i));
570 RR(DIVISORo(i));
571
572 RR(DATA_CYCLE1(i));
573 RR(DATA_CYCLE2(i));
574 RR(DATA_CYCLE3(i));
575
576 if (dispc_has_feature(FEAT_CPR)) {
577 RR(CPR_COEF_R(i));
578 RR(CPR_COEF_G(i));
579 RR(CPR_COEF_B(i));
580 }
581 }
582
583 for (i = 0; i < dispc_get_num_ovls(); i++) {
584 RR(OVL_BA0(i));
585 RR(OVL_BA1(i));
586 RR(OVL_POSITION(i));
587 RR(OVL_SIZE(i));
588 RR(OVL_ATTRIBUTES(i));
589 RR(OVL_FIFO_THRESHOLD(i));
590 RR(OVL_ROW_INC(i));
591 RR(OVL_PIXEL_INC(i));
592 if (dispc_has_feature(FEAT_PRELOAD))
593 RR(OVL_PRELOAD(i));
594 if (i == OMAP_DSS_GFX) {
595 RR(OVL_WINDOW_SKIP(i));
596 RR(OVL_TABLE_BA(i));
597 continue;
598 }
599 RR(OVL_FIR(i));
600 RR(OVL_PICTURE_SIZE(i));
601 RR(OVL_ACCU0(i));
602 RR(OVL_ACCU1(i));
603
604 for (j = 0; j < 8; j++)
605 RR(OVL_FIR_COEF_H(i, j));
606
607 for (j = 0; j < 8; j++)
608 RR(OVL_FIR_COEF_HV(i, j));
609
610 for (j = 0; j < 5; j++)
611 RR(OVL_CONV_COEF(i, j));
612
613 if (dispc_has_feature(FEAT_FIR_COEF_V)) {
614 for (j = 0; j < 8; j++)
615 RR(OVL_FIR_COEF_V(i, j));
616 }
617
618 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
619 RR(OVL_BA0_UV(i));
620 RR(OVL_BA1_UV(i));
621 RR(OVL_FIR2(i));
622 RR(OVL_ACCU2_0(i));
623 RR(OVL_ACCU2_1(i));
624
625 for (j = 0; j < 8; j++)
626 RR(OVL_FIR_COEF_H2(i, j));
627
628 for (j = 0; j < 8; j++)
629 RR(OVL_FIR_COEF_HV2(i, j));
630
631 for (j = 0; j < 8; j++)
632 RR(OVL_FIR_COEF_V2(i, j));
633 }
634 if (dispc_has_feature(FEAT_ATTR2))
635 RR(OVL_ATTRIBUTES2(i));
636 }
637
638 if (dispc_has_feature(FEAT_CORE_CLK_DIV))
639 RR(DIVISOR);
640
641 /* enable last, because LCD & DIGIT enable are here */
642 RR(CONTROL);
643 if (dispc_has_feature(FEAT_MGR_LCD2))
644 RR(CONTROL2);
645 if (dispc_has_feature(FEAT_MGR_LCD3))
646 RR(CONTROL3);
647 /* clear spurious SYNC_LOST_DIGIT interrupts */
648 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
649
650 /*
651 * enable last so IRQs won't trigger before
652 * the context is fully restored
653 */
654 RR(IRQENABLE);
655
656 DSSDBG("context restored\n");
657 }
658
659 #undef SR
660 #undef RR
661
662 int dispc_runtime_get(void)
663 {
664 int r;
665
666 DSSDBG("dispc_runtime_get\n");
667
668 r = pm_runtime_get_sync(&dispc.pdev->dev);
669 WARN_ON(r < 0);
670 return r < 0 ? r : 0;
671 }
672
673 void dispc_runtime_put(void)
674 {
675 int r;
676
677 DSSDBG("dispc_runtime_put\n");
678
679 r = pm_runtime_put_sync(&dispc.pdev->dev);
680 WARN_ON(r < 0 && r != -ENOSYS);
681 }
682
683 static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
684 {
685 return mgr_desc[channel].vsync_irq;
686 }
687
688 static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
689 {
690 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
691 return 0;
692
693 return mgr_desc[channel].framedone_irq;
694 }
695
696 static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
697 {
698 return mgr_desc[channel].sync_lost_irq;
699 }
700
701 u32 dispc_wb_get_framedone_irq(void)
702 {
703 return DISPC_IRQ_FRAMEDONEWB;
704 }
705
706 static void dispc_mgr_enable(enum omap_channel channel, bool enable)
707 {
708 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
709 /* flush posted write */
710 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
711 }
712
713 static bool dispc_mgr_is_enabled(enum omap_channel channel)
714 {
715 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
716 }
717
718 static bool dispc_mgr_go_busy(enum omap_channel channel)
719 {
720 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
721 }
722
723 static void dispc_mgr_go(enum omap_channel channel)
724 {
725 WARN_ON(!dispc_mgr_is_enabled(channel));
726 WARN_ON(dispc_mgr_go_busy(channel));
727
728 DSSDBG("GO %s\n", mgr_desc[channel].name);
729
730 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
731 }
732
733 bool dispc_wb_go_busy(void)
734 {
735 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
736 }
737
738 void dispc_wb_go(void)
739 {
740 enum omap_plane_id plane = OMAP_DSS_WB;
741 bool enable, go;
742
743 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
744
745 if (!enable)
746 return;
747
748 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
749 if (go) {
750 DSSERR("GO bit not down for WB\n");
751 return;
752 }
753
754 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
755 }
756
757 static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg,
758 u32 value)
759 {
760 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
761 }
762
763 static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg,
764 u32 value)
765 {
766 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
767 }
768
769 static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg,
770 u32 value)
771 {
772 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
773 }
774
775 static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg,
776 u32 value)
777 {
778 BUG_ON(plane == OMAP_DSS_GFX);
779
780 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
781 }
782
783 static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg,
784 u32 value)
785 {
786 BUG_ON(plane == OMAP_DSS_GFX);
787
788 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
789 }
790
791 static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg,
792 u32 value)
793 {
794 BUG_ON(plane == OMAP_DSS_GFX);
795
796 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
797 }
798
799 static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
800 int fir_vinc, int five_taps,
801 enum omap_color_component color_comp)
802 {
803 const struct dispc_coef *h_coef, *v_coef;
804 int i;
805
806 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
807 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
808
809 for (i = 0; i < 8; i++) {
810 u32 h, hv;
811
812 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
813 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
814 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
815 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
816 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
817 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
818 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
819 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
820
821 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
822 dispc_ovl_write_firh_reg(plane, i, h);
823 dispc_ovl_write_firhv_reg(plane, i, hv);
824 } else {
825 dispc_ovl_write_firh2_reg(plane, i, h);
826 dispc_ovl_write_firhv2_reg(plane, i, hv);
827 }
828
829 }
830
831 if (five_taps) {
832 for (i = 0; i < 8; i++) {
833 u32 v;
834 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
835 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
836 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
837 dispc_ovl_write_firv_reg(plane, i, v);
838 else
839 dispc_ovl_write_firv2_reg(plane, i, v);
840 }
841 }
842 }
843
844
845 static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane,
846 const struct color_conv_coef *ct)
847 {
848 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
849
850 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
851 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
852 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
853 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
854 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
855
856 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
857
858 #undef CVAL
859 }
860
861 static void dispc_setup_color_conv_coef(void)
862 {
863 int i;
864 int num_ovl = dispc_get_num_ovls();
865 const struct color_conv_coef ctbl_bt601_5_ovl = {
866 /* YUV -> RGB */
867 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
868 };
869 const struct color_conv_coef ctbl_bt601_5_wb = {
870 /* RGB -> YUV */
871 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
872 };
873
874 for (i = 1; i < num_ovl; i++)
875 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
876
877 if (dispc.feat->has_writeback)
878 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
879 }
880
881 static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr)
882 {
883 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
884 }
885
886 static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr)
887 {
888 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
889 }
890
891 static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr)
892 {
893 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
894 }
895
896 static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr)
897 {
898 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
899 }
900
901 static void dispc_ovl_set_pos(enum omap_plane_id plane,
902 enum omap_overlay_caps caps, int x, int y)
903 {
904 u32 val;
905
906 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
907 return;
908
909 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
910
911 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
912 }
913
914 static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width,
915 int height)
916 {
917 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
918
919 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
920 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
921 else
922 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
923 }
924
925 static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width,
926 int height)
927 {
928 u32 val;
929
930 BUG_ON(plane == OMAP_DSS_GFX);
931
932 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
933
934 if (plane == OMAP_DSS_WB)
935 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
936 else
937 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
938 }
939
940 static void dispc_ovl_set_zorder(enum omap_plane_id plane,
941 enum omap_overlay_caps caps, u8 zorder)
942 {
943 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
944 return;
945
946 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
947 }
948
949 static void dispc_ovl_enable_zorder_planes(void)
950 {
951 int i;
952
953 if (!dispc_has_feature(FEAT_ALPHA_FREE_ZORDER))
954 return;
955
956 for (i = 0; i < dispc_get_num_ovls(); i++)
957 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
958 }
959
960 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane,
961 enum omap_overlay_caps caps, bool enable)
962 {
963 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
964 return;
965
966 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
967 }
968
969 static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane,
970 enum omap_overlay_caps caps, u8 global_alpha)
971 {
972 static const unsigned shifts[] = { 0, 8, 16, 24, };
973 int shift;
974
975 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
976 return;
977
978 shift = shifts[plane];
979 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
980 }
981
982 static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc)
983 {
984 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
985 }
986
987 static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc)
988 {
989 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
990 }
991
992 static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc)
993 {
994 u32 m = 0;
995 if (plane != OMAP_DSS_GFX) {
996 switch (fourcc) {
997 case DRM_FORMAT_NV12:
998 m = 0x0; break;
999 case DRM_FORMAT_XRGB4444:
1000 m = 0x1; break;
1001 case DRM_FORMAT_RGBA4444:
1002 m = 0x2; break;
1003 case DRM_FORMAT_RGBX4444:
1004 m = 0x4; break;
1005 case DRM_FORMAT_ARGB4444:
1006 m = 0x5; break;
1007 case DRM_FORMAT_RGB565:
1008 m = 0x6; break;
1009 case DRM_FORMAT_ARGB1555:
1010 m = 0x7; break;
1011 case DRM_FORMAT_XRGB8888:
1012 m = 0x8; break;
1013 case DRM_FORMAT_RGB888:
1014 m = 0x9; break;
1015 case DRM_FORMAT_YUYV:
1016 m = 0xa; break;
1017 case DRM_FORMAT_UYVY:
1018 m = 0xb; break;
1019 case DRM_FORMAT_ARGB8888:
1020 m = 0xc; break;
1021 case DRM_FORMAT_RGBA8888:
1022 m = 0xd; break;
1023 case DRM_FORMAT_RGBX8888:
1024 m = 0xe; break;
1025 case DRM_FORMAT_XRGB1555:
1026 m = 0xf; break;
1027 default:
1028 BUG(); return;
1029 }
1030 } else {
1031 switch (fourcc) {
1032 case DRM_FORMAT_RGBX4444:
1033 m = 0x4; break;
1034 case DRM_FORMAT_ARGB4444:
1035 m = 0x5; break;
1036 case DRM_FORMAT_RGB565:
1037 m = 0x6; break;
1038 case DRM_FORMAT_ARGB1555:
1039 m = 0x7; break;
1040 case DRM_FORMAT_XRGB8888:
1041 m = 0x8; break;
1042 case DRM_FORMAT_RGB888:
1043 m = 0x9; break;
1044 case DRM_FORMAT_XRGB4444:
1045 m = 0xa; break;
1046 case DRM_FORMAT_RGBA4444:
1047 m = 0xb; break;
1048 case DRM_FORMAT_ARGB8888:
1049 m = 0xc; break;
1050 case DRM_FORMAT_RGBA8888:
1051 m = 0xd; break;
1052 case DRM_FORMAT_RGBX8888:
1053 m = 0xe; break;
1054 case DRM_FORMAT_XRGB1555:
1055 m = 0xf; break;
1056 default:
1057 BUG(); return;
1058 }
1059 }
1060
1061 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1062 }
1063
1064 static bool format_is_yuv(u32 fourcc)
1065 {
1066 switch (fourcc) {
1067 case DRM_FORMAT_YUYV:
1068 case DRM_FORMAT_UYVY:
1069 case DRM_FORMAT_NV12:
1070 return true;
1071 default:
1072 return false;
1073 }
1074 }
1075
1076 static void dispc_ovl_configure_burst_type(enum omap_plane_id plane,
1077 enum omap_dss_rotation_type rotation_type)
1078 {
1079 if (dispc_has_feature(FEAT_BURST_2D) == 0)
1080 return;
1081
1082 if (rotation_type == OMAP_DSS_ROT_TILER)
1083 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1084 else
1085 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1086 }
1087
1088 static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1089 enum omap_channel channel)
1090 {
1091 int shift;
1092 u32 val;
1093 int chan = 0, chan2 = 0;
1094
1095 switch (plane) {
1096 case OMAP_DSS_GFX:
1097 shift = 8;
1098 break;
1099 case OMAP_DSS_VIDEO1:
1100 case OMAP_DSS_VIDEO2:
1101 case OMAP_DSS_VIDEO3:
1102 shift = 16;
1103 break;
1104 default:
1105 BUG();
1106 return;
1107 }
1108
1109 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1110 if (dispc_has_feature(FEAT_MGR_LCD2)) {
1111 switch (channel) {
1112 case OMAP_DSS_CHANNEL_LCD:
1113 chan = 0;
1114 chan2 = 0;
1115 break;
1116 case OMAP_DSS_CHANNEL_DIGIT:
1117 chan = 1;
1118 chan2 = 0;
1119 break;
1120 case OMAP_DSS_CHANNEL_LCD2:
1121 chan = 0;
1122 chan2 = 1;
1123 break;
1124 case OMAP_DSS_CHANNEL_LCD3:
1125 if (dispc_has_feature(FEAT_MGR_LCD3)) {
1126 chan = 0;
1127 chan2 = 2;
1128 } else {
1129 BUG();
1130 return;
1131 }
1132 break;
1133 case OMAP_DSS_CHANNEL_WB:
1134 chan = 0;
1135 chan2 = 3;
1136 break;
1137 default:
1138 BUG();
1139 return;
1140 }
1141
1142 val = FLD_MOD(val, chan, shift, shift);
1143 val = FLD_MOD(val, chan2, 31, 30);
1144 } else {
1145 val = FLD_MOD(val, channel, shift, shift);
1146 }
1147 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1148 }
1149
1150 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
1151 {
1152 int shift;
1153 u32 val;
1154
1155 switch (plane) {
1156 case OMAP_DSS_GFX:
1157 shift = 8;
1158 break;
1159 case OMAP_DSS_VIDEO1:
1160 case OMAP_DSS_VIDEO2:
1161 case OMAP_DSS_VIDEO3:
1162 shift = 16;
1163 break;
1164 default:
1165 BUG();
1166 return 0;
1167 }
1168
1169 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1170
1171 if (FLD_GET(val, shift, shift) == 1)
1172 return OMAP_DSS_CHANNEL_DIGIT;
1173
1174 if (!dispc_has_feature(FEAT_MGR_LCD2))
1175 return OMAP_DSS_CHANNEL_LCD;
1176
1177 switch (FLD_GET(val, 31, 30)) {
1178 case 0:
1179 default:
1180 return OMAP_DSS_CHANNEL_LCD;
1181 case 1:
1182 return OMAP_DSS_CHANNEL_LCD2;
1183 case 2:
1184 return OMAP_DSS_CHANNEL_LCD3;
1185 case 3:
1186 return OMAP_DSS_CHANNEL_WB;
1187 }
1188 }
1189
1190 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1191 {
1192 enum omap_plane_id plane = OMAP_DSS_WB;
1193
1194 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1195 }
1196
1197 static void dispc_ovl_set_burst_size(enum omap_plane_id plane,
1198 enum omap_burst_size burst_size)
1199 {
1200 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1201 int shift;
1202
1203 shift = shifts[plane];
1204 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1205 }
1206
1207 static void dispc_configure_burst_sizes(void)
1208 {
1209 int i;
1210 const int burst_size = BURST_SIZE_X8;
1211
1212 /* Configure burst size always to maximum size */
1213 for (i = 0; i < dispc_get_num_ovls(); ++i)
1214 dispc_ovl_set_burst_size(i, burst_size);
1215 if (dispc.feat->has_writeback)
1216 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1217 }
1218
1219 static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane)
1220 {
1221 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1222 return dispc.feat->burst_size_unit * 8;
1223 }
1224
1225 static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc)
1226 {
1227 const u32 *modes;
1228 unsigned int i;
1229
1230 modes = dispc.feat->supported_color_modes[plane];
1231
1232 for (i = 0; modes[i]; ++i) {
1233 if (modes[i] == fourcc)
1234 return true;
1235 }
1236
1237 return false;
1238 }
1239
1240 static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane)
1241 {
1242 return dispc.feat->supported_color_modes[plane];
1243 }
1244
1245 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1246 {
1247 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1248 return;
1249
1250 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1251 }
1252
1253 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1254 const struct omap_dss_cpr_coefs *coefs)
1255 {
1256 u32 coef_r, coef_g, coef_b;
1257
1258 if (!dss_mgr_is_lcd(channel))
1259 return;
1260
1261 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1262 FLD_VAL(coefs->rb, 9, 0);
1263 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1264 FLD_VAL(coefs->gb, 9, 0);
1265 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1266 FLD_VAL(coefs->bb, 9, 0);
1267
1268 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1269 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1270 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1271 }
1272
1273 static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane,
1274 bool enable)
1275 {
1276 u32 val;
1277
1278 BUG_ON(plane == OMAP_DSS_GFX);
1279
1280 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1281 val = FLD_MOD(val, enable, 9, 9);
1282 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1283 }
1284
1285 static void dispc_ovl_enable_replication(enum omap_plane_id plane,
1286 enum omap_overlay_caps caps, bool enable)
1287 {
1288 static const unsigned shifts[] = { 5, 10, 10, 10 };
1289 int shift;
1290
1291 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1292 return;
1293
1294 shift = shifts[plane];
1295 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1296 }
1297
1298 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1299 u16 height)
1300 {
1301 u32 val;
1302
1303 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1304 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1305
1306 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1307 }
1308
1309 static void dispc_init_fifos(void)
1310 {
1311 u32 size;
1312 int fifo;
1313 u8 start, end;
1314 u32 unit;
1315 int i;
1316
1317 unit = dispc.feat->buffer_size_unit;
1318
1319 dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1320
1321 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1322 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1323 size *= unit;
1324 dispc.fifo_size[fifo] = size;
1325
1326 /*
1327 * By default fifos are mapped directly to overlays, fifo 0 to
1328 * ovl 0, fifo 1 to ovl 1, etc.
1329 */
1330 dispc.fifo_assignment[fifo] = fifo;
1331 }
1332
1333 /*
1334 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1335 * causes problems with certain use cases, like using the tiler in 2D
1336 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1337 * giving GFX plane a larger fifo. WB but should work fine with a
1338 * smaller fifo.
1339 */
1340 if (dispc.feat->gfx_fifo_workaround) {
1341 u32 v;
1342
1343 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1344
1345 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1346 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1347 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1348 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1349
1350 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1351
1352 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1353 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1354 }
1355
1356 /*
1357 * Setup default fifo thresholds.
1358 */
1359 for (i = 0; i < dispc_get_num_ovls(); ++i) {
1360 u32 low, high;
1361 const bool use_fifomerge = false;
1362 const bool manual_update = false;
1363
1364 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1365 use_fifomerge, manual_update);
1366
1367 dispc_ovl_set_fifo_threshold(i, low, high);
1368 }
1369
1370 if (dispc.feat->has_writeback) {
1371 u32 low, high;
1372 const bool use_fifomerge = false;
1373 const bool manual_update = false;
1374
1375 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1376 use_fifomerge, manual_update);
1377
1378 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1379 }
1380 }
1381
1382 static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane)
1383 {
1384 int fifo;
1385 u32 size = 0;
1386
1387 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1388 if (dispc.fifo_assignment[fifo] == plane)
1389 size += dispc.fifo_size[fifo];
1390 }
1391
1392 return size;
1393 }
1394
1395 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
1396 u32 high)
1397 {
1398 u8 hi_start, hi_end, lo_start, lo_end;
1399 u32 unit;
1400
1401 unit = dispc.feat->buffer_size_unit;
1402
1403 WARN_ON(low % unit != 0);
1404 WARN_ON(high % unit != 0);
1405
1406 low /= unit;
1407 high /= unit;
1408
1409 dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1410 dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1411
1412 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1413 plane,
1414 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1415 lo_start, lo_end) * unit,
1416 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1417 hi_start, hi_end) * unit,
1418 low * unit, high * unit);
1419
1420 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1421 FLD_VAL(high, hi_start, hi_end) |
1422 FLD_VAL(low, lo_start, lo_end));
1423
1424 /*
1425 * configure the preload to the pipeline's high threhold, if HT it's too
1426 * large for the preload field, set the threshold to the maximum value
1427 * that can be held by the preload register
1428 */
1429 if (dispc_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1430 plane != OMAP_DSS_WB)
1431 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1432 }
1433
1434 void dispc_enable_fifomerge(bool enable)
1435 {
1436 if (!dispc_has_feature(FEAT_FIFO_MERGE)) {
1437 WARN_ON(enable);
1438 return;
1439 }
1440
1441 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1442 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1443 }
1444
1445 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
1446 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1447 bool manual_update)
1448 {
1449 /*
1450 * All sizes are in bytes. Both the buffer and burst are made of
1451 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1452 */
1453
1454 unsigned buf_unit = dispc.feat->buffer_size_unit;
1455 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1456 int i;
1457
1458 burst_size = dispc_ovl_get_burst_size(plane);
1459 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1460
1461 if (use_fifomerge) {
1462 total_fifo_size = 0;
1463 for (i = 0; i < dispc_get_num_ovls(); ++i)
1464 total_fifo_size += dispc_ovl_get_fifo_size(i);
1465 } else {
1466 total_fifo_size = ovl_fifo_size;
1467 }
1468
1469 /*
1470 * We use the same low threshold for both fifomerge and non-fifomerge
1471 * cases, but for fifomerge we calculate the high threshold using the
1472 * combined fifo size
1473 */
1474
1475 if (manual_update && dispc_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1476 *fifo_low = ovl_fifo_size - burst_size * 2;
1477 *fifo_high = total_fifo_size - burst_size;
1478 } else if (plane == OMAP_DSS_WB) {
1479 /*
1480 * Most optimal configuration for writeback is to push out data
1481 * to the interconnect the moment writeback pushes enough pixels
1482 * in the FIFO to form a burst
1483 */
1484 *fifo_low = 0;
1485 *fifo_high = burst_size;
1486 } else {
1487 *fifo_low = ovl_fifo_size - burst_size;
1488 *fifo_high = total_fifo_size - buf_unit;
1489 }
1490 }
1491
1492 static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
1493 {
1494 int bit;
1495
1496 if (plane == OMAP_DSS_GFX)
1497 bit = 14;
1498 else
1499 bit = 23;
1500
1501 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1502 }
1503
1504 static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane,
1505 int low, int high)
1506 {
1507 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1508 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1509 }
1510
1511 static void dispc_init_mflag(void)
1512 {
1513 int i;
1514
1515 /*
1516 * HACK: NV12 color format and MFLAG seem to have problems working
1517 * together: using two displays, and having an NV12 overlay on one of
1518 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1519 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1520 * remove the errors, but there doesn't seem to be a clear logic on
1521 * which values work and which not.
1522 *
1523 * As a work-around, set force MFLAG to always on.
1524 */
1525 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1526 (1 << 0) | /* MFLAG_CTRL = force always on */
1527 (0 << 2)); /* MFLAG_START = disable */
1528
1529 for (i = 0; i < dispc_get_num_ovls(); ++i) {
1530 u32 size = dispc_ovl_get_fifo_size(i);
1531 u32 unit = dispc.feat->buffer_size_unit;
1532 u32 low, high;
1533
1534 dispc_ovl_set_mflag(i, true);
1535
1536 /*
1537 * Simulation team suggests below thesholds:
1538 * HT = fifosize * 5 / 8;
1539 * LT = fifosize * 4 / 8;
1540 */
1541
1542 low = size * 4 / 8 / unit;
1543 high = size * 5 / 8 / unit;
1544
1545 dispc_ovl_set_mflag_threshold(i, low, high);
1546 }
1547
1548 if (dispc.feat->has_writeback) {
1549 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1550 u32 unit = dispc.feat->buffer_size_unit;
1551 u32 low, high;
1552
1553 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1554
1555 /*
1556 * Simulation team suggests below thesholds:
1557 * HT = fifosize * 5 / 8;
1558 * LT = fifosize * 4 / 8;
1559 */
1560
1561 low = size * 4 / 8 / unit;
1562 high = size * 5 / 8 / unit;
1563
1564 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1565 }
1566 }
1567
1568 static void dispc_ovl_set_fir(enum omap_plane_id plane,
1569 int hinc, int vinc,
1570 enum omap_color_component color_comp)
1571 {
1572 u32 val;
1573
1574 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1575 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1576
1577 dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1578 dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1579 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1580 FLD_VAL(hinc, hinc_start, hinc_end);
1581
1582 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1583 } else {
1584 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1585 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1586 }
1587 }
1588
1589 static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu,
1590 int vaccu)
1591 {
1592 u32 val;
1593 u8 hor_start, hor_end, vert_start, vert_end;
1594
1595 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1596 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1597
1598 val = FLD_VAL(vaccu, vert_start, vert_end) |
1599 FLD_VAL(haccu, hor_start, hor_end);
1600
1601 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1602 }
1603
1604 static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu,
1605 int vaccu)
1606 {
1607 u32 val;
1608 u8 hor_start, hor_end, vert_start, vert_end;
1609
1610 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1611 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1612
1613 val = FLD_VAL(vaccu, vert_start, vert_end) |
1614 FLD_VAL(haccu, hor_start, hor_end);
1615
1616 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1617 }
1618
1619 static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu,
1620 int vaccu)
1621 {
1622 u32 val;
1623
1624 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1625 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1626 }
1627
1628 static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu,
1629 int vaccu)
1630 {
1631 u32 val;
1632
1633 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1634 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1635 }
1636
1637 static void dispc_ovl_set_scale_param(enum omap_plane_id plane,
1638 u16 orig_width, u16 orig_height,
1639 u16 out_width, u16 out_height,
1640 bool five_taps, u8 rotation,
1641 enum omap_color_component color_comp)
1642 {
1643 int fir_hinc, fir_vinc;
1644
1645 fir_hinc = 1024 * orig_width / out_width;
1646 fir_vinc = 1024 * orig_height / out_height;
1647
1648 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1649 color_comp);
1650 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1651 }
1652
1653 static void dispc_ovl_set_accu_uv(enum omap_plane_id plane,
1654 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1655 bool ilace, u32 fourcc, u8 rotation)
1656 {
1657 int h_accu2_0, h_accu2_1;
1658 int v_accu2_0, v_accu2_1;
1659 int chroma_hinc, chroma_vinc;
1660 int idx;
1661
1662 struct accu {
1663 s8 h0_m, h0_n;
1664 s8 h1_m, h1_n;
1665 s8 v0_m, v0_n;
1666 s8 v1_m, v1_n;
1667 };
1668
1669 const struct accu *accu_table;
1670 const struct accu *accu_val;
1671
1672 static const struct accu accu_nv12[4] = {
1673 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1674 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1675 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1676 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1677 };
1678
1679 static const struct accu accu_nv12_ilace[4] = {
1680 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1681 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1682 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1683 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1684 };
1685
1686 static const struct accu accu_yuv[4] = {
1687 { 0, 1, 0, 1, 0, 1, 0, 1 },
1688 { 0, 1, 0, 1, 0, 1, 0, 1 },
1689 { -1, 1, 0, 1, 0, 1, 0, 1 },
1690 { 0, 1, 0, 1, -1, 1, 0, 1 },
1691 };
1692
1693 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1694 switch (rotation & DRM_MODE_ROTATE_MASK) {
1695 default:
1696 case DRM_MODE_ROTATE_0:
1697 idx = 0;
1698 break;
1699 case DRM_MODE_ROTATE_90:
1700 idx = 3;
1701 break;
1702 case DRM_MODE_ROTATE_180:
1703 idx = 2;
1704 break;
1705 case DRM_MODE_ROTATE_270:
1706 idx = 1;
1707 break;
1708 }
1709
1710 switch (fourcc) {
1711 case DRM_FORMAT_NV12:
1712 if (ilace)
1713 accu_table = accu_nv12_ilace;
1714 else
1715 accu_table = accu_nv12;
1716 break;
1717 case DRM_FORMAT_YUYV:
1718 case DRM_FORMAT_UYVY:
1719 accu_table = accu_yuv;
1720 break;
1721 default:
1722 BUG();
1723 return;
1724 }
1725
1726 accu_val = &accu_table[idx];
1727
1728 chroma_hinc = 1024 * orig_width / out_width;
1729 chroma_vinc = 1024 * orig_height / out_height;
1730
1731 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1732 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1733 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1734 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1735
1736 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1737 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1738 }
1739
1740 static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
1741 u16 orig_width, u16 orig_height,
1742 u16 out_width, u16 out_height,
1743 bool ilace, bool five_taps,
1744 bool fieldmode, u32 fourcc,
1745 u8 rotation)
1746 {
1747 int accu0 = 0;
1748 int accu1 = 0;
1749 u32 l;
1750
1751 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1752 out_width, out_height, five_taps,
1753 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1754 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1755
1756 /* RESIZEENABLE and VERTICALTAPS */
1757 l &= ~((0x3 << 5) | (0x1 << 21));
1758 l |= (orig_width != out_width) ? (1 << 5) : 0;
1759 l |= (orig_height != out_height) ? (1 << 6) : 0;
1760 l |= five_taps ? (1 << 21) : 0;
1761
1762 /* VRESIZECONF and HRESIZECONF */
1763 if (dispc_has_feature(FEAT_RESIZECONF)) {
1764 l &= ~(0x3 << 7);
1765 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1766 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1767 }
1768
1769 /* LINEBUFFERSPLIT */
1770 if (dispc_has_feature(FEAT_LINEBUFFERSPLIT)) {
1771 l &= ~(0x1 << 22);
1772 l |= five_taps ? (1 << 22) : 0;
1773 }
1774
1775 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1776
1777 /*
1778 * field 0 = even field = bottom field
1779 * field 1 = odd field = top field
1780 */
1781 if (ilace && !fieldmode) {
1782 accu1 = 0;
1783 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1784 if (accu0 >= 1024/2) {
1785 accu1 = 1024/2;
1786 accu0 -= accu1;
1787 }
1788 }
1789
1790 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1791 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1792 }
1793
1794 static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane,
1795 u16 orig_width, u16 orig_height,
1796 u16 out_width, u16 out_height,
1797 bool ilace, bool five_taps,
1798 bool fieldmode, u32 fourcc,
1799 u8 rotation)
1800 {
1801 int scale_x = out_width != orig_width;
1802 int scale_y = out_height != orig_height;
1803 bool chroma_upscale = plane != OMAP_DSS_WB;
1804
1805 if (!dispc_has_feature(FEAT_HANDLE_UV_SEPARATE))
1806 return;
1807
1808 if (!format_is_yuv(fourcc)) {
1809 /* reset chroma resampling for RGB formats */
1810 if (plane != OMAP_DSS_WB)
1811 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1812 return;
1813 }
1814
1815 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1816 out_height, ilace, fourcc, rotation);
1817
1818 switch (fourcc) {
1819 case DRM_FORMAT_NV12:
1820 if (chroma_upscale) {
1821 /* UV is subsampled by 2 horizontally and vertically */
1822 orig_height >>= 1;
1823 orig_width >>= 1;
1824 } else {
1825 /* UV is downsampled by 2 horizontally and vertically */
1826 orig_height <<= 1;
1827 orig_width <<= 1;
1828 }
1829
1830 break;
1831 case DRM_FORMAT_YUYV:
1832 case DRM_FORMAT_UYVY:
1833 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1834 if (!drm_rotation_90_or_270(rotation)) {
1835 if (chroma_upscale)
1836 /* UV is subsampled by 2 horizontally */
1837 orig_width >>= 1;
1838 else
1839 /* UV is downsampled by 2 horizontally */
1840 orig_width <<= 1;
1841 }
1842
1843 /* must use FIR for YUV422 if rotated */
1844 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0)
1845 scale_x = scale_y = true;
1846
1847 break;
1848 default:
1849 BUG();
1850 return;
1851 }
1852
1853 if (out_width != orig_width)
1854 scale_x = true;
1855 if (out_height != orig_height)
1856 scale_y = true;
1857
1858 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1859 out_width, out_height, five_taps,
1860 rotation, DISPC_COLOR_COMPONENT_UV);
1861
1862 if (plane != OMAP_DSS_WB)
1863 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1864 (scale_x || scale_y) ? 1 : 0, 8, 8);
1865
1866 /* set H scaling */
1867 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1868 /* set V scaling */
1869 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1870 }
1871
1872 static void dispc_ovl_set_scaling(enum omap_plane_id plane,
1873 u16 orig_width, u16 orig_height,
1874 u16 out_width, u16 out_height,
1875 bool ilace, bool five_taps,
1876 bool fieldmode, u32 fourcc,
1877 u8 rotation)
1878 {
1879 BUG_ON(plane == OMAP_DSS_GFX);
1880
1881 dispc_ovl_set_scaling_common(plane,
1882 orig_width, orig_height,
1883 out_width, out_height,
1884 ilace, five_taps,
1885 fieldmode, fourcc,
1886 rotation);
1887
1888 dispc_ovl_set_scaling_uv(plane,
1889 orig_width, orig_height,
1890 out_width, out_height,
1891 ilace, five_taps,
1892 fieldmode, fourcc,
1893 rotation);
1894 }
1895
1896 static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation,
1897 enum omap_dss_rotation_type rotation_type, u32 fourcc)
1898 {
1899 bool row_repeat = false;
1900 int vidrot = 0;
1901
1902 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1903 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
1904
1905 if (rotation & DRM_MODE_REFLECT_X) {
1906 switch (rotation & DRM_MODE_ROTATE_MASK) {
1907 case DRM_MODE_ROTATE_0:
1908 vidrot = 2;
1909 break;
1910 case DRM_MODE_ROTATE_90:
1911 vidrot = 1;
1912 break;
1913 case DRM_MODE_ROTATE_180:
1914 vidrot = 0;
1915 break;
1916 case DRM_MODE_ROTATE_270:
1917 vidrot = 3;
1918 break;
1919 }
1920 } else {
1921 switch (rotation & DRM_MODE_ROTATE_MASK) {
1922 case DRM_MODE_ROTATE_0:
1923 vidrot = 0;
1924 break;
1925 case DRM_MODE_ROTATE_90:
1926 vidrot = 3;
1927 break;
1928 case DRM_MODE_ROTATE_180:
1929 vidrot = 2;
1930 break;
1931 case DRM_MODE_ROTATE_270:
1932 vidrot = 1;
1933 break;
1934 }
1935 }
1936
1937 if (drm_rotation_90_or_270(rotation))
1938 row_repeat = true;
1939 else
1940 row_repeat = false;
1941 }
1942
1943 /*
1944 * OMAP4/5 Errata i631:
1945 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1946 * rows beyond the framebuffer, which may cause OCP error.
1947 */
1948 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER)
1949 vidrot = 1;
1950
1951 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1952 if (dispc_has_feature(FEAT_ROWREPEATENABLE))
1953 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1954 row_repeat ? 1 : 0, 18, 18);
1955
1956 if (dispc_ovl_color_mode_supported(plane, DRM_FORMAT_NV12)) {
1957 bool doublestride =
1958 fourcc == DRM_FORMAT_NV12 &&
1959 rotation_type == OMAP_DSS_ROT_TILER &&
1960 !drm_rotation_90_or_270(rotation);
1961
1962 /* DOUBLESTRIDE */
1963 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1964 }
1965 }
1966
1967 static int color_mode_to_bpp(u32 fourcc)
1968 {
1969 switch (fourcc) {
1970 case DRM_FORMAT_NV12:
1971 return 8;
1972 case DRM_FORMAT_RGBX4444:
1973 case DRM_FORMAT_RGB565:
1974 case DRM_FORMAT_ARGB4444:
1975 case DRM_FORMAT_YUYV:
1976 case DRM_FORMAT_UYVY:
1977 case DRM_FORMAT_RGBA4444:
1978 case DRM_FORMAT_XRGB4444:
1979 case DRM_FORMAT_ARGB1555:
1980 case DRM_FORMAT_XRGB1555:
1981 return 16;
1982 case DRM_FORMAT_RGB888:
1983 return 24;
1984 case DRM_FORMAT_XRGB8888:
1985 case DRM_FORMAT_ARGB8888:
1986 case DRM_FORMAT_RGBA8888:
1987 case DRM_FORMAT_RGBX8888:
1988 return 32;
1989 default:
1990 BUG();
1991 return 0;
1992 }
1993 }
1994
1995 static s32 pixinc(int pixels, u8 ps)
1996 {
1997 if (pixels == 1)
1998 return 1;
1999 else if (pixels > 1)
2000 return 1 + (pixels - 1) * ps;
2001 else if (pixels < 0)
2002 return 1 - (-pixels + 1) * ps;
2003 else
2004 BUG();
2005 return 0;
2006 }
2007
2008 static void calc_offset(u16 screen_width, u16 width,
2009 u32 fourcc, bool fieldmode,
2010 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2011 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
2012 enum omap_dss_rotation_type rotation_type, u8 rotation)
2013 {
2014 u8 ps;
2015
2016 ps = color_mode_to_bpp(fourcc) / 8;
2017
2018 DSSDBG("scrw %d, width %d\n", screen_width, width);
2019
2020 if (rotation_type == OMAP_DSS_ROT_TILER &&
2021 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) &&
2022 drm_rotation_90_or_270(rotation)) {
2023 /*
2024 * HACK: ROW_INC needs to be calculated with TILER units.
2025 * We get such 'screen_width' that multiplying it with the
2026 * YUV422 pixel size gives the correct TILER container width.
2027 * However, 'width' is in pixels and multiplying it with YUV422
2028 * pixel size gives incorrect result. We thus multiply it here
2029 * with 2 to match the 32 bit TILER unit size.
2030 */
2031 width *= 2;
2032 }
2033
2034 /*
2035 * field 0 = even field = bottom field
2036 * field 1 = odd field = top field
2037 */
2038 *offset0 = field_offset * screen_width * ps;
2039 *offset1 = 0;
2040
2041 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2042 (fieldmode ? screen_width : 0), ps);
2043 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
2044 *pix_inc = pixinc(x_predecim, 2 * ps);
2045 else
2046 *pix_inc = pixinc(x_predecim, ps);
2047 }
2048
2049 /*
2050 * This function is used to avoid synclosts in OMAP3, because of some
2051 * undocumented horizontal position and timing related limitations.
2052 */
2053 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2054 const struct videomode *vm, u16 pos_x,
2055 u16 width, u16 height, u16 out_width, u16 out_height,
2056 bool five_taps)
2057 {
2058 const int ds = DIV_ROUND_UP(height, out_height);
2059 unsigned long nonactive;
2060 static const u8 limits[3] = { 8, 10, 20 };
2061 u64 val, blank;
2062 int i;
2063
2064 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2065 vm->hback_porch - out_width;
2066
2067 i = 0;
2068 if (out_height < height)
2069 i++;
2070 if (out_width < width)
2071 i++;
2072 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2073 lclk, pclk);
2074 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2075 if (blank <= limits[i])
2076 return -EINVAL;
2077
2078 /* FIXME add checks for 3-tap filter once the limitations are known */
2079 if (!five_taps)
2080 return 0;
2081
2082 /*
2083 * Pixel data should be prepared before visible display point starts.
2084 * So, atleast DS-2 lines must have already been fetched by DISPC
2085 * during nonactive - pos_x period.
2086 */
2087 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2088 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2089 val, max(0, ds - 2) * width);
2090 if (val < max(0, ds - 2) * width)
2091 return -EINVAL;
2092
2093 /*
2094 * All lines need to be refilled during the nonactive period of which
2095 * only one line can be loaded during the active period. So, atleast
2096 * DS - 1 lines should be loaded during nonactive period.
2097 */
2098 val = div_u64((u64)nonactive * lclk, pclk);
2099 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2100 val, max(0, ds - 1) * width);
2101 if (val < max(0, ds - 1) * width)
2102 return -EINVAL;
2103
2104 return 0;
2105 }
2106
2107 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2108 const struct videomode *vm, u16 width,
2109 u16 height, u16 out_width, u16 out_height,
2110 u32 fourcc)
2111 {
2112 u32 core_clk = 0;
2113 u64 tmp;
2114
2115 if (height <= out_height && width <= out_width)
2116 return (unsigned long) pclk;
2117
2118 if (height > out_height) {
2119 unsigned int ppl = vm->hactive;
2120
2121 tmp = (u64)pclk * height * out_width;
2122 do_div(tmp, 2 * out_height * ppl);
2123 core_clk = tmp;
2124
2125 if (height > 2 * out_height) {
2126 if (ppl == out_width)
2127 return 0;
2128
2129 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2130 do_div(tmp, 2 * out_height * (ppl - out_width));
2131 core_clk = max_t(u32, core_clk, tmp);
2132 }
2133 }
2134
2135 if (width > out_width) {
2136 tmp = (u64)pclk * width;
2137 do_div(tmp, out_width);
2138 core_clk = max_t(u32, core_clk, tmp);
2139
2140 if (fourcc == DRM_FORMAT_XRGB8888)
2141 core_clk <<= 1;
2142 }
2143
2144 return core_clk;
2145 }
2146
2147 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2148 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2149 {
2150 if (height > out_height && width > out_width)
2151 return pclk * 4;
2152 else
2153 return pclk * 2;
2154 }
2155
2156 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2157 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2158 {
2159 unsigned int hf, vf;
2160
2161 /*
2162 * FIXME how to determine the 'A' factor
2163 * for the no downscaling case ?
2164 */
2165
2166 if (width > 3 * out_width)
2167 hf = 4;
2168 else if (width > 2 * out_width)
2169 hf = 3;
2170 else if (width > out_width)
2171 hf = 2;
2172 else
2173 hf = 1;
2174 if (height > out_height)
2175 vf = 2;
2176 else
2177 vf = 1;
2178
2179 return pclk * vf * hf;
2180 }
2181
2182 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2183 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2184 {
2185 /*
2186 * If the overlay/writeback is in mem to mem mode, there are no
2187 * downscaling limitations with respect to pixel clock, return 1 as
2188 * required core clock to represent that we have sufficient enough
2189 * core clock to do maximum downscaling
2190 */
2191 if (mem_to_mem)
2192 return 1;
2193
2194 if (width > out_width)
2195 return DIV_ROUND_UP(pclk, out_width) * width;
2196 else
2197 return pclk;
2198 }
2199
2200 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2201 const struct videomode *vm,
2202 u16 width, u16 height, u16 out_width, u16 out_height,
2203 u32 fourcc, bool *five_taps,
2204 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2205 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2206 {
2207 int error;
2208 u16 in_width, in_height;
2209 int min_factor = min(*decim_x, *decim_y);
2210 const int maxsinglelinewidth = dispc.feat->max_line_width;
2211
2212 *five_taps = false;
2213
2214 do {
2215 in_height = height / *decim_y;
2216 in_width = width / *decim_x;
2217 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2218 in_height, out_width, out_height, mem_to_mem);
2219 error = (in_width > maxsinglelinewidth || !*core_clk ||
2220 *core_clk > dispc_core_clk_rate());
2221 if (error) {
2222 if (*decim_x == *decim_y) {
2223 *decim_x = min_factor;
2224 ++*decim_y;
2225 } else {
2226 swap(*decim_x, *decim_y);
2227 if (*decim_x < *decim_y)
2228 ++*decim_x;
2229 }
2230 }
2231 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2232
2233 if (error) {
2234 DSSERR("failed to find scaling settings\n");
2235 return -EINVAL;
2236 }
2237
2238 if (in_width > maxsinglelinewidth) {
2239 DSSERR("Cannot scale max input width exceeded");
2240 return -EINVAL;
2241 }
2242 return 0;
2243 }
2244
2245 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2246 const struct videomode *vm,
2247 u16 width, u16 height, u16 out_width, u16 out_height,
2248 u32 fourcc, bool *five_taps,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2251 {
2252 int error;
2253 u16 in_width, in_height;
2254 const int maxsinglelinewidth = dispc.feat->max_line_width;
2255
2256 do {
2257 in_height = height / *decim_y;
2258 in_width = width / *decim_x;
2259 *five_taps = in_height > out_height;
2260
2261 if (in_width > maxsinglelinewidth)
2262 if (in_height > out_height &&
2263 in_height < out_height * 2)
2264 *five_taps = false;
2265 again:
2266 if (*five_taps)
2267 *core_clk = calc_core_clk_five_taps(pclk, vm,
2268 in_width, in_height, out_width,
2269 out_height, fourcc);
2270 else
2271 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2272 in_height, out_width, out_height,
2273 mem_to_mem);
2274
2275 error = check_horiz_timing_omap3(pclk, lclk, vm,
2276 pos_x, in_width, in_height, out_width,
2277 out_height, *five_taps);
2278 if (error && *five_taps) {
2279 *five_taps = false;
2280 goto again;
2281 }
2282
2283 error = (error || in_width > maxsinglelinewidth * 2 ||
2284 (in_width > maxsinglelinewidth && *five_taps) ||
2285 !*core_clk || *core_clk > dispc_core_clk_rate());
2286
2287 if (!error) {
2288 /* verify that we're inside the limits of scaler */
2289 if (in_width / 4 > out_width)
2290 error = 1;
2291
2292 if (*five_taps) {
2293 if (in_height / 4 > out_height)
2294 error = 1;
2295 } else {
2296 if (in_height / 2 > out_height)
2297 error = 1;
2298 }
2299 }
2300
2301 if (error)
2302 ++*decim_y;
2303 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2304
2305 if (error) {
2306 DSSERR("failed to find scaling settings\n");
2307 return -EINVAL;
2308 }
2309
2310 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2311 in_height, out_width, out_height, *five_taps)) {
2312 DSSERR("horizontal timing too tight\n");
2313 return -EINVAL;
2314 }
2315
2316 if (in_width > (maxsinglelinewidth * 2)) {
2317 DSSERR("Cannot setup scaling");
2318 DSSERR("width exceeds maximum width possible");
2319 return -EINVAL;
2320 }
2321
2322 if (in_width > maxsinglelinewidth && *five_taps) {
2323 DSSERR("cannot setup scaling with five taps");
2324 return -EINVAL;
2325 }
2326 return 0;
2327 }
2328
2329 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2330 const struct videomode *vm,
2331 u16 width, u16 height, u16 out_width, u16 out_height,
2332 u32 fourcc, bool *five_taps,
2333 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2334 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2335 {
2336 u16 in_width, in_width_max;
2337 int decim_x_min = *decim_x;
2338 u16 in_height = height / *decim_y;
2339 const int maxsinglelinewidth = dispc.feat->max_line_width;
2340 const int maxdownscale = dispc.feat->max_downscale;
2341
2342 if (mem_to_mem) {
2343 in_width_max = out_width * maxdownscale;
2344 } else {
2345 in_width_max = dispc_core_clk_rate() /
2346 DIV_ROUND_UP(pclk, out_width);
2347 }
2348
2349 *decim_x = DIV_ROUND_UP(width, in_width_max);
2350
2351 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2352 if (*decim_x > *x_predecim)
2353 return -EINVAL;
2354
2355 do {
2356 in_width = width / *decim_x;
2357 } while (*decim_x <= *x_predecim &&
2358 in_width > maxsinglelinewidth && ++*decim_x);
2359
2360 if (in_width > maxsinglelinewidth) {
2361 DSSERR("Cannot scale width exceeds max line width");
2362 return -EINVAL;
2363 }
2364
2365 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) {
2366 /*
2367 * Let's disable all scaling that requires horizontal
2368 * decimation with higher factor than 4, until we have
2369 * better estimates of what we can and can not
2370 * do. However, NV12 color format appears to work Ok
2371 * with all decimation factors.
2372 *
2373 * When decimating horizontally by more that 4 the dss
2374 * is not able to fetch the data in burst mode. When
2375 * this happens it is hard to tell if there enough
2376 * bandwidth. Despite what theory says this appears to
2377 * be true also for 16-bit color formats.
2378 */
2379 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x);
2380
2381 return -EINVAL;
2382 }
2383
2384 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2385 out_width, out_height, mem_to_mem);
2386 return 0;
2387 }
2388
2389 #define DIV_FRAC(dividend, divisor) \
2390 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2391
2392 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2393 enum omap_overlay_caps caps,
2394 const struct videomode *vm,
2395 u16 width, u16 height, u16 out_width, u16 out_height,
2396 u32 fourcc, bool *five_taps,
2397 int *x_predecim, int *y_predecim, u16 pos_x,
2398 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2399 {
2400 const int maxdownscale = dispc.feat->max_downscale;
2401 const int max_decim_limit = 16;
2402 unsigned long core_clk = 0;
2403 int decim_x, decim_y, ret;
2404
2405 if (width == out_width && height == out_height)
2406 return 0;
2407
2408 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2409 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2410 return -EINVAL;
2411 }
2412
2413 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2414 return -EINVAL;
2415
2416 if (mem_to_mem) {
2417 *x_predecim = *y_predecim = 1;
2418 } else {
2419 *x_predecim = max_decim_limit;
2420 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2421 dispc_has_feature(FEAT_BURST_2D)) ?
2422 2 : max_decim_limit;
2423 }
2424
2425 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2426 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2427
2428 if (decim_x > *x_predecim || out_width > width * 8)
2429 return -EINVAL;
2430
2431 if (decim_y > *y_predecim || out_height > height * 8)
2432 return -EINVAL;
2433
2434 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height,
2435 out_width, out_height, fourcc, five_taps,
2436 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2437 mem_to_mem);
2438 if (ret)
2439 return ret;
2440
2441 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2442 width, height,
2443 out_width, out_height,
2444 out_width / width, DIV_FRAC(out_width, width),
2445 out_height / height, DIV_FRAC(out_height, height),
2446
2447 decim_x, decim_y,
2448 width / decim_x, height / decim_y,
2449 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2450 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2451
2452 *five_taps ? 5 : 3,
2453 core_clk, dispc_core_clk_rate());
2454
2455 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2456 DSSERR("failed to set up scaling, "
2457 "required core clk rate = %lu Hz, "
2458 "current core clk rate = %lu Hz\n",
2459 core_clk, dispc_core_clk_rate());
2460 return -EINVAL;
2461 }
2462
2463 *x_predecim = decim_x;
2464 *y_predecim = decim_y;
2465 return 0;
2466 }
2467
2468 static int dispc_ovl_setup_common(enum omap_plane_id plane,
2469 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2470 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2471 u16 out_width, u16 out_height, u32 fourcc,
2472 u8 rotation, u8 zorder, u8 pre_mult_alpha,
2473 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2474 bool replication, const struct videomode *vm,
2475 bool mem_to_mem)
2476 {
2477 bool five_taps = true;
2478 bool fieldmode = false;
2479 int r, cconv = 0;
2480 unsigned offset0, offset1;
2481 s32 row_inc;
2482 s32 pix_inc;
2483 u16 frame_width, frame_height;
2484 unsigned int field_offset = 0;
2485 u16 in_height = height;
2486 u16 in_width = width;
2487 int x_predecim = 1, y_predecim = 1;
2488 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2489 unsigned long pclk = dispc_plane_pclk_rate(plane);
2490 unsigned long lclk = dispc_plane_lclk_rate(plane);
2491
2492 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2493 return -EINVAL;
2494
2495 if (format_is_yuv(fourcc) && (in_width & 1)) {
2496 DSSERR("input width %d is not even for YUV format\n", in_width);
2497 return -EINVAL;
2498 }
2499
2500 out_width = out_width == 0 ? width : out_width;
2501 out_height = out_height == 0 ? height : out_height;
2502
2503 if (ilace && height == out_height)
2504 fieldmode = true;
2505
2506 if (ilace) {
2507 if (fieldmode)
2508 in_height /= 2;
2509 pos_y /= 2;
2510 out_height /= 2;
2511
2512 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2513 "out_height %d\n", in_height, pos_y,
2514 out_height);
2515 }
2516
2517 if (!dispc_ovl_color_mode_supported(plane, fourcc))
2518 return -EINVAL;
2519
2520 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width,
2521 in_height, out_width, out_height, fourcc,
2522 &five_taps, &x_predecim, &y_predecim, pos_x,
2523 rotation_type, mem_to_mem);
2524 if (r)
2525 return r;
2526
2527 in_width = in_width / x_predecim;
2528 in_height = in_height / y_predecim;
2529
2530 if (x_predecim > 1 || y_predecim > 1)
2531 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2532 x_predecim, y_predecim, in_width, in_height);
2533
2534 if (format_is_yuv(fourcc) && (in_width & 1)) {
2535 DSSDBG("predecimated input width is not even for YUV format\n");
2536 DSSDBG("adjusting input width %d -> %d\n",
2537 in_width, in_width & ~1);
2538
2539 in_width &= ~1;
2540 }
2541
2542 if (format_is_yuv(fourcc))
2543 cconv = 1;
2544
2545 if (ilace && !fieldmode) {
2546 /*
2547 * when downscaling the bottom field may have to start several
2548 * source lines below the top field. Unfortunately ACCUI
2549 * registers will only hold the fractional part of the offset
2550 * so the integer part must be added to the base address of the
2551 * bottom field.
2552 */
2553 if (!in_height || in_height == out_height)
2554 field_offset = 0;
2555 else
2556 field_offset = in_height / out_height / 2;
2557 }
2558
2559 /* Fields are independent but interleaved in memory. */
2560 if (fieldmode)
2561 field_offset = 1;
2562
2563 offset0 = 0;
2564 offset1 = 0;
2565 row_inc = 0;
2566 pix_inc = 0;
2567
2568 if (plane == OMAP_DSS_WB) {
2569 frame_width = out_width;
2570 frame_height = out_height;
2571 } else {
2572 frame_width = in_width;
2573 frame_height = height;
2574 }
2575
2576 calc_offset(screen_width, frame_width,
2577 fourcc, fieldmode, field_offset,
2578 &offset0, &offset1, &row_inc, &pix_inc,
2579 x_predecim, y_predecim,
2580 rotation_type, rotation);
2581
2582 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2583 offset0, offset1, row_inc, pix_inc);
2584
2585 dispc_ovl_set_color_mode(plane, fourcc);
2586
2587 dispc_ovl_configure_burst_type(plane, rotation_type);
2588
2589 if (dispc.feat->reverse_ilace_field_order)
2590 swap(offset0, offset1);
2591
2592 dispc_ovl_set_ba0(plane, paddr + offset0);
2593 dispc_ovl_set_ba1(plane, paddr + offset1);
2594
2595 if (fourcc == DRM_FORMAT_NV12) {
2596 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2597 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2598 }
2599
2600 if (dispc.feat->last_pixel_inc_missing)
2601 row_inc += pix_inc - 1;
2602
2603 dispc_ovl_set_row_inc(plane, row_inc);
2604 dispc_ovl_set_pix_inc(plane, pix_inc);
2605
2606 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2607 in_height, out_width, out_height);
2608
2609 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2610
2611 dispc_ovl_set_input_size(plane, in_width, in_height);
2612
2613 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2614 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2615 out_height, ilace, five_taps, fieldmode,
2616 fourcc, rotation);
2617 dispc_ovl_set_output_size(plane, out_width, out_height);
2618 dispc_ovl_set_vid_color_conv(plane, cconv);
2619 }
2620
2621 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc);
2622
2623 dispc_ovl_set_zorder(plane, caps, zorder);
2624 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2625 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2626
2627 dispc_ovl_enable_replication(plane, caps, replication);
2628
2629 return 0;
2630 }
2631
2632 static int dispc_ovl_setup(enum omap_plane_id plane,
2633 const struct omap_overlay_info *oi,
2634 const struct videomode *vm, bool mem_to_mem,
2635 enum omap_channel channel)
2636 {
2637 int r;
2638 enum omap_overlay_caps caps = dispc.feat->overlay_caps[plane];
2639 const bool replication = true;
2640
2641 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2642 " %dx%d, cmode %x, rot %d, chan %d repl %d\n",
2643 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2644 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2645 oi->fourcc, oi->rotation, channel, replication);
2646
2647 dispc_ovl_set_channel_out(plane, channel);
2648
2649 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2650 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2651 oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
2652 oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2653 oi->rotation_type, replication, vm, mem_to_mem);
2654
2655 return r;
2656 }
2657
2658 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2659 bool mem_to_mem, const struct videomode *vm)
2660 {
2661 int r;
2662 u32 l;
2663 enum omap_plane_id plane = OMAP_DSS_WB;
2664 const int pos_x = 0, pos_y = 0;
2665 const u8 zorder = 0, global_alpha = 0;
2666 const bool replication = true;
2667 bool truncation;
2668 int in_width = vm->hactive;
2669 int in_height = vm->vactive;
2670 enum omap_overlay_caps caps =
2671 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2672
2673 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2674 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
2675 in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
2676
2677 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2678 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2679 wi->height, wi->fourcc, wi->rotation, zorder,
2680 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2681 replication, vm, mem_to_mem);
2682
2683 switch (wi->fourcc) {
2684 case DRM_FORMAT_RGB565:
2685 case DRM_FORMAT_RGB888:
2686 case DRM_FORMAT_ARGB4444:
2687 case DRM_FORMAT_RGBA4444:
2688 case DRM_FORMAT_RGBX4444:
2689 case DRM_FORMAT_ARGB1555:
2690 case DRM_FORMAT_XRGB1555:
2691 case DRM_FORMAT_XRGB4444:
2692 truncation = true;
2693 break;
2694 default:
2695 truncation = false;
2696 break;
2697 }
2698
2699 /* setup extra DISPC_WB_ATTRIBUTES */
2700 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2701 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2702 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2703 if (mem_to_mem)
2704 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2705 else
2706 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2707 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2708
2709 if (mem_to_mem) {
2710 /* WBDELAYCOUNT */
2711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2712 } else {
2713 int wbdelay;
2714
2715 wbdelay = min(vm->vfront_porch +
2716 vm->vsync_len + vm->vback_porch, (u32)255);
2717
2718 /* WBDELAYCOUNT */
2719 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2720 }
2721
2722 return r;
2723 }
2724
2725 static int dispc_ovl_enable(enum omap_plane_id plane, bool enable)
2726 {
2727 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2728
2729 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2730
2731 return 0;
2732 }
2733
2734 static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2735 {
2736 return dss_get_supported_outputs(channel);
2737 }
2738
2739 static void dispc_lcd_enable_signal_polarity(bool act_high)
2740 {
2741 if (!dispc_has_feature(FEAT_LCDENABLEPOL))
2742 return;
2743
2744 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2745 }
2746
2747 void dispc_lcd_enable_signal(bool enable)
2748 {
2749 if (!dispc_has_feature(FEAT_LCDENABLESIGNAL))
2750 return;
2751
2752 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2753 }
2754
2755 void dispc_pck_free_enable(bool enable)
2756 {
2757 if (!dispc_has_feature(FEAT_PCKFREEENABLE))
2758 return;
2759
2760 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2761 }
2762
2763 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2764 {
2765 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2766 }
2767
2768
2769 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2770 {
2771 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2772 }
2773
2774 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2775 {
2776 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2777 }
2778
2779
2780 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2781 {
2782 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2783 }
2784
2785 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2786 enum omap_dss_trans_key_type type,
2787 u32 trans_key)
2788 {
2789 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2790
2791 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2792 }
2793
2794 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2795 {
2796 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2797 }
2798
2799 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2800 bool enable)
2801 {
2802 if (!dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2803 return;
2804
2805 if (ch == OMAP_DSS_CHANNEL_LCD)
2806 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2807 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2808 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2809 }
2810
2811 static void dispc_mgr_setup(enum omap_channel channel,
2812 const struct omap_overlay_manager_info *info)
2813 {
2814 dispc_mgr_set_default_color(channel, info->default_color);
2815 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2816 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2817 dispc_mgr_enable_alpha_fixed_zorder(channel,
2818 info->partial_alpha_enabled);
2819 if (dispc_has_feature(FEAT_CPR)) {
2820 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2821 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2822 }
2823 }
2824
2825 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2826 {
2827 int code;
2828
2829 switch (data_lines) {
2830 case 12:
2831 code = 0;
2832 break;
2833 case 16:
2834 code = 1;
2835 break;
2836 case 18:
2837 code = 2;
2838 break;
2839 case 24:
2840 code = 3;
2841 break;
2842 default:
2843 BUG();
2844 return;
2845 }
2846
2847 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2848 }
2849
2850 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2851 {
2852 u32 l;
2853 int gpout0, gpout1;
2854
2855 switch (mode) {
2856 case DSS_IO_PAD_MODE_RESET:
2857 gpout0 = 0;
2858 gpout1 = 0;
2859 break;
2860 case DSS_IO_PAD_MODE_RFBI:
2861 gpout0 = 1;
2862 gpout1 = 0;
2863 break;
2864 case DSS_IO_PAD_MODE_BYPASS:
2865 gpout0 = 1;
2866 gpout1 = 1;
2867 break;
2868 default:
2869 BUG();
2870 return;
2871 }
2872
2873 l = dispc_read_reg(DISPC_CONTROL);
2874 l = FLD_MOD(l, gpout0, 15, 15);
2875 l = FLD_MOD(l, gpout1, 16, 16);
2876 dispc_write_reg(DISPC_CONTROL, l);
2877 }
2878
2879 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2880 {
2881 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2882 }
2883
2884 static void dispc_mgr_set_lcd_config(enum omap_channel channel,
2885 const struct dss_lcd_mgr_config *config)
2886 {
2887 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2888
2889 dispc_mgr_enable_stallmode(channel, config->stallmode);
2890 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2891
2892 dispc_mgr_set_clock_div(channel, &config->clock_info);
2893
2894 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2895
2896 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2897
2898 dispc_mgr_set_lcd_type_tft(channel);
2899 }
2900
2901 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2902 {
2903 return width <= dispc.feat->mgr_width_max &&
2904 height <= dispc.feat->mgr_height_max;
2905 }
2906
2907 static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
2908 int vsw, int vfp, int vbp)
2909 {
2910 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
2911 hfp < 1 || hfp > dispc.feat->hp_max ||
2912 hbp < 1 || hbp > dispc.feat->hp_max ||
2913 vsw < 1 || vsw > dispc.feat->sw_max ||
2914 vfp < 0 || vfp > dispc.feat->vp_max ||
2915 vbp < 0 || vbp > dispc.feat->vp_max)
2916 return false;
2917 return true;
2918 }
2919
2920 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2921 unsigned long pclk)
2922 {
2923 if (dss_mgr_is_lcd(channel))
2924 return pclk <= dispc.feat->max_lcd_pclk;
2925 else
2926 return pclk <= dispc.feat->max_tv_pclk;
2927 }
2928
2929 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
2930 {
2931 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive))
2932 return false;
2933
2934 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock))
2935 return false;
2936
2937 if (dss_mgr_is_lcd(channel)) {
2938 /* TODO: OMAP4+ supports interlace for LCD outputs */
2939 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2940 return false;
2941
2942 if (!_dispc_lcd_timings_ok(vm->hsync_len,
2943 vm->hfront_porch, vm->hback_porch,
2944 vm->vsync_len, vm->vfront_porch,
2945 vm->vback_porch))
2946 return false;
2947 }
2948
2949 return true;
2950 }
2951
2952 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
2953 const struct videomode *vm)
2954 {
2955 u32 timing_h, timing_v, l;
2956 bool onoff, rf, ipc, vs, hs, de;
2957
2958 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) |
2959 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) |
2960 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20);
2961 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) |
2962 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) |
2963 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20);
2964
2965 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2966 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2967
2968 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
2969 vs = false;
2970 else
2971 vs = true;
2972
2973 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
2974 hs = false;
2975 else
2976 hs = true;
2977
2978 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
2979 de = false;
2980 else
2981 de = true;
2982
2983 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2984 ipc = false;
2985 else
2986 ipc = true;
2987
2988 /* always use the 'rf' setting */
2989 onoff = true;
2990
2991 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
2992 rf = true;
2993 else
2994 rf = false;
2995
2996 l = FLD_VAL(onoff, 17, 17) |
2997 FLD_VAL(rf, 16, 16) |
2998 FLD_VAL(de, 15, 15) |
2999 FLD_VAL(ipc, 14, 14) |
3000 FLD_VAL(hs, 13, 13) |
3001 FLD_VAL(vs, 12, 12);
3002
3003 /* always set ALIGN bit when available */
3004 if (dispc.feat->supports_sync_align)
3005 l |= (1 << 18);
3006
3007 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3008
3009 if (dispc.syscon_pol) {
3010 const int shifts[] = {
3011 [OMAP_DSS_CHANNEL_LCD] = 0,
3012 [OMAP_DSS_CHANNEL_LCD2] = 1,
3013 [OMAP_DSS_CHANNEL_LCD3] = 2,
3014 };
3015
3016 u32 mask, val;
3017
3018 mask = (1 << 0) | (1 << 3) | (1 << 6);
3019 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3020
3021 mask <<= 16 + shifts[channel];
3022 val <<= 16 + shifts[channel];
3023
3024 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3025 mask, val);
3026 }
3027 }
3028
3029 static int vm_flag_to_int(enum display_flags flags, enum display_flags high,
3030 enum display_flags low)
3031 {
3032 if (flags & high)
3033 return 1;
3034 if (flags & low)
3035 return -1;
3036 return 0;
3037 }
3038
3039 /* change name to mode? */
3040 static void dispc_mgr_set_timings(enum omap_channel channel,
3041 const struct videomode *vm)
3042 {
3043 unsigned xtot, ytot;
3044 unsigned long ht, vt;
3045 struct videomode t = *vm;
3046
3047 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3048
3049 if (!dispc_mgr_timings_ok(channel, &t)) {
3050 BUG();
3051 return;
3052 }
3053
3054 if (dss_mgr_is_lcd(channel)) {
3055 _dispc_mgr_set_lcd_timings(channel, &t);
3056
3057 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3058 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3059
3060 ht = vm->pixelclock / xtot;
3061 vt = vm->pixelclock / xtot / ytot;
3062
3063 DSSDBG("pck %lu\n", vm->pixelclock);
3064 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3065 t.hsync_len, t.hfront_porch, t.hback_porch,
3066 t.vsync_len, t.vfront_porch, t.vback_porch);
3067 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3068 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW),
3069 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW),
3070 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE),
3071 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW),
3072 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE));
3073
3074 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3075 } else {
3076 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3077 t.vactive /= 2;
3078
3079 if (dispc.feat->supports_double_pixel)
3080 REG_FLD_MOD(DISPC_CONTROL,
3081 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3082 19, 17);
3083 }
3084
3085 dispc_mgr_set_size(channel, t.hactive, t.vactive);
3086 }
3087
3088 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3089 u16 pck_div)
3090 {
3091 BUG_ON(lck_div < 1);
3092 BUG_ON(pck_div < 1);
3093
3094 dispc_write_reg(DISPC_DIVISORo(channel),
3095 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3096
3097 if (!dispc_has_feature(FEAT_CORE_CLK_DIV) &&
3098 channel == OMAP_DSS_CHANNEL_LCD)
3099 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3100 }
3101
3102 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3103 int *pck_div)
3104 {
3105 u32 l;
3106 l = dispc_read_reg(DISPC_DIVISORo(channel));
3107 *lck_div = FLD_GET(l, 23, 16);
3108 *pck_div = FLD_GET(l, 7, 0);
3109 }
3110
3111 static unsigned long dispc_fclk_rate(void)
3112 {
3113 unsigned long r;
3114 enum dss_clk_source src;
3115
3116 src = dss_get_dispc_clk_source();
3117
3118 if (src == DSS_CLK_SRC_FCK) {
3119 r = dss_get_dispc_clk_rate();
3120 } else {
3121 struct dss_pll *pll;
3122 unsigned clkout_idx;
3123
3124 pll = dss_pll_find_by_src(src);
3125 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3126
3127 r = pll->cinfo.clkout[clkout_idx];
3128 }
3129
3130 return r;
3131 }
3132
3133 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3134 {
3135 int lcd;
3136 unsigned long r;
3137 enum dss_clk_source src;
3138
3139 /* for TV, LCLK rate is the FCLK rate */
3140 if (!dss_mgr_is_lcd(channel))
3141 return dispc_fclk_rate();
3142
3143 src = dss_get_lcd_clk_source(channel);
3144
3145 if (src == DSS_CLK_SRC_FCK) {
3146 r = dss_get_dispc_clk_rate();
3147 } else {
3148 struct dss_pll *pll;
3149 unsigned clkout_idx;
3150
3151 pll = dss_pll_find_by_src(src);
3152 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3153
3154 r = pll->cinfo.clkout[clkout_idx];
3155 }
3156
3157 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3158
3159 return r / lcd;
3160 }
3161
3162 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3163 {
3164 unsigned long r;
3165
3166 if (dss_mgr_is_lcd(channel)) {
3167 int pcd;
3168 u32 l;
3169
3170 l = dispc_read_reg(DISPC_DIVISORo(channel));
3171
3172 pcd = FLD_GET(l, 7, 0);
3173
3174 r = dispc_mgr_lclk_rate(channel);
3175
3176 return r / pcd;
3177 } else {
3178 return dispc.tv_pclk_rate;
3179 }
3180 }
3181
3182 void dispc_set_tv_pclk(unsigned long pclk)
3183 {
3184 dispc.tv_pclk_rate = pclk;
3185 }
3186
3187 static unsigned long dispc_core_clk_rate(void)
3188 {
3189 return dispc.core_clk_rate;
3190 }
3191
3192 static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane)
3193 {
3194 enum omap_channel channel;
3195
3196 if (plane == OMAP_DSS_WB)
3197 return 0;
3198
3199 channel = dispc_ovl_get_channel_out(plane);
3200
3201 return dispc_mgr_pclk_rate(channel);
3202 }
3203
3204 static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane)
3205 {
3206 enum omap_channel channel;
3207
3208 if (plane == OMAP_DSS_WB)
3209 return 0;
3210
3211 channel = dispc_ovl_get_channel_out(plane);
3212
3213 return dispc_mgr_lclk_rate(channel);
3214 }
3215
3216 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3217 {
3218 int lcd, pcd;
3219 enum dss_clk_source lcd_clk_src;
3220
3221 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3222
3223 lcd_clk_src = dss_get_lcd_clk_source(channel);
3224
3225 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3226 dss_get_clk_source_name(lcd_clk_src));
3227
3228 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3229
3230 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3231 dispc_mgr_lclk_rate(channel), lcd);
3232 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3233 dispc_mgr_pclk_rate(channel), pcd);
3234 }
3235
3236 void dispc_dump_clocks(struct seq_file *s)
3237 {
3238 int lcd;
3239 u32 l;
3240 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3241
3242 if (dispc_runtime_get())
3243 return;
3244
3245 seq_printf(s, "- DISPC -\n");
3246
3247 seq_printf(s, "dispc fclk source = %s\n",
3248 dss_get_clk_source_name(dispc_clk_src));
3249
3250 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3251
3252 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) {
3253 seq_printf(s, "- DISPC-CORE-CLK -\n");
3254 l = dispc_read_reg(DISPC_DIVISOR);
3255 lcd = FLD_GET(l, 23, 16);
3256
3257 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3258 (dispc_fclk_rate()/lcd), lcd);
3259 }
3260
3261 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3262
3263 if (dispc_has_feature(FEAT_MGR_LCD2))
3264 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3265 if (dispc_has_feature(FEAT_MGR_LCD3))
3266 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3267
3268 dispc_runtime_put();
3269 }
3270
3271 static void dispc_dump_regs(struct seq_file *s)
3272 {
3273 int i, j;
3274 const char *mgr_names[] = {
3275 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3276 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3277 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3278 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3279 };
3280 const char *ovl_names[] = {
3281 [OMAP_DSS_GFX] = "GFX",
3282 [OMAP_DSS_VIDEO1] = "VID1",
3283 [OMAP_DSS_VIDEO2] = "VID2",
3284 [OMAP_DSS_VIDEO3] = "VID3",
3285 [OMAP_DSS_WB] = "WB",
3286 };
3287 const char **p_names;
3288
3289 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3290
3291 if (dispc_runtime_get())
3292 return;
3293
3294 /* DISPC common registers */
3295 DUMPREG(DISPC_REVISION);
3296 DUMPREG(DISPC_SYSCONFIG);
3297 DUMPREG(DISPC_SYSSTATUS);
3298 DUMPREG(DISPC_IRQSTATUS);
3299 DUMPREG(DISPC_IRQENABLE);
3300 DUMPREG(DISPC_CONTROL);
3301 DUMPREG(DISPC_CONFIG);
3302 DUMPREG(DISPC_CAPABLE);
3303 DUMPREG(DISPC_LINE_STATUS);
3304 DUMPREG(DISPC_LINE_NUMBER);
3305 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3306 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER))
3307 DUMPREG(DISPC_GLOBAL_ALPHA);
3308 if (dispc_has_feature(FEAT_MGR_LCD2)) {
3309 DUMPREG(DISPC_CONTROL2);
3310 DUMPREG(DISPC_CONFIG2);
3311 }
3312 if (dispc_has_feature(FEAT_MGR_LCD3)) {
3313 DUMPREG(DISPC_CONTROL3);
3314 DUMPREG(DISPC_CONFIG3);
3315 }
3316 if (dispc_has_feature(FEAT_MFLAG))
3317 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3318
3319 #undef DUMPREG
3320
3321 #define DISPC_REG(i, name) name(i)
3322 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3323 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3324 dispc_read_reg(DISPC_REG(i, r)))
3325
3326 p_names = mgr_names;
3327
3328 /* DISPC channel specific registers */
3329 for (i = 0; i < dispc_get_num_mgrs(); i++) {
3330 DUMPREG(i, DISPC_DEFAULT_COLOR);
3331 DUMPREG(i, DISPC_TRANS_COLOR);
3332 DUMPREG(i, DISPC_SIZE_MGR);
3333
3334 if (i == OMAP_DSS_CHANNEL_DIGIT)
3335 continue;
3336
3337 DUMPREG(i, DISPC_TIMING_H);
3338 DUMPREG(i, DISPC_TIMING_V);
3339 DUMPREG(i, DISPC_POL_FREQ);
3340 DUMPREG(i, DISPC_DIVISORo);
3341
3342 DUMPREG(i, DISPC_DATA_CYCLE1);
3343 DUMPREG(i, DISPC_DATA_CYCLE2);
3344 DUMPREG(i, DISPC_DATA_CYCLE3);
3345
3346 if (dispc_has_feature(FEAT_CPR)) {
3347 DUMPREG(i, DISPC_CPR_COEF_R);
3348 DUMPREG(i, DISPC_CPR_COEF_G);
3349 DUMPREG(i, DISPC_CPR_COEF_B);
3350 }
3351 }
3352
3353 p_names = ovl_names;
3354
3355 for (i = 0; i < dispc_get_num_ovls(); i++) {
3356 DUMPREG(i, DISPC_OVL_BA0);
3357 DUMPREG(i, DISPC_OVL_BA1);
3358 DUMPREG(i, DISPC_OVL_POSITION);
3359 DUMPREG(i, DISPC_OVL_SIZE);
3360 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3361 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3362 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3363 DUMPREG(i, DISPC_OVL_ROW_INC);
3364 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3365
3366 if (dispc_has_feature(FEAT_PRELOAD))
3367 DUMPREG(i, DISPC_OVL_PRELOAD);
3368 if (dispc_has_feature(FEAT_MFLAG))
3369 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3370
3371 if (i == OMAP_DSS_GFX) {
3372 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3373 DUMPREG(i, DISPC_OVL_TABLE_BA);
3374 continue;
3375 }
3376
3377 DUMPREG(i, DISPC_OVL_FIR);
3378 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3379 DUMPREG(i, DISPC_OVL_ACCU0);
3380 DUMPREG(i, DISPC_OVL_ACCU1);
3381 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3382 DUMPREG(i, DISPC_OVL_BA0_UV);
3383 DUMPREG(i, DISPC_OVL_BA1_UV);
3384 DUMPREG(i, DISPC_OVL_FIR2);
3385 DUMPREG(i, DISPC_OVL_ACCU2_0);
3386 DUMPREG(i, DISPC_OVL_ACCU2_1);
3387 }
3388 if (dispc_has_feature(FEAT_ATTR2))
3389 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3390 }
3391
3392 if (dispc.feat->has_writeback) {
3393 i = OMAP_DSS_WB;
3394 DUMPREG(i, DISPC_OVL_BA0);
3395 DUMPREG(i, DISPC_OVL_BA1);
3396 DUMPREG(i, DISPC_OVL_SIZE);
3397 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3398 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3399 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3400 DUMPREG(i, DISPC_OVL_ROW_INC);
3401 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3402
3403 if (dispc_has_feature(FEAT_MFLAG))
3404 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3405
3406 DUMPREG(i, DISPC_OVL_FIR);
3407 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3408 DUMPREG(i, DISPC_OVL_ACCU0);
3409 DUMPREG(i, DISPC_OVL_ACCU1);
3410 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3411 DUMPREG(i, DISPC_OVL_BA0_UV);
3412 DUMPREG(i, DISPC_OVL_BA1_UV);
3413 DUMPREG(i, DISPC_OVL_FIR2);
3414 DUMPREG(i, DISPC_OVL_ACCU2_0);
3415 DUMPREG(i, DISPC_OVL_ACCU2_1);
3416 }
3417 if (dispc_has_feature(FEAT_ATTR2))
3418 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3419 }
3420
3421 #undef DISPC_REG
3422 #undef DUMPREG
3423
3424 #define DISPC_REG(plane, name, i) name(plane, i)
3425 #define DUMPREG(plane, name, i) \
3426 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3427 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3428 dispc_read_reg(DISPC_REG(plane, name, i)))
3429
3430 /* Video pipeline coefficient registers */
3431
3432 /* start from OMAP_DSS_VIDEO1 */
3433 for (i = 1; i < dispc_get_num_ovls(); i++) {
3434 for (j = 0; j < 8; j++)
3435 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3436
3437 for (j = 0; j < 8; j++)
3438 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3439
3440 for (j = 0; j < 5; j++)
3441 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3442
3443 if (dispc_has_feature(FEAT_FIR_COEF_V)) {
3444 for (j = 0; j < 8; j++)
3445 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3446 }
3447
3448 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3449 for (j = 0; j < 8; j++)
3450 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3451
3452 for (j = 0; j < 8; j++)
3453 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3454
3455 for (j = 0; j < 8; j++)
3456 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3457 }
3458 }
3459
3460 dispc_runtime_put();
3461
3462 #undef DISPC_REG
3463 #undef DUMPREG
3464 }
3465
3466 /* calculate clock rates using dividers in cinfo */
3467 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3468 struct dispc_clock_info *cinfo)
3469 {
3470 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3471 return -EINVAL;
3472 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3473 return -EINVAL;
3474
3475 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3476 cinfo->pck = cinfo->lck / cinfo->pck_div;
3477
3478 return 0;
3479 }
3480
3481 bool dispc_div_calc(unsigned long dispc_freq,
3482 unsigned long pck_min, unsigned long pck_max,
3483 dispc_div_calc_func func, void *data)
3484 {
3485 int lckd, lckd_start, lckd_stop;
3486 int pckd, pckd_start, pckd_stop;
3487 unsigned long pck, lck;
3488 unsigned long lck_max;
3489 unsigned long pckd_hw_min, pckd_hw_max;
3490 unsigned min_fck_per_pck;
3491 unsigned long fck;
3492
3493 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3494 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3495 #else
3496 min_fck_per_pck = 0;
3497 #endif
3498
3499 pckd_hw_min = dispc.feat->min_pcd;
3500 pckd_hw_max = 255;
3501
3502 lck_max = dss_get_max_fck_rate();
3503
3504 pck_min = pck_min ? pck_min : 1;
3505 pck_max = pck_max ? pck_max : ULONG_MAX;
3506
3507 lckd_start = max(DIV_ROUND_UP(dispc_freq, lck_max), 1ul);
3508 lckd_stop = min(dispc_freq / pck_min, 255ul);
3509
3510 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3511 lck = dispc_freq / lckd;
3512
3513 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3514 pckd_stop = min(lck / pck_min, pckd_hw_max);
3515
3516 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3517 pck = lck / pckd;
3518
3519 /*
3520 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3521 * clock, which means we're configuring DISPC fclk here
3522 * also. Thus we need to use the calculated lck. For
3523 * OMAP4+ the DISPC fclk is a separate clock.
3524 */
3525 if (dispc_has_feature(FEAT_CORE_CLK_DIV))
3526 fck = dispc_core_clk_rate();
3527 else
3528 fck = lck;
3529
3530 if (fck < pck * min_fck_per_pck)
3531 continue;
3532
3533 if (func(lckd, pckd, lck, pck, data))
3534 return true;
3535 }
3536 }
3537
3538 return false;
3539 }
3540
3541 void dispc_mgr_set_clock_div(enum omap_channel channel,
3542 const struct dispc_clock_info *cinfo)
3543 {
3544 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3545 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3546
3547 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3548 }
3549
3550 int dispc_mgr_get_clock_div(enum omap_channel channel,
3551 struct dispc_clock_info *cinfo)
3552 {
3553 unsigned long fck;
3554
3555 fck = dispc_fclk_rate();
3556
3557 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3558 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3559
3560 cinfo->lck = fck / cinfo->lck_div;
3561 cinfo->pck = cinfo->lck / cinfo->pck_div;
3562
3563 return 0;
3564 }
3565
3566 static u32 dispc_read_irqstatus(void)
3567 {
3568 return dispc_read_reg(DISPC_IRQSTATUS);
3569 }
3570
3571 static void dispc_clear_irqstatus(u32 mask)
3572 {
3573 dispc_write_reg(DISPC_IRQSTATUS, mask);
3574 }
3575
3576 static void dispc_write_irqenable(u32 mask)
3577 {
3578 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3579
3580 /* clear the irqstatus for newly enabled irqs */
3581 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3582
3583 dispc_write_reg(DISPC_IRQENABLE, mask);
3584
3585 /* flush posted write */
3586 dispc_read_reg(DISPC_IRQENABLE);
3587 }
3588
3589 void dispc_enable_sidle(void)
3590 {
3591 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3592 }
3593
3594 void dispc_disable_sidle(void)
3595 {
3596 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3597 }
3598
3599 static u32 dispc_mgr_gamma_size(enum omap_channel channel)
3600 {
3601 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3602
3603 if (!dispc.feat->has_gamma_table)
3604 return 0;
3605
3606 return gdesc->len;
3607 }
3608
3609 static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3610 {
3611 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3612 u32 *table = dispc.gamma_table[channel];
3613 unsigned int i;
3614
3615 DSSDBG("%s: channel %d\n", __func__, channel);
3616
3617 for (i = 0; i < gdesc->len; ++i) {
3618 u32 v = table[i];
3619
3620 if (gdesc->has_index)
3621 v |= i << 24;
3622 else if (i == 0)
3623 v |= 1 << 31;
3624
3625 dispc_write_reg(gdesc->reg, v);
3626 }
3627 }
3628
3629 static void dispc_restore_gamma_tables(void)
3630 {
3631 DSSDBG("%s()\n", __func__);
3632
3633 if (!dispc.feat->has_gamma_table)
3634 return;
3635
3636 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD);
3637
3638 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT);
3639
3640 if (dispc_has_feature(FEAT_MGR_LCD2))
3641 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2);
3642
3643 if (dispc_has_feature(FEAT_MGR_LCD3))
3644 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3);
3645 }
3646
3647 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3648 { .red = 0, .green = 0, .blue = 0, },
3649 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3650 };
3651
3652 static void dispc_mgr_set_gamma(enum omap_channel channel,
3653 const struct drm_color_lut *lut,
3654 unsigned int length)
3655 {
3656 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3657 u32 *table = dispc.gamma_table[channel];
3658 uint i;
3659
3660 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3661 channel, length, gdesc->len);
3662
3663 if (!dispc.feat->has_gamma_table)
3664 return;
3665
3666 if (lut == NULL || length < 2) {
3667 lut = dispc_mgr_gamma_default_lut;
3668 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3669 }
3670
3671 for (i = 0; i < length - 1; ++i) {
3672 uint first = i * (gdesc->len - 1) / (length - 1);
3673 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3674 uint w = last - first;
3675 u16 r, g, b;
3676 uint j;
3677
3678 if (w == 0)
3679 continue;
3680
3681 for (j = 0; j <= w; j++) {
3682 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3683 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3684 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3685
3686 r >>= 16 - gdesc->bits;
3687 g >>= 16 - gdesc->bits;
3688 b >>= 16 - gdesc->bits;
3689
3690 table[first + j] = (r << (gdesc->bits * 2)) |
3691 (g << gdesc->bits) | b;
3692 }
3693 }
3694
3695 if (dispc.is_enabled)
3696 dispc_mgr_write_gamma_table(channel);
3697 }
3698
3699 static int dispc_init_gamma_tables(void)
3700 {
3701 int channel;
3702
3703 if (!dispc.feat->has_gamma_table)
3704 return 0;
3705
3706 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) {
3707 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3708 u32 *gt;
3709
3710 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3711 !dispc_has_feature(FEAT_MGR_LCD2))
3712 continue;
3713
3714 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3715 !dispc_has_feature(FEAT_MGR_LCD3))
3716 continue;
3717
3718 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len,
3719 sizeof(u32), GFP_KERNEL);
3720 if (!gt)
3721 return -ENOMEM;
3722
3723 dispc.gamma_table[channel] = gt;
3724
3725 dispc_mgr_set_gamma(channel, NULL, 0);
3726 }
3727 return 0;
3728 }
3729
3730 static void _omap_dispc_initial_config(void)
3731 {
3732 u32 l;
3733
3734 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3735 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) {
3736 l = dispc_read_reg(DISPC_DIVISOR);
3737 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3738 l = FLD_MOD(l, 1, 0, 0);
3739 l = FLD_MOD(l, 1, 23, 16);
3740 dispc_write_reg(DISPC_DIVISOR, l);
3741
3742 dispc.core_clk_rate = dispc_fclk_rate();
3743 }
3744
3745 /* Use gamma table mode, instead of palette mode */
3746 if (dispc.feat->has_gamma_table)
3747 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3748
3749 /* For older DSS versions (FEAT_FUNCGATED) this enables
3750 * func-clock auto-gating. For newer versions
3751 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3752 */
3753 if (dispc_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
3754 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3755
3756 dispc_setup_color_conv_coef();
3757
3758 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3759
3760 dispc_init_fifos();
3761
3762 dispc_configure_burst_sizes();
3763
3764 dispc_ovl_enable_zorder_planes();
3765
3766 if (dispc.feat->mstandby_workaround)
3767 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3768
3769 if (dispc_has_feature(FEAT_MFLAG))
3770 dispc_init_mflag();
3771 }
3772
3773 static const enum dispc_feature_id omap2_dispc_features_list[] = {
3774 FEAT_LCDENABLEPOL,
3775 FEAT_LCDENABLESIGNAL,
3776 FEAT_PCKFREEENABLE,
3777 FEAT_FUNCGATED,
3778 FEAT_ROWREPEATENABLE,
3779 FEAT_RESIZECONF,
3780 };
3781
3782 static const enum dispc_feature_id omap3_dispc_features_list[] = {
3783 FEAT_LCDENABLEPOL,
3784 FEAT_LCDENABLESIGNAL,
3785 FEAT_PCKFREEENABLE,
3786 FEAT_FUNCGATED,
3787 FEAT_LINEBUFFERSPLIT,
3788 FEAT_ROWREPEATENABLE,
3789 FEAT_RESIZECONF,
3790 FEAT_CPR,
3791 FEAT_PRELOAD,
3792 FEAT_FIR_COEF_V,
3793 FEAT_ALPHA_FIXED_ZORDER,
3794 FEAT_FIFO_MERGE,
3795 FEAT_OMAP3_DSI_FIFO_BUG,
3796 };
3797
3798 static const enum dispc_feature_id am43xx_dispc_features_list[] = {
3799 FEAT_LCDENABLEPOL,
3800 FEAT_LCDENABLESIGNAL,
3801 FEAT_PCKFREEENABLE,
3802 FEAT_FUNCGATED,
3803 FEAT_LINEBUFFERSPLIT,
3804 FEAT_ROWREPEATENABLE,
3805 FEAT_RESIZECONF,
3806 FEAT_CPR,
3807 FEAT_PRELOAD,
3808 FEAT_FIR_COEF_V,
3809 FEAT_ALPHA_FIXED_ZORDER,
3810 FEAT_FIFO_MERGE,
3811 };
3812
3813 static const enum dispc_feature_id omap4_dispc_features_list[] = {
3814 FEAT_MGR_LCD2,
3815 FEAT_CORE_CLK_DIV,
3816 FEAT_HANDLE_UV_SEPARATE,
3817 FEAT_ATTR2,
3818 FEAT_CPR,
3819 FEAT_PRELOAD,
3820 FEAT_FIR_COEF_V,
3821 FEAT_ALPHA_FREE_ZORDER,
3822 FEAT_FIFO_MERGE,
3823 FEAT_BURST_2D,
3824 };
3825
3826 static const enum dispc_feature_id omap5_dispc_features_list[] = {
3827 FEAT_MGR_LCD2,
3828 FEAT_MGR_LCD3,
3829 FEAT_CORE_CLK_DIV,
3830 FEAT_HANDLE_UV_SEPARATE,
3831 FEAT_ATTR2,
3832 FEAT_CPR,
3833 FEAT_PRELOAD,
3834 FEAT_FIR_COEF_V,
3835 FEAT_ALPHA_FREE_ZORDER,
3836 FEAT_FIFO_MERGE,
3837 FEAT_BURST_2D,
3838 FEAT_MFLAG,
3839 };
3840
3841 static const struct dss_reg_field omap2_dispc_reg_fields[] = {
3842 [FEAT_REG_FIRHINC] = { 11, 0 },
3843 [FEAT_REG_FIRVINC] = { 27, 16 },
3844 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
3845 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
3846 [FEAT_REG_FIFOSIZE] = { 8, 0 },
3847 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
3848 [FEAT_REG_VERTICALACCU] = { 25, 16 },
3849 };
3850
3851 static const struct dss_reg_field omap3_dispc_reg_fields[] = {
3852 [FEAT_REG_FIRHINC] = { 12, 0 },
3853 [FEAT_REG_FIRVINC] = { 28, 16 },
3854 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
3855 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
3856 [FEAT_REG_FIFOSIZE] = { 10, 0 },
3857 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
3858 [FEAT_REG_VERTICALACCU] = { 25, 16 },
3859 };
3860
3861 static const struct dss_reg_field omap4_dispc_reg_fields[] = {
3862 [FEAT_REG_FIRHINC] = { 12, 0 },
3863 [FEAT_REG_FIRVINC] = { 28, 16 },
3864 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
3865 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
3866 [FEAT_REG_FIFOSIZE] = { 15, 0 },
3867 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
3868 [FEAT_REG_VERTICALACCU] = { 26, 16 },
3869 };
3870
3871 static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = {
3872 /* OMAP_DSS_GFX */
3873 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3874
3875 /* OMAP_DSS_VIDEO1 */
3876 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
3877 OMAP_DSS_OVL_CAP_REPLICATION,
3878
3879 /* OMAP_DSS_VIDEO2 */
3880 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
3881 OMAP_DSS_OVL_CAP_REPLICATION,
3882 };
3883
3884 static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = {
3885 /* OMAP_DSS_GFX */
3886 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
3887 OMAP_DSS_OVL_CAP_REPLICATION,
3888
3889 /* OMAP_DSS_VIDEO1 */
3890 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
3891 OMAP_DSS_OVL_CAP_REPLICATION,
3892
3893 /* OMAP_DSS_VIDEO2 */
3894 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
3895 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3896 };
3897
3898 static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = {
3899 /* OMAP_DSS_GFX */
3900 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
3901 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3902
3903 /* OMAP_DSS_VIDEO1 */
3904 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
3905 OMAP_DSS_OVL_CAP_REPLICATION,
3906
3907 /* OMAP_DSS_VIDEO2 */
3908 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
3909 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
3910 OMAP_DSS_OVL_CAP_REPLICATION,
3911 };
3912
3913 static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = {
3914 /* OMAP_DSS_GFX */
3915 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
3916 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
3917 OMAP_DSS_OVL_CAP_REPLICATION,
3918
3919 /* OMAP_DSS_VIDEO1 */
3920 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
3921 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
3922 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3923
3924 /* OMAP_DSS_VIDEO2 */
3925 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
3926 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
3927 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3928
3929 /* OMAP_DSS_VIDEO3 */
3930 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
3931 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
3932 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
3933 };
3934
3935 #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 }
3936
3937 static const u32 *omap2_dispc_supported_color_modes[] = {
3938
3939 /* OMAP_DSS_GFX */
3940 COLOR_ARRAY(
3941 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
3942 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888),
3943
3944 /* OMAP_DSS_VIDEO1 */
3945 COLOR_ARRAY(
3946 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
3947 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
3948 DRM_FORMAT_UYVY),
3949
3950 /* OMAP_DSS_VIDEO2 */
3951 COLOR_ARRAY(
3952 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
3953 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
3954 DRM_FORMAT_UYVY),
3955 };
3956
3957 static const u32 *omap3_dispc_supported_color_modes[] = {
3958 /* OMAP_DSS_GFX */
3959 COLOR_ARRAY(
3960 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
3961 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
3962 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
3963 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
3964
3965 /* OMAP_DSS_VIDEO1 */
3966 COLOR_ARRAY(
3967 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888,
3968 DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565,
3969 DRM_FORMAT_YUYV, DRM_FORMAT_UYVY),
3970
3971 /* OMAP_DSS_VIDEO2 */
3972 COLOR_ARRAY(
3973 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
3974 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
3975 DRM_FORMAT_RGB888, DRM_FORMAT_YUYV,
3976 DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888,
3977 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888),
3978 };
3979
3980 static const u32 *omap4_dispc_supported_color_modes[] = {
3981 /* OMAP_DSS_GFX */
3982 COLOR_ARRAY(
3983 DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444,
3984 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,
3985 DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888,
3986 DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888,
3987 DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444,
3988 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555),
3989
3990 /* OMAP_DSS_VIDEO1 */
3991 COLOR_ARRAY(
3992 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
3993 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
3994 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
3995 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
3996 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
3997 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
3998 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
3999 DRM_FORMAT_RGBX8888),
4000
4001 /* OMAP_DSS_VIDEO2 */
4002 COLOR_ARRAY(
4003 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4004 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4005 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4006 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4007 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4008 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4009 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4010 DRM_FORMAT_RGBX8888),
4011
4012 /* OMAP_DSS_VIDEO3 */
4013 COLOR_ARRAY(
4014 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4015 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4016 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4017 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4018 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4019 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4020 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4021 DRM_FORMAT_RGBX8888),
4022
4023 /* OMAP_DSS_WB */
4024 COLOR_ARRAY(
4025 DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444,
4026 DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555,
4027 DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12,
4028 DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888,
4029 DRM_FORMAT_RGB888, DRM_FORMAT_UYVY,
4030 DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555,
4031 DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444,
4032 DRM_FORMAT_RGBX8888),
4033 };
4034
4035 static const struct dispc_features omap24xx_dispc_feats = {
4036 .sw_start = 5,
4037 .fp_start = 15,
4038 .bp_start = 27,
4039 .sw_max = 64,
4040 .vp_max = 255,
4041 .hp_max = 256,
4042 .mgr_width_start = 10,
4043 .mgr_height_start = 26,
4044 .mgr_width_max = 2048,
4045 .mgr_height_max = 2048,
4046 .max_lcd_pclk = 66500000,
4047 .max_downscale = 2,
4048 /*
4049 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4050 * cannot scale an image width larger than 768.
4051 */
4052 .max_line_width = 768,
4053 .min_pcd = 2,
4054 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4055 .calc_core_clk = calc_core_clk_24xx,
4056 .num_fifos = 3,
4057 .features = omap2_dispc_features_list,
4058 .num_features = ARRAY_SIZE(omap2_dispc_features_list),
4059 .reg_fields = omap2_dispc_reg_fields,
4060 .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields),
4061 .overlay_caps = omap2_dispc_overlay_caps,
4062 .supported_color_modes = omap2_dispc_supported_color_modes,
4063 .num_mgrs = 2,
4064 .num_ovls = 3,
4065 .buffer_size_unit = 1,
4066 .burst_size_unit = 8,
4067 .no_framedone_tv = true,
4068 .set_max_preload = false,
4069 .last_pixel_inc_missing = true,
4070 };
4071
4072 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
4073 .sw_start = 5,
4074 .fp_start = 15,
4075 .bp_start = 27,
4076 .sw_max = 64,
4077 .vp_max = 255,
4078 .hp_max = 256,
4079 .mgr_width_start = 10,
4080 .mgr_height_start = 26,
4081 .mgr_width_max = 2048,
4082 .mgr_height_max = 2048,
4083 .max_lcd_pclk = 173000000,
4084 .max_tv_pclk = 59000000,
4085 .max_downscale = 4,
4086 .max_line_width = 1024,
4087 .min_pcd = 1,
4088 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4089 .calc_core_clk = calc_core_clk_34xx,
4090 .num_fifos = 3,
4091 .features = omap3_dispc_features_list,
4092 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4093 .reg_fields = omap3_dispc_reg_fields,
4094 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4095 .overlay_caps = omap3430_dispc_overlay_caps,
4096 .supported_color_modes = omap3_dispc_supported_color_modes,
4097 .num_mgrs = 2,
4098 .num_ovls = 3,
4099 .buffer_size_unit = 1,
4100 .burst_size_unit = 8,
4101 .no_framedone_tv = true,
4102 .set_max_preload = false,
4103 .last_pixel_inc_missing = true,
4104 };
4105
4106 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
4107 .sw_start = 7,
4108 .fp_start = 19,
4109 .bp_start = 31,
4110 .sw_max = 256,
4111 .vp_max = 4095,
4112 .hp_max = 4096,
4113 .mgr_width_start = 10,
4114 .mgr_height_start = 26,
4115 .mgr_width_max = 2048,
4116 .mgr_height_max = 2048,
4117 .max_lcd_pclk = 173000000,
4118 .max_tv_pclk = 59000000,
4119 .max_downscale = 4,
4120 .max_line_width = 1024,
4121 .min_pcd = 1,
4122 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4123 .calc_core_clk = calc_core_clk_34xx,
4124 .num_fifos = 3,
4125 .features = omap3_dispc_features_list,
4126 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4127 .reg_fields = omap3_dispc_reg_fields,
4128 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4129 .overlay_caps = omap3430_dispc_overlay_caps,
4130 .supported_color_modes = omap3_dispc_supported_color_modes,
4131 .num_mgrs = 2,
4132 .num_ovls = 3,
4133 .buffer_size_unit = 1,
4134 .burst_size_unit = 8,
4135 .no_framedone_tv = true,
4136 .set_max_preload = false,
4137 .last_pixel_inc_missing = true,
4138 };
4139
4140 static const struct dispc_features omap36xx_dispc_feats = {
4141 .sw_start = 7,
4142 .fp_start = 19,
4143 .bp_start = 31,
4144 .sw_max = 256,
4145 .vp_max = 4095,
4146 .hp_max = 4096,
4147 .mgr_width_start = 10,
4148 .mgr_height_start = 26,
4149 .mgr_width_max = 2048,
4150 .mgr_height_max = 2048,
4151 .max_lcd_pclk = 173000000,
4152 .max_tv_pclk = 59000000,
4153 .max_downscale = 4,
4154 .max_line_width = 1024,
4155 .min_pcd = 1,
4156 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4157 .calc_core_clk = calc_core_clk_34xx,
4158 .num_fifos = 3,
4159 .features = omap3_dispc_features_list,
4160 .num_features = ARRAY_SIZE(omap3_dispc_features_list),
4161 .reg_fields = omap3_dispc_reg_fields,
4162 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4163 .overlay_caps = omap3630_dispc_overlay_caps,
4164 .supported_color_modes = omap3_dispc_supported_color_modes,
4165 .num_mgrs = 2,
4166 .num_ovls = 3,
4167 .buffer_size_unit = 1,
4168 .burst_size_unit = 8,
4169 .no_framedone_tv = true,
4170 .set_max_preload = false,
4171 .last_pixel_inc_missing = true,
4172 };
4173
4174 static const struct dispc_features am43xx_dispc_feats = {
4175 .sw_start = 7,
4176 .fp_start = 19,
4177 .bp_start = 31,
4178 .sw_max = 256,
4179 .vp_max = 4095,
4180 .hp_max = 4096,
4181 .mgr_width_start = 10,
4182 .mgr_height_start = 26,
4183 .mgr_width_max = 2048,
4184 .mgr_height_max = 2048,
4185 .max_lcd_pclk = 173000000,
4186 .max_tv_pclk = 59000000,
4187 .max_downscale = 4,
4188 .max_line_width = 1024,
4189 .min_pcd = 1,
4190 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4191 .calc_core_clk = calc_core_clk_34xx,
4192 .num_fifos = 3,
4193 .features = am43xx_dispc_features_list,
4194 .num_features = ARRAY_SIZE(am43xx_dispc_features_list),
4195 .reg_fields = omap3_dispc_reg_fields,
4196 .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields),
4197 .overlay_caps = omap3430_dispc_overlay_caps,
4198 .supported_color_modes = omap3_dispc_supported_color_modes,
4199 .num_mgrs = 1,
4200 .num_ovls = 3,
4201 .buffer_size_unit = 1,
4202 .burst_size_unit = 8,
4203 .no_framedone_tv = true,
4204 .set_max_preload = false,
4205 .last_pixel_inc_missing = true,
4206 };
4207
4208 static const struct dispc_features omap44xx_dispc_feats = {
4209 .sw_start = 7,
4210 .fp_start = 19,
4211 .bp_start = 31,
4212 .sw_max = 256,
4213 .vp_max = 4095,
4214 .hp_max = 4096,
4215 .mgr_width_start = 10,
4216 .mgr_height_start = 26,
4217 .mgr_width_max = 2048,
4218 .mgr_height_max = 2048,
4219 .max_lcd_pclk = 170000000,
4220 .max_tv_pclk = 185625000,
4221 .max_downscale = 4,
4222 .max_line_width = 2048,
4223 .min_pcd = 1,
4224 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4225 .calc_core_clk = calc_core_clk_44xx,
4226 .num_fifos = 5,
4227 .features = omap4_dispc_features_list,
4228 .num_features = ARRAY_SIZE(omap4_dispc_features_list),
4229 .reg_fields = omap4_dispc_reg_fields,
4230 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
4231 .overlay_caps = omap4_dispc_overlay_caps,
4232 .supported_color_modes = omap4_dispc_supported_color_modes,
4233 .num_mgrs = 3,
4234 .num_ovls = 4,
4235 .buffer_size_unit = 16,
4236 .burst_size_unit = 16,
4237 .gfx_fifo_workaround = true,
4238 .set_max_preload = true,
4239 .supports_sync_align = true,
4240 .has_writeback = true,
4241 .supports_double_pixel = true,
4242 .reverse_ilace_field_order = true,
4243 .has_gamma_table = true,
4244 .has_gamma_i734_bug = true,
4245 };
4246
4247 static const struct dispc_features omap54xx_dispc_feats = {
4248 .sw_start = 7,
4249 .fp_start = 19,
4250 .bp_start = 31,
4251 .sw_max = 256,
4252 .vp_max = 4095,
4253 .hp_max = 4096,
4254 .mgr_width_start = 11,
4255 .mgr_height_start = 27,
4256 .mgr_width_max = 4096,
4257 .mgr_height_max = 4096,
4258 .max_lcd_pclk = 170000000,
4259 .max_tv_pclk = 186000000,
4260 .max_downscale = 4,
4261 .max_line_width = 2048,
4262 .min_pcd = 1,
4263 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4264 .calc_core_clk = calc_core_clk_44xx,
4265 .num_fifos = 5,
4266 .features = omap5_dispc_features_list,
4267 .num_features = ARRAY_SIZE(omap5_dispc_features_list),
4268 .reg_fields = omap4_dispc_reg_fields,
4269 .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields),
4270 .overlay_caps = omap4_dispc_overlay_caps,
4271 .supported_color_modes = omap4_dispc_supported_color_modes,
4272 .num_mgrs = 4,
4273 .num_ovls = 4,
4274 .buffer_size_unit = 16,
4275 .burst_size_unit = 16,
4276 .gfx_fifo_workaround = true,
4277 .mstandby_workaround = true,
4278 .set_max_preload = true,
4279 .supports_sync_align = true,
4280 .has_writeback = true,
4281 .supports_double_pixel = true,
4282 .reverse_ilace_field_order = true,
4283 .has_gamma_table = true,
4284 .has_gamma_i734_bug = true,
4285 };
4286
4287 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4288 {
4289 if (!dispc.is_enabled)
4290 return IRQ_NONE;
4291
4292 return dispc.user_handler(irq, dispc.user_data);
4293 }
4294
4295 static int dispc_request_irq(irq_handler_t handler, void *dev_id)
4296 {
4297 int r;
4298
4299 if (dispc.user_handler != NULL)
4300 return -EBUSY;
4301
4302 dispc.user_handler = handler;
4303 dispc.user_data = dev_id;
4304
4305 /* ensure the dispc_irq_handler sees the values above */
4306 smp_wmb();
4307
4308 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4309 IRQF_SHARED, "OMAP DISPC", &dispc);
4310 if (r) {
4311 dispc.user_handler = NULL;
4312 dispc.user_data = NULL;
4313 }
4314
4315 return r;
4316 }
4317
4318 static void dispc_free_irq(void *dev_id)
4319 {
4320 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4321
4322 dispc.user_handler = NULL;
4323 dispc.user_data = NULL;
4324 }
4325
4326 static u32 dispc_get_memory_bandwidth_limit(void)
4327 {
4328 u32 limit = 0;
4329
4330 /* Optional maximum memory bandwidth */
4331 of_property_read_u32(dispc.pdev->dev.of_node, "max-memory-bandwidth",
4332 &limit);
4333
4334 return limit;
4335 }
4336
4337 /*
4338 * Workaround for errata i734 in DSS dispc
4339 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4340 *
4341 * For gamma tables to work on LCD1 the GFX plane has to be used at
4342 * least once after DSS HW has come out of reset. The workaround
4343 * sets up a minimal LCD setup with GFX plane and waits for one
4344 * vertical sync irq before disabling the setup and continuing with
4345 * the context restore. The physical outputs are gated during the
4346 * operation. This workaround requires that gamma table's LOADMODE
4347 * is set to 0x2 in DISPC_CONTROL1 register.
4348 *
4349 * For details see:
4350 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4351 * Literature Number: SWPZ037E
4352 * Or some other relevant errata document for the DSS IP version.
4353 */
4354
4355 static const struct dispc_errata_i734_data {
4356 struct videomode vm;
4357 struct omap_overlay_info ovli;
4358 struct omap_overlay_manager_info mgri;
4359 struct dss_lcd_mgr_config lcd_conf;
4360 } i734 = {
4361 .vm = {
4362 .hactive = 8, .vactive = 1,
4363 .pixelclock = 16000000,
4364 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
4365 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
4366
4367 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4368 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
4369 DISPLAY_FLAGS_PIXDATA_POSEDGE,
4370 },
4371 .ovli = {
4372 .screen_width = 1,
4373 .width = 1, .height = 1,
4374 .fourcc = DRM_FORMAT_XRGB8888,
4375 .rotation = DRM_MODE_ROTATE_0,
4376 .rotation_type = OMAP_DSS_ROT_NONE,
4377 .pos_x = 0, .pos_y = 0,
4378 .out_width = 0, .out_height = 0,
4379 .global_alpha = 0xff,
4380 .pre_mult_alpha = 0,
4381 .zorder = 0,
4382 },
4383 .mgri = {
4384 .default_color = 0,
4385 .trans_enabled = false,
4386 .partial_alpha_enabled = false,
4387 .cpr_enable = false,
4388 },
4389 .lcd_conf = {
4390 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
4391 .stallmode = false,
4392 .fifohandcheck = false,
4393 .clock_info = {
4394 .lck_div = 1,
4395 .pck_div = 2,
4396 },
4397 .video_port_width = 24,
4398 .lcden_sig_polarity = 0,
4399 },
4400 };
4401
4402 static struct i734_buf {
4403 size_t size;
4404 dma_addr_t paddr;
4405 void *vaddr;
4406 } i734_buf;
4407
4408 static int dispc_errata_i734_wa_init(void)
4409 {
4410 if (!dispc.feat->has_gamma_i734_bug)
4411 return 0;
4412
4413 i734_buf.size = i734.ovli.width * i734.ovli.height *
4414 color_mode_to_bpp(i734.ovli.fourcc) / 8;
4415
4416 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size,
4417 &i734_buf.paddr, GFP_KERNEL);
4418 if (!i734_buf.vaddr) {
4419 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed",
4420 __func__);
4421 return -ENOMEM;
4422 }
4423
4424 return 0;
4425 }
4426
4427 static void dispc_errata_i734_wa_fini(void)
4428 {
4429 if (!dispc.feat->has_gamma_i734_bug)
4430 return;
4431
4432 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr,
4433 i734_buf.paddr);
4434 }
4435
4436 static void dispc_errata_i734_wa(void)
4437 {
4438 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD);
4439 struct omap_overlay_info ovli;
4440 struct dss_lcd_mgr_config lcd_conf;
4441 u32 gatestate;
4442 unsigned int count;
4443
4444 if (!dispc.feat->has_gamma_i734_bug)
4445 return;
4446
4447 gatestate = REG_GET(DISPC_CONFIG, 8, 4);
4448
4449 ovli = i734.ovli;
4450 ovli.paddr = i734_buf.paddr;
4451 lcd_conf = i734.lcd_conf;
4452
4453 /* Gate all LCD1 outputs */
4454 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4);
4455
4456 /* Setup and enable GFX plane */
4457 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false,
4458 OMAP_DSS_CHANNEL_LCD);
4459 dispc_ovl_enable(OMAP_DSS_GFX, true);
4460
4461 /* Set up and enable display manager for LCD1 */
4462 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4463 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4464 &lcd_conf.clock_info);
4465 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4466 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm);
4467
4468 dispc_clear_irqstatus(framedone_irq);
4469
4470 /* Enable and shut the channel to produce just one frame */
4471 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true);
4472 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false);
4473
4474 /* Busy wait for framedone. We can't fiddle with irq handlers
4475 * in PM resume. Typically the loop runs less than 5 times and
4476 * waits less than a micro second.
4477 */
4478 count = 0;
4479 while (!(dispc_read_irqstatus() & framedone_irq)) {
4480 if (count++ > 10000) {
4481 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n",
4482 __func__);
4483 break;
4484 }
4485 }
4486 dispc_ovl_enable(OMAP_DSS_GFX, false);
4487
4488 /* Clear all irq bits before continuing */
4489 dispc_clear_irqstatus(0xffffffff);
4490
4491 /* Restore the original state to LCD1 output gates */
4492 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4);
4493 }
4494
4495 static const struct dispc_ops dispc_ops = {
4496 .read_irqstatus = dispc_read_irqstatus,
4497 .clear_irqstatus = dispc_clear_irqstatus,
4498 .write_irqenable = dispc_write_irqenable,
4499
4500 .request_irq = dispc_request_irq,
4501 .free_irq = dispc_free_irq,
4502
4503 .runtime_get = dispc_runtime_get,
4504 .runtime_put = dispc_runtime_put,
4505
4506 .get_num_ovls = dispc_get_num_ovls,
4507 .get_num_mgrs = dispc_get_num_mgrs,
4508
4509 .get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,
4510
4511 .mgr_enable = dispc_mgr_enable,
4512 .mgr_is_enabled = dispc_mgr_is_enabled,
4513 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,
4514 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq,
4515 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq,
4516 .mgr_go_busy = dispc_mgr_go_busy,
4517 .mgr_go = dispc_mgr_go,
4518 .mgr_set_lcd_config = dispc_mgr_set_lcd_config,
4519 .mgr_set_timings = dispc_mgr_set_timings,
4520 .mgr_setup = dispc_mgr_setup,
4521 .mgr_get_supported_outputs = dispc_mgr_get_supported_outputs,
4522 .mgr_gamma_size = dispc_mgr_gamma_size,
4523 .mgr_set_gamma = dispc_mgr_set_gamma,
4524
4525 .ovl_enable = dispc_ovl_enable,
4526 .ovl_setup = dispc_ovl_setup,
4527 .ovl_get_color_modes = dispc_ovl_get_color_modes,
4528 };
4529
4530 /* DISPC HW IP initialisation */
4531 static const struct of_device_id dispc_of_match[] = {
4532 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4533 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4534 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4535 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4536 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4537 {},
4538 };
4539
4540 static const struct soc_device_attribute dispc_soc_devices[] = {
4541 { .machine = "OMAP3[45]*",
4542 .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats },
4543 { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats },
4544 { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats },
4545 { .machine = "AM43*", .data = &am43xx_dispc_feats },
4546 { /* sentinel */ }
4547 };
4548
4549 static int dispc_bind(struct device *dev, struct device *master, void *data)
4550 {
4551 struct platform_device *pdev = to_platform_device(dev);
4552 const struct soc_device_attribute *soc;
4553 u32 rev;
4554 int r = 0;
4555 struct resource *dispc_mem;
4556 struct device_node *np = pdev->dev.of_node;
4557
4558 dispc.pdev = pdev;
4559
4560 spin_lock_init(&dispc.control_lock);
4561
4562 /*
4563 * The OMAP3-based models can't be told apart using the compatible
4564 * string, use SoC device matching.
4565 */
4566 soc = soc_device_match(dispc_soc_devices);
4567 if (soc)
4568 dispc.feat = soc->data;
4569 else
4570 dispc.feat = of_match_device(dispc_of_match, &pdev->dev)->data;
4571
4572 r = dispc_errata_i734_wa_init();
4573 if (r)
4574 return r;
4575
4576 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4577 dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem);
4578 if (IS_ERR(dispc.base))
4579 return PTR_ERR(dispc.base);
4580
4581 dispc.irq = platform_get_irq(dispc.pdev, 0);
4582 if (dispc.irq < 0) {
4583 DSSERR("platform_get_irq failed\n");
4584 return -ENODEV;
4585 }
4586
4587 if (np && of_property_read_bool(np, "syscon-pol")) {
4588 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4589 if (IS_ERR(dispc.syscon_pol)) {
4590 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4591 return PTR_ERR(dispc.syscon_pol);
4592 }
4593
4594 if (of_property_read_u32_index(np, "syscon-pol", 1,
4595 &dispc.syscon_pol_offset)) {
4596 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4597 return -EINVAL;
4598 }
4599 }
4600
4601 r = dispc_init_gamma_tables();
4602 if (r)
4603 return r;
4604
4605 pm_runtime_enable(&pdev->dev);
4606
4607 r = dispc_runtime_get();
4608 if (r)
4609 goto err_runtime_get;
4610
4611 _omap_dispc_initial_config();
4612
4613 rev = dispc_read_reg(DISPC_REVISION);
4614 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4615 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4616
4617 dispc_runtime_put();
4618
4619 dispc_set_ops(&dispc_ops);
4620
4621 dss_debugfs_create_file("dispc", dispc_dump_regs);
4622
4623 return 0;
4624
4625 err_runtime_get:
4626 pm_runtime_disable(&pdev->dev);
4627 return r;
4628 }
4629
4630 static void dispc_unbind(struct device *dev, struct device *master,
4631 void *data)
4632 {
4633 dispc_set_ops(NULL);
4634
4635 pm_runtime_disable(dev);
4636
4637 dispc_errata_i734_wa_fini();
4638 }
4639
4640 static const struct component_ops dispc_component_ops = {
4641 .bind = dispc_bind,
4642 .unbind = dispc_unbind,
4643 };
4644
4645 static int dispc_probe(struct platform_device *pdev)
4646 {
4647 return component_add(&pdev->dev, &dispc_component_ops);
4648 }
4649
4650 static int dispc_remove(struct platform_device *pdev)
4651 {
4652 component_del(&pdev->dev, &dispc_component_ops);
4653 return 0;
4654 }
4655
4656 static int dispc_runtime_suspend(struct device *dev)
4657 {
4658 dispc.is_enabled = false;
4659 /* ensure the dispc_irq_handler sees the is_enabled value */
4660 smp_wmb();
4661 /* wait for current handler to finish before turning the DISPC off */
4662 synchronize_irq(dispc.irq);
4663
4664 dispc_save_context();
4665
4666 return 0;
4667 }
4668
4669 static int dispc_runtime_resume(struct device *dev)
4670 {
4671 /*
4672 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4673 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4674 * _omap_dispc_initial_config(). We can thus use it to detect if
4675 * we have lost register context.
4676 */
4677 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4678 _omap_dispc_initial_config();
4679
4680 dispc_errata_i734_wa();
4681
4682 dispc_restore_context();
4683
4684 dispc_restore_gamma_tables();
4685 }
4686
4687 dispc.is_enabled = true;
4688 /* ensure the dispc_irq_handler sees the is_enabled value */
4689 smp_wmb();
4690
4691 return 0;
4692 }
4693
4694 static const struct dev_pm_ops dispc_pm_ops = {
4695 .runtime_suspend = dispc_runtime_suspend,
4696 .runtime_resume = dispc_runtime_resume,
4697 };
4698
4699 struct platform_driver omap_dispchw_driver = {
4700 .probe = dispc_probe,
4701 .remove = dispc_remove,
4702 .driver = {
4703 .name = "omapdss_dispc",
4704 .pm = &dispc_pm_ops,
4705 .of_match_table = dispc_of_match,
4706 .suppress_bind_attrs = true,
4707 },
4708 };
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