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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / gpu / drm / omapdrm / dss / hdmi5_core.c
blob09759f8ea7bcb6ba9df6030a39cca3f342438bc8
1 /*
2 * OMAP5 HDMI CORE IP driver library
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Authors:
6 * Yong Zhi
7 * Mythri pk
8 * Archit Taneja <archit@ti.com>
9 * Tomi Valkeinen <tomi.valkeinen@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/seq_file.h>
31 #include <drm/drm_edid.h>
32 #include <sound/asound.h>
33 #include <sound/asoundef.h>
34
35 #include "hdmi5_core.h"
36
37 /* only 24 bit color depth used for now */
38 static const struct csc_table csc_table_deepcolor[] = {
39 /* HDMI_DEEP_COLOR_24BIT */
40 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
41 /* HDMI_DEEP_COLOR_30BIT */
42 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
43 /* HDMI_DEEP_COLOR_36BIT */
44 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
45 /* FULL RANGE */
46 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
47 };
48
49 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
50 {
51 void __iomem *base = core->base;
52 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
53 const unsigned ss_scl_high = 4600; /* ns */
54 const unsigned ss_scl_low = 5400; /* ns */
55 const unsigned fs_scl_high = 600; /* ns */
56 const unsigned fs_scl_low = 1300; /* ns */
57 const unsigned sda_hold = 1000; /* ns */
58 const unsigned sfr_div = 10;
59 unsigned long long sfr;
60 unsigned v;
61
62 sfr = iclk / sfr_div; /* SFR_DIV */
63 sfr /= 1000; /* SFR clock in kHz */
64
65 /* Reset */
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
67 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
68 0, 0, 1) != 1)
69 DSSERR("HDMI I2CM reset failed\n");
70
71 /* Standard (0) or Fast (1) Mode */
72 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
73
74 /* Standard Mode SCL High counter */
75 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
76 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
77 (v >> 8) & 0xff, 7, 0);
78 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
79 v & 0xff, 7, 0);
80
81 /* Standard Mode SCL Low counter */
82 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
83 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
84 (v >> 8) & 0xff, 7, 0);
85 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
86 v & 0xff, 7, 0);
87
88 /* Fast Mode SCL High Counter */
89 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
90 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
91 (v >> 8) & 0xff, 7, 0);
92 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
93 v & 0xff, 7, 0);
94
95 /* Fast Mode SCL Low Counter */
96 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
97 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
98 (v >> 8) & 0xff, 7, 0);
99 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
100 v & 0xff, 7, 0);
101
102 /* SDA Hold Time */
103 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
104 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
105
106 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
107 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
108
109 /* NACK_POL to high */
110 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
111
112 /* NACK_MASK to unmasked */
113 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
114
115 /* ARBITRATION_POL to high */
116 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
117
118 /* ARBITRATION_MASK to unmasked */
119 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
120
121 /* DONE_POL to high */
122 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
123
124 /* DONE_MASK to unmasked */
125 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
126 }
127
128 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
129 {
130 void __iomem *base = core->base;
131
132 /* Mask I2C interrupts */
133 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
134 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
135 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
136 }
137
138 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
139 {
140 void __iomem *base = core->base;
141 u8 cur_addr;
142 char checksum = 0;
143 const int retries = 1000;
144 u8 seg_ptr = ext / 2;
145 u8 edidbase = ((ext % 2) * 0x80);
146
147 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
148
149 /*
150 * TODO: We use polling here, although we probably should use proper
151 * interrupts.
152 */
153 for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
154 int i;
155
156 /* clear ERROR and DONE */
157 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
158
159 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
160 edidbase + cur_addr, 7, 0);
161
162 if (seg_ptr)
163 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
164 else
165 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
166
167 for (i = 0; i < retries; ++i) {
168 u32 stat;
169
170 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
171
172 /* I2CM_ERROR */
173 if (stat & 1) {
174 DSSERR("HDMI I2C Master Error\n");
175 return -EIO;
176 }
177
178 /* I2CM_DONE */
179 if (stat & (1 << 1))
180 break;
181
182 usleep_range(250, 1000);
183 }
184
185 if (i == retries) {
186 DSSERR("HDMI I2C timeout reading EDID\n");
187 return -EIO;
188 }
189
190 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
191 checksum += pedid[cur_addr];
192 }
193
194 return 0;
195
196 }
197
198 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
199 {
200 int r, n, i;
201 int max_ext_blocks = (len / 128) - 1;
202
203 if (len < 128)
204 return -EINVAL;
205
206 hdmi_core_ddc_init(core);
207
208 r = hdmi_core_ddc_edid(core, edid, 0);
209 if (r)
210 goto out;
211
212 n = edid[0x7e];
213
214 if (n > max_ext_blocks)
215 n = max_ext_blocks;
216
217 for (i = 1; i <= n; i++) {
218 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
219 if (r)
220 goto out;
221 }
222
223 out:
224 hdmi_core_ddc_uninit(core);
225
226 return r ? r : len;
227 }
228
229 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
230 {
231
232 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
233 hdmi_read_reg(core->base, r))
234
235 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
236 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
237 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
238 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
239 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
240 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
241 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
242 DUMPCORE(HDMI_CORE_FC_INVBLANK);
243 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
244 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
245 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
246 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
247 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
248 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
249 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
250 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
251 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
252 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
253 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
254 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
255 DUMPCORE(HDMI_CORE_FC_AVICONF0);
256 DUMPCORE(HDMI_CORE_FC_AVICONF1);
257 DUMPCORE(HDMI_CORE_FC_AVICONF2);
258 DUMPCORE(HDMI_CORE_FC_AVIVID);
259 DUMPCORE(HDMI_CORE_FC_PRCONF);
260
261 DUMPCORE(HDMI_CORE_MC_CLKDIS);
262 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
263 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
264 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
265 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
266
267 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
268 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
269 DUMPCORE(HDMI_CORE_I2CM_DATAO);
270 DUMPCORE(HDMI_CORE_I2CM_DATAI);
271 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
272 DUMPCORE(HDMI_CORE_I2CM_INT);
273 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
274 DUMPCORE(HDMI_CORE_I2CM_DIV);
275 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
276 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
277 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
278 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
279 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
280 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
281 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
282 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
283 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
284 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
285 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
286 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
287 }
288
289 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
290 struct hdmi_config *cfg)
291 {
292 DSSDBG("hdmi_core_init\n");
293
294 video_cfg->v_fc_config.vm = cfg->vm;
295
296 /* video core */
297 video_cfg->data_enable_pol = 1; /* It is always 1*/
298 video_cfg->hblank = cfg->vm.hfront_porch +
299 cfg->vm.hback_porch + cfg->vm.hsync_len;
300 video_cfg->vblank_osc = 0;
301 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
302 cfg->vm.vback_porch;
303 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
304
305 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
306 /* set vblank_osc if vblank is fractional */
307 if (video_cfg->vblank % 2 != 0)
308 video_cfg->vblank_osc = 1;
309
310 video_cfg->v_fc_config.vm.vactive /= 2;
311 video_cfg->vblank /= 2;
312 video_cfg->v_fc_config.vm.vfront_porch /= 2;
313 video_cfg->v_fc_config.vm.vsync_len /= 2;
314 video_cfg->v_fc_config.vm.vback_porch /= 2;
315 }
316
317 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
318 video_cfg->v_fc_config.vm.hactive *= 2;
319 video_cfg->hblank *= 2;
320 video_cfg->v_fc_config.vm.hfront_porch *= 2;
321 video_cfg->v_fc_config.vm.hsync_len *= 2;
322 video_cfg->v_fc_config.vm.hback_porch *= 2;
323 }
324 }
325
326 /* DSS_HDMI_CORE_VIDEO_CONFIG */
327 static void hdmi_core_video_config(struct hdmi_core_data *core,
328 struct hdmi_core_vid_config *cfg)
329 {
330 void __iomem *base = core->base;
331 struct videomode *vm = &cfg->v_fc_config.vm;
332 unsigned char r = 0;
333 bool vsync_pol, hsync_pol;
334
335 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
336 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
337
338 /* Set hsync, vsync and data-enable polarity */
339 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
340 r = FLD_MOD(r, vsync_pol, 6, 6);
341 r = FLD_MOD(r, hsync_pol, 5, 5);
342 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
343 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
344 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
345 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
346
347 /* set x resolution */
348 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
349 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
350
351 /* set y resolution */
352 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
353 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
354
355 /* set horizontal blanking pixels */
356 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
357 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
358
359 /* set vertial blanking pixels */
360 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
361
362 /* set horizontal sync offset */
363 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
364 4, 0);
365 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
366 7, 0);
367
368 /* set vertical sync offset */
369 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
370
371 /* set horizontal sync pulse width */
372 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
373 1, 0);
374 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
375 7, 0);
376
377 /* set vertical sync pulse width */
378 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
379
380 /* select DVI mode */
381 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
382 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
383
384 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
385 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
386 else
387 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
388 }
389
390 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
391 {
392 void __iomem *base = core->base;
393 int clr_depth = 0; /* 24 bit color depth */
394
395 /* COLOR_DEPTH */
396 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
397 /* BYPASS_EN */
398 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
399 /* PP_EN */
400 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
401 /* YCC422_EN */
402 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
403 /* PP_STUFFING */
404 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
405 /* YCC422_STUFFING */
406 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
407 /* OUTPUT_SELECTOR */
408 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
409 }
410
411 static void hdmi_core_config_csc(struct hdmi_core_data *core)
412 {
413 int clr_depth = 0; /* 24 bit color depth */
414
415 /* CSC_COLORDEPTH */
416 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
417 }
418
419 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
420 {
421 int video_mapping = 1; /* for 24 bit color depth */
422
423 /* VIDEO_MAPPING */
424 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
425 }
426
427 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
428 struct hdmi_avi_infoframe *frame)
429 {
430 void __iomem *base = core->base;
431 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
432 u8 *ptr;
433 unsigned y, a, b, s;
434 unsigned c, m, r;
435 unsigned itc, ec, q, sc;
436 unsigned vic;
437 unsigned yq, cn, pr;
438
439 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
440
441 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
442 HDMI_INFOFRAME_SIZE(AVI), false);
443
444 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
445
446 y = (ptr[0] >> 5) & 0x3;
447 a = (ptr[0] >> 4) & 0x1;
448 b = (ptr[0] >> 2) & 0x3;
449 s = (ptr[0] >> 0) & 0x3;
450
451 c = (ptr[1] >> 6) & 0x3;
452 m = (ptr[1] >> 4) & 0x3;
453 r = (ptr[1] >> 0) & 0xf;
454
455 itc = (ptr[2] >> 7) & 0x1;
456 ec = (ptr[2] >> 4) & 0x7;
457 q = (ptr[2] >> 2) & 0x3;
458 sc = (ptr[2] >> 0) & 0x3;
459
460 vic = ptr[3];
461
462 yq = (ptr[4] >> 6) & 0x3;
463 cn = (ptr[4] >> 4) & 0x3;
464 pr = (ptr[4] >> 0) & 0xf;
465
466 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
467 (a << 6) | (s << 4) | (b << 2) | (y << 0));
468
469 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
470 (c << 6) | (m << 4) | (r << 0));
471
472 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
473 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
474
475 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
476
477 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
478 (yq << 2) | (cn << 0));
479
480 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
481 }
482
483 static void hdmi_core_csc_config(struct hdmi_core_data *core,
484 struct csc_table csc_coeff)
485 {
486 void __iomem *base = core->base;
487
488 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
501 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
502 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
503 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
504 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
505 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
506 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
507 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
508 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
509 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
510 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
511 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
512
513 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
514 }
515
516 static void hdmi_core_configure_range(struct hdmi_core_data *core)
517 {
518 struct csc_table csc_coeff = { 0 };
519
520 /* support limited range with 24 bit color depth for now */
521 csc_coeff = csc_table_deepcolor[0];
522
523 hdmi_core_csc_config(core, csc_coeff);
524 }
525
526 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
527 {
528 void __iomem *base = core->base;
529
530 DSSDBG("hdmi_core_enable_video_path\n");
531
532 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
533 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
534 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
535 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
536 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
537 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
538 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
539 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
540 }
541
542 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
543 {
544 void __iomem *base = core->base;
545
546 /* Master IRQ mask */
547 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
548
549 /* Mask all the interrupts in HDMI core */
550
551 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
552 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
553 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
554 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
555
556 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
557 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
558
559 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
560
561 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
562 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
563 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
564
565 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
566
567 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
568
569 /* Clear all the current interrupt bits */
570
571 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
572 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
573 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
574 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
575
576 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
577
578 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
579
580 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
581
582 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
583 }
584
585 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
586 {
587 /* Unmute interrupts */
588 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
589 }
590
591 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
592 {
593 void __iomem *base = core->base;
594
595 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
596 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
597 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
598 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
599 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
600 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
601 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
602 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
603 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
604
605 return 0;
606 }
607
608 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
609 struct hdmi_config *cfg)
610 {
611 struct videomode vm;
612 struct hdmi_video_format video_format;
613 struct hdmi_core_vid_config v_core_cfg;
614
615 hdmi_core_mask_interrupts(core);
616
617 hdmi_core_init(&v_core_cfg, cfg);
618
619 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
620
621 hdmi_wp_video_config_timing(wp, &vm);
622
623 /* video config */
624 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
625
626 hdmi_wp_video_config_format(wp, &video_format);
627
628 hdmi_wp_video_config_interface(wp, &vm);
629
630 /* support limited range with 24 bit color depth for now */
631 hdmi_core_configure_range(core);
632 cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
633
634 /*
635 * configure core video part, set software reset in the core
636 */
637 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
638
639 hdmi_core_video_config(core, &v_core_cfg);
640
641 hdmi_core_config_video_packetizer(core);
642 hdmi_core_config_csc(core);
643 hdmi_core_config_video_sampler(core);
644
645 if (cfg->hdmi_dvi_mode == HDMI_HDMI)
646 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
647
648 hdmi_core_enable_video_path(core);
649
650 hdmi_core_enable_interrupts(core);
651 }
652
653 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
654 struct hdmi_core_audio_config *cfg)
655 {
656 void __iomem *base = core->base;
657 u8 val;
658
659 /* Mute audio before configuring */
660 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
661
662 /* Set the N parameter */
663 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
664 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
665 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
666
667 /*
668 * CTS manual mode. Automatic mode is not supported when using audio
669 * parallel interface.
670 */
671 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
672 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
673 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
674 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
675
676 /* Layout of Audio Sample Packets: 2-channel or multichannels */
677 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
678 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
679 else
680 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
681
682 /* Configure IEC-609580 Validity bits */
683 /* Channel 0 is valid */
684 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
685 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
686
687 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
688 val = 1;
689 else
690 val = 0;
691
692 /* Channels 1, 2 setting */
693 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
694 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
695 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
696 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
697 /* Channel 3 setting */
698 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
699 val = 1;
700 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
701 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
702
703 /* Configure IEC-60958 User bits */
704 /* TODO: should be set by user. */
705 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
706
707 /* Configure IEC-60958 Channel Status word */
708 /* CGMSA */
709 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
710 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
711
712 /* Copyright */
713 val = (cfg->iec60958_cfg->status[0] &
714 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
715 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
716
717 /* Category */
718 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
719 cfg->iec60958_cfg->status[1]);
720
721 /* PCM audio mode */
722 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
723 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
724
725 /* Source number */
726 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
727 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
728
729 /* Channel number right 0 */
730 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
731 /* Channel number right 1*/
732 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
733 /* Channel number right 2 */
734 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
735 /* Channel number right 3*/
736 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
737 /* Channel number left 0 */
738 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
739 /* Channel number left 1*/
740 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
741 /* Channel number left 2 */
742 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
743 /* Channel number left 3*/
744 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
745
746 /* Clock accuracy and sample rate */
747 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
748 cfg->iec60958_cfg->status[3]);
749
750 /* Original sample rate and word length */
751 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
752 cfg->iec60958_cfg->status[4]);
753
754 /* Enable FIFO empty and full interrupts */
755 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
756
757 /* Configure GPA */
758 /* select HBR/SPDIF interfaces */
759 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
760 /* select HBR/SPDIF interfaces */
761 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
762 /* enable two channels in GPA */
763 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
764 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
765 /* select HBR/SPDIF interfaces */
766 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
767 /* enable six channels in GPA */
768 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
769 } else {
770 /* select HBR/SPDIF interfaces */
771 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
772 /* enable eight channels in GPA */
773 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
774 }
775
776 /* disable HBR */
777 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
778 /* enable PCUV */
779 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
780 /* enable GPA FIFO full and empty mask */
781 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
782 /* set polarity of GPA FIFO empty interrupts */
783 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
784
785 /* unmute audio */
786 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
787 }
788
789 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
790 struct snd_cea_861_aud_if *info_aud)
791 {
792 void __iomem *base = core->base;
793
794 /* channel count and coding type fields in AUDICONF0 are swapped */
795 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
796 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
797 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
798
799 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
800 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
801 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
802 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
803 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
804 }
805
806 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
807 struct omap_dss_audio *audio, u32 pclk)
808 {
809 struct hdmi_audio_format audio_format;
810 struct hdmi_audio_dma audio_dma;
811 struct hdmi_core_audio_config core_cfg;
812 int err, n, cts, channel_count;
813 unsigned int fs_nr;
814 bool word_length_16b = false;
815
816 if (!audio || !audio->iec || !audio->cea || !core)
817 return -EINVAL;
818
819 core_cfg.iec60958_cfg = audio->iec;
820
821 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
822 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
823 word_length_16b = true;
824
825 /* only 16-bit word length supported atm */
826 if (!word_length_16b)
827 return -EINVAL;
828
829 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
830 case IEC958_AES3_CON_FS_32000:
831 fs_nr = 32000;
832 break;
833 case IEC958_AES3_CON_FS_44100:
834 fs_nr = 44100;
835 break;
836 case IEC958_AES3_CON_FS_48000:
837 fs_nr = 48000;
838 break;
839 case IEC958_AES3_CON_FS_88200:
840 fs_nr = 88200;
841 break;
842 case IEC958_AES3_CON_FS_96000:
843 fs_nr = 96000;
844 break;
845 case IEC958_AES3_CON_FS_176400:
846 fs_nr = 176400;
847 break;
848 case IEC958_AES3_CON_FS_192000:
849 fs_nr = 192000;
850 break;
851 default:
852 return -EINVAL;
853 }
854
855 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
856 core_cfg.n = n;
857 core_cfg.cts = cts;
858
859 /* Audio channels settings */
860 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
861 + 1;
862
863 if (channel_count == 2)
864 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
865 else if (channel_count == 6)
866 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
867 else
868 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
869
870 /* DMA settings */
871 if (word_length_16b)
872 audio_dma.transfer_size = 0x10;
873 else
874 audio_dma.transfer_size = 0x20;
875 audio_dma.block_size = 0xC0;
876 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
877 audio_dma.fifo_threshold = 0x20; /* in number of samples */
878
879 /* audio FIFO format settings for 16-bit samples*/
880 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
881 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
882 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
883 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
884
885 /* only LPCM atm */
886 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
887
888 /* only allowed option */
889 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
890
891 /* disable start/stop signals of IEC 60958 blocks */
892 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
893
894 /* configure DMA and audio FIFO format*/
895 hdmi_wp_audio_config_dma(wp, &audio_dma);
896 hdmi_wp_audio_config_format(wp, &audio_format);
897
898 /* configure the core */
899 hdmi5_core_audio_config(core, &core_cfg);
900
901 /* configure CEA 861 audio infoframe */
902 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
903
904 return 0;
905 }
906
907 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
908 {
909 struct resource *res;
910
911 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
912 core->base = devm_ioremap_resource(&pdev->dev, res);
913 if (IS_ERR(core->base))
914 return PTR_ERR(core->base);
915
916 return 0;
917 }
CRIS linux kernel tree