2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
32 void radeon_gem_object_free(struct drm_gem_object
*gobj
)
34 struct radeon_bo
*robj
= gem_to_radeon_bo(gobj
);
37 if (robj
->gem_base
.import_attach
)
38 drm_prime_gem_destroy(&robj
->gem_base
, robj
->tbo
.sg
);
39 radeon_mn_unregister(robj
);
40 radeon_bo_unref(&robj
);
44 int radeon_gem_object_create(struct radeon_device
*rdev
, unsigned long size
,
45 int alignment
, int initial_domain
,
46 u32 flags
, bool kernel
,
47 struct drm_gem_object
**obj
)
49 struct radeon_bo
*robj
;
50 unsigned long max_size
;
54 /* At least align on page size */
55 if (alignment
< PAGE_SIZE
) {
56 alignment
= PAGE_SIZE
;
59 /* Maximum bo size is the unpinned gtt size since we use the gtt to
60 * handle vram to system pool migrations.
62 max_size
= rdev
->mc
.gtt_size
- rdev
->gart_pin_size
;
63 if (size
> max_size
) {
64 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
65 size
>> 20, max_size
>> 20);
70 r
= radeon_bo_create(rdev
, size
, alignment
, kernel
, initial_domain
,
71 flags
, NULL
, NULL
, &robj
);
73 if (r
!= -ERESTARTSYS
) {
74 if (initial_domain
== RADEON_GEM_DOMAIN_VRAM
) {
75 initial_domain
|= RADEON_GEM_DOMAIN_GTT
;
78 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
79 size
, initial_domain
, alignment
, r
);
83 *obj
= &robj
->gem_base
;
84 robj
->pid
= task_pid_nr(current
);
86 mutex_lock(&rdev
->gem
.mutex
);
87 list_add_tail(&robj
->list
, &rdev
->gem
.objects
);
88 mutex_unlock(&rdev
->gem
.mutex
);
93 static int radeon_gem_set_domain(struct drm_gem_object
*gobj
,
94 uint32_t rdomain
, uint32_t wdomain
)
96 struct radeon_bo
*robj
;
100 /* FIXME: reeimplement */
101 robj
= gem_to_radeon_bo(gobj
);
102 /* work out where to validate the buffer to */
109 pr_warn("Set domain without domain !\n");
112 if (domain
== RADEON_GEM_DOMAIN_CPU
) {
113 /* Asking for cpu access wait for object idle */
114 r
= reservation_object_wait_timeout_rcu(robj
->tbo
.resv
, true, true, 30 * HZ
);
118 if (r
< 0 && r
!= -EINTR
) {
119 pr_err("Failed to wait for object: %li\n", r
);
123 if (domain
== RADEON_GEM_DOMAIN_VRAM
&& robj
->prime_shared_count
) {
124 /* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */
130 int radeon_gem_init(struct radeon_device
*rdev
)
132 INIT_LIST_HEAD(&rdev
->gem
.objects
);
136 void radeon_gem_fini(struct radeon_device
*rdev
)
138 radeon_bo_force_delete(rdev
);
142 * Call from drm_gem_handle_create which appear in both new and open ioctl
145 int radeon_gem_object_open(struct drm_gem_object
*obj
, struct drm_file
*file_priv
)
147 struct radeon_bo
*rbo
= gem_to_radeon_bo(obj
);
148 struct radeon_device
*rdev
= rbo
->rdev
;
149 struct radeon_fpriv
*fpriv
= file_priv
->driver_priv
;
150 struct radeon_vm
*vm
= &fpriv
->vm
;
151 struct radeon_bo_va
*bo_va
;
154 if ((rdev
->family
< CHIP_CAYMAN
) ||
155 (!rdev
->accel_working
)) {
159 r
= radeon_bo_reserve(rbo
, false);
164 bo_va
= radeon_vm_bo_find(vm
, rbo
);
166 bo_va
= radeon_vm_bo_add(rdev
, vm
, rbo
);
170 radeon_bo_unreserve(rbo
);
175 void radeon_gem_object_close(struct drm_gem_object
*obj
,
176 struct drm_file
*file_priv
)
178 struct radeon_bo
*rbo
= gem_to_radeon_bo(obj
);
179 struct radeon_device
*rdev
= rbo
->rdev
;
180 struct radeon_fpriv
*fpriv
= file_priv
->driver_priv
;
181 struct radeon_vm
*vm
= &fpriv
->vm
;
182 struct radeon_bo_va
*bo_va
;
185 if ((rdev
->family
< CHIP_CAYMAN
) ||
186 (!rdev
->accel_working
)) {
190 r
= radeon_bo_reserve(rbo
, true);
192 dev_err(rdev
->dev
, "leaking bo va because "
193 "we fail to reserve bo (%d)\n", r
);
196 bo_va
= radeon_vm_bo_find(vm
, rbo
);
198 if (--bo_va
->ref_count
== 0) {
199 radeon_vm_bo_rmv(rdev
, bo_va
);
202 radeon_bo_unreserve(rbo
);
205 static int radeon_gem_handle_lockup(struct radeon_device
*rdev
, int r
)
208 r
= radeon_gpu_reset(rdev
);
218 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
219 struct drm_file
*filp
)
221 struct radeon_device
*rdev
= dev
->dev_private
;
222 struct drm_radeon_gem_info
*args
= data
;
223 struct ttm_mem_type_manager
*man
;
225 man
= &rdev
->mman
.bdev
.man
[TTM_PL_VRAM
];
227 args
->vram_size
= (u64
)man
->size
<< PAGE_SHIFT
;
228 args
->vram_visible
= rdev
->mc
.visible_vram_size
;
229 args
->vram_visible
-= rdev
->vram_pin_size
;
230 args
->gart_size
= rdev
->mc
.gtt_size
;
231 args
->gart_size
-= rdev
->gart_pin_size
;
236 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
237 struct drm_file
*filp
)
239 /* TODO: implement */
240 DRM_ERROR("unimplemented %s\n", __func__
);
244 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
245 struct drm_file
*filp
)
247 /* TODO: implement */
248 DRM_ERROR("unimplemented %s\n", __func__
);
252 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
253 struct drm_file
*filp
)
255 struct radeon_device
*rdev
= dev
->dev_private
;
256 struct drm_radeon_gem_create
*args
= data
;
257 struct drm_gem_object
*gobj
;
261 down_read(&rdev
->exclusive_lock
);
262 /* create a gem object to contain this object in */
263 args
->size
= roundup(args
->size
, PAGE_SIZE
);
264 r
= radeon_gem_object_create(rdev
, args
->size
, args
->alignment
,
265 args
->initial_domain
, args
->flags
,
268 up_read(&rdev
->exclusive_lock
);
269 r
= radeon_gem_handle_lockup(rdev
, r
);
272 r
= drm_gem_handle_create(filp
, gobj
, &handle
);
273 /* drop reference from allocate - handle holds it now */
274 drm_gem_object_put_unlocked(gobj
);
276 up_read(&rdev
->exclusive_lock
);
277 r
= radeon_gem_handle_lockup(rdev
, r
);
280 args
->handle
= handle
;
281 up_read(&rdev
->exclusive_lock
);
285 int radeon_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
286 struct drm_file
*filp
)
288 struct ttm_operation_ctx ctx
= { true, false };
289 struct radeon_device
*rdev
= dev
->dev_private
;
290 struct drm_radeon_gem_userptr
*args
= data
;
291 struct drm_gem_object
*gobj
;
292 struct radeon_bo
*bo
;
296 if (offset_in_page(args
->addr
| args
->size
))
299 /* reject unknown flag values */
300 if (args
->flags
& ~(RADEON_GEM_USERPTR_READONLY
|
301 RADEON_GEM_USERPTR_ANONONLY
| RADEON_GEM_USERPTR_VALIDATE
|
302 RADEON_GEM_USERPTR_REGISTER
))
305 if (args
->flags
& RADEON_GEM_USERPTR_READONLY
) {
306 /* readonly pages not tested on older hardware */
307 if (rdev
->family
< CHIP_R600
)
310 } else if (!(args
->flags
& RADEON_GEM_USERPTR_ANONONLY
) ||
311 !(args
->flags
& RADEON_GEM_USERPTR_REGISTER
)) {
313 /* if we want to write to it we must require anonymous
314 memory and install a MMU notifier */
318 down_read(&rdev
->exclusive_lock
);
320 /* create a gem object to contain this object in */
321 r
= radeon_gem_object_create(rdev
, args
->size
, 0,
322 RADEON_GEM_DOMAIN_CPU
, 0,
327 bo
= gem_to_radeon_bo(gobj
);
328 r
= radeon_ttm_tt_set_userptr(bo
->tbo
.ttm
, args
->addr
, args
->flags
);
332 if (args
->flags
& RADEON_GEM_USERPTR_REGISTER
) {
333 r
= radeon_mn_register(bo
, args
->addr
);
338 if (args
->flags
& RADEON_GEM_USERPTR_VALIDATE
) {
339 down_read(¤t
->mm
->mmap_sem
);
340 r
= radeon_bo_reserve(bo
, true);
342 up_read(¤t
->mm
->mmap_sem
);
346 radeon_ttm_placement_from_domain(bo
, RADEON_GEM_DOMAIN_GTT
);
347 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, &ctx
);
348 radeon_bo_unreserve(bo
);
349 up_read(¤t
->mm
->mmap_sem
);
354 r
= drm_gem_handle_create(filp
, gobj
, &handle
);
355 /* drop reference from allocate - handle holds it now */
356 drm_gem_object_put_unlocked(gobj
);
360 args
->handle
= handle
;
361 up_read(&rdev
->exclusive_lock
);
365 drm_gem_object_put_unlocked(gobj
);
368 up_read(&rdev
->exclusive_lock
);
369 r
= radeon_gem_handle_lockup(rdev
, r
);
374 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
375 struct drm_file
*filp
)
377 /* transition the BO to a domain -
378 * just validate the BO into a certain domain */
379 struct radeon_device
*rdev
= dev
->dev_private
;
380 struct drm_radeon_gem_set_domain
*args
= data
;
381 struct drm_gem_object
*gobj
;
382 struct radeon_bo
*robj
;
385 /* for now if someone requests domain CPU -
386 * just make sure the buffer is finished with */
387 down_read(&rdev
->exclusive_lock
);
389 /* just do a BO wait for now */
390 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
392 up_read(&rdev
->exclusive_lock
);
395 robj
= gem_to_radeon_bo(gobj
);
397 r
= radeon_gem_set_domain(gobj
, args
->read_domains
, args
->write_domain
);
399 drm_gem_object_put_unlocked(gobj
);
400 up_read(&rdev
->exclusive_lock
);
401 r
= radeon_gem_handle_lockup(robj
->rdev
, r
);
405 int radeon_mode_dumb_mmap(struct drm_file
*filp
,
406 struct drm_device
*dev
,
407 uint32_t handle
, uint64_t *offset_p
)
409 struct drm_gem_object
*gobj
;
410 struct radeon_bo
*robj
;
412 gobj
= drm_gem_object_lookup(filp
, handle
);
416 robj
= gem_to_radeon_bo(gobj
);
417 if (radeon_ttm_tt_has_userptr(robj
->tbo
.ttm
)) {
418 drm_gem_object_put_unlocked(gobj
);
421 *offset_p
= radeon_bo_mmap_offset(robj
);
422 drm_gem_object_put_unlocked(gobj
);
426 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
427 struct drm_file
*filp
)
429 struct drm_radeon_gem_mmap
*args
= data
;
431 return radeon_mode_dumb_mmap(filp
, dev
, args
->handle
, &args
->addr_ptr
);
434 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
435 struct drm_file
*filp
)
437 struct drm_radeon_gem_busy
*args
= data
;
438 struct drm_gem_object
*gobj
;
439 struct radeon_bo
*robj
;
441 uint32_t cur_placement
= 0;
443 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
447 robj
= gem_to_radeon_bo(gobj
);
449 r
= reservation_object_test_signaled_rcu(robj
->tbo
.resv
, true);
455 cur_placement
= READ_ONCE(robj
->tbo
.mem
.mem_type
);
456 args
->domain
= radeon_mem_type_to_domain(cur_placement
);
457 drm_gem_object_put_unlocked(gobj
);
461 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
462 struct drm_file
*filp
)
464 struct radeon_device
*rdev
= dev
->dev_private
;
465 struct drm_radeon_gem_wait_idle
*args
= data
;
466 struct drm_gem_object
*gobj
;
467 struct radeon_bo
*robj
;
469 uint32_t cur_placement
= 0;
472 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
476 robj
= gem_to_radeon_bo(gobj
);
478 ret
= reservation_object_wait_timeout_rcu(robj
->tbo
.resv
, true, true, 30 * HZ
);
484 /* Flush HDP cache via MMIO if necessary */
485 cur_placement
= READ_ONCE(robj
->tbo
.mem
.mem_type
);
486 if (rdev
->asic
->mmio_hdp_flush
&&
487 radeon_mem_type_to_domain(cur_placement
) == RADEON_GEM_DOMAIN_VRAM
)
488 robj
->rdev
->asic
->mmio_hdp_flush(rdev
);
489 drm_gem_object_put_unlocked(gobj
);
490 r
= radeon_gem_handle_lockup(rdev
, r
);
494 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
495 struct drm_file
*filp
)
497 struct drm_radeon_gem_set_tiling
*args
= data
;
498 struct drm_gem_object
*gobj
;
499 struct radeon_bo
*robj
;
502 DRM_DEBUG("%d \n", args
->handle
);
503 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
506 robj
= gem_to_radeon_bo(gobj
);
507 r
= radeon_bo_set_tiling_flags(robj
, args
->tiling_flags
, args
->pitch
);
508 drm_gem_object_put_unlocked(gobj
);
512 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
513 struct drm_file
*filp
)
515 struct drm_radeon_gem_get_tiling
*args
= data
;
516 struct drm_gem_object
*gobj
;
517 struct radeon_bo
*rbo
;
521 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
524 rbo
= gem_to_radeon_bo(gobj
);
525 r
= radeon_bo_reserve(rbo
, false);
526 if (unlikely(r
!= 0))
528 radeon_bo_get_tiling_flags(rbo
, &args
->tiling_flags
, &args
->pitch
);
529 radeon_bo_unreserve(rbo
);
531 drm_gem_object_put_unlocked(gobj
);
536 * radeon_gem_va_update_vm -update the bo_va in its VM
538 * @rdev: radeon_device pointer
539 * @bo_va: bo_va to update
541 * Update the bo_va directly after setting it's address. Errors are not
542 * vital here, so they are not reported back to userspace.
544 static void radeon_gem_va_update_vm(struct radeon_device
*rdev
,
545 struct radeon_bo_va
*bo_va
)
547 struct ttm_validate_buffer tv
, *entry
;
548 struct radeon_bo_list
*vm_bos
;
549 struct ww_acquire_ctx ticket
;
550 struct list_head list
;
554 INIT_LIST_HEAD(&list
);
556 tv
.bo
= &bo_va
->bo
->tbo
;
558 list_add(&tv
.head
, &list
);
560 vm_bos
= radeon_vm_get_bos(rdev
, bo_va
->vm
, &list
);
564 r
= ttm_eu_reserve_buffers(&ticket
, &list
, true, NULL
);
568 list_for_each_entry(entry
, &list
, head
) {
569 domain
= radeon_mem_type_to_domain(entry
->bo
->mem
.mem_type
);
570 /* if anything is swapped out don't swap it in here,
571 just abort and wait for the next CS */
572 if (domain
== RADEON_GEM_DOMAIN_CPU
)
573 goto error_unreserve
;
576 mutex_lock(&bo_va
->vm
->mutex
);
577 r
= radeon_vm_clear_freed(rdev
, bo_va
->vm
);
582 r
= radeon_vm_bo_update(rdev
, bo_va
, &bo_va
->bo
->tbo
.mem
);
585 mutex_unlock(&bo_va
->vm
->mutex
);
588 ttm_eu_backoff_reservation(&ticket
, &list
);
593 if (r
&& r
!= -ERESTARTSYS
)
594 DRM_ERROR("Couldn't update BO_VA (%d)\n", r
);
597 int radeon_gem_va_ioctl(struct drm_device
*dev
, void *data
,
598 struct drm_file
*filp
)
600 struct drm_radeon_gem_va
*args
= data
;
601 struct drm_gem_object
*gobj
;
602 struct radeon_device
*rdev
= dev
->dev_private
;
603 struct radeon_fpriv
*fpriv
= filp
->driver_priv
;
604 struct radeon_bo
*rbo
;
605 struct radeon_bo_va
*bo_va
;
609 if (!rdev
->vm_manager
.enabled
) {
610 args
->operation
= RADEON_VA_RESULT_ERROR
;
615 * We don't support vm_id yet, to be sure we don't have have broken
616 * userspace, reject anyone trying to use non 0 value thus moving
617 * forward we can use those fields without breaking existant userspace
620 args
->operation
= RADEON_VA_RESULT_ERROR
;
624 if (args
->offset
< RADEON_VA_RESERVED_SIZE
) {
625 dev_err(&dev
->pdev
->dev
,
626 "offset 0x%lX is in reserved area 0x%X\n",
627 (unsigned long)args
->offset
,
628 RADEON_VA_RESERVED_SIZE
);
629 args
->operation
= RADEON_VA_RESULT_ERROR
;
633 /* don't remove, we need to enforce userspace to set the snooped flag
634 * otherwise we will endup with broken userspace and we won't be able
635 * to enable this feature without adding new interface
637 invalid_flags
= RADEON_VM_PAGE_VALID
| RADEON_VM_PAGE_SYSTEM
;
638 if ((args
->flags
& invalid_flags
)) {
639 dev_err(&dev
->pdev
->dev
, "invalid flags 0x%08X vs 0x%08X\n",
640 args
->flags
, invalid_flags
);
641 args
->operation
= RADEON_VA_RESULT_ERROR
;
645 switch (args
->operation
) {
647 case RADEON_VA_UNMAP
:
650 dev_err(&dev
->pdev
->dev
, "unsupported operation %d\n",
652 args
->operation
= RADEON_VA_RESULT_ERROR
;
656 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
658 args
->operation
= RADEON_VA_RESULT_ERROR
;
661 rbo
= gem_to_radeon_bo(gobj
);
662 r
= radeon_bo_reserve(rbo
, false);
664 args
->operation
= RADEON_VA_RESULT_ERROR
;
665 drm_gem_object_put_unlocked(gobj
);
668 bo_va
= radeon_vm_bo_find(&fpriv
->vm
, rbo
);
670 args
->operation
= RADEON_VA_RESULT_ERROR
;
671 radeon_bo_unreserve(rbo
);
672 drm_gem_object_put_unlocked(gobj
);
676 switch (args
->operation
) {
678 if (bo_va
->it
.start
) {
679 args
->operation
= RADEON_VA_RESULT_VA_EXIST
;
680 args
->offset
= bo_va
->it
.start
* RADEON_GPU_PAGE_SIZE
;
681 radeon_bo_unreserve(rbo
);
684 r
= radeon_vm_bo_set_addr(rdev
, bo_va
, args
->offset
, args
->flags
);
686 case RADEON_VA_UNMAP
:
687 r
= radeon_vm_bo_set_addr(rdev
, bo_va
, 0, 0);
693 radeon_gem_va_update_vm(rdev
, bo_va
);
694 args
->operation
= RADEON_VA_RESULT_OK
;
696 args
->operation
= RADEON_VA_RESULT_ERROR
;
699 drm_gem_object_put_unlocked(gobj
);
703 int radeon_gem_op_ioctl(struct drm_device
*dev
, void *data
,
704 struct drm_file
*filp
)
706 struct drm_radeon_gem_op
*args
= data
;
707 struct drm_gem_object
*gobj
;
708 struct radeon_bo
*robj
;
711 gobj
= drm_gem_object_lookup(filp
, args
->handle
);
715 robj
= gem_to_radeon_bo(gobj
);
718 if (radeon_ttm_tt_has_userptr(robj
->tbo
.ttm
))
721 r
= radeon_bo_reserve(robj
, false);
726 case RADEON_GEM_OP_GET_INITIAL_DOMAIN
:
727 args
->value
= robj
->initial_domain
;
729 case RADEON_GEM_OP_SET_INITIAL_DOMAIN
:
730 robj
->initial_domain
= args
->value
& (RADEON_GEM_DOMAIN_VRAM
|
731 RADEON_GEM_DOMAIN_GTT
|
732 RADEON_GEM_DOMAIN_CPU
);
738 radeon_bo_unreserve(robj
);
740 drm_gem_object_put_unlocked(gobj
);
744 int radeon_mode_dumb_create(struct drm_file
*file_priv
,
745 struct drm_device
*dev
,
746 struct drm_mode_create_dumb
*args
)
748 struct radeon_device
*rdev
= dev
->dev_private
;
749 struct drm_gem_object
*gobj
;
753 args
->pitch
= radeon_align_pitch(rdev
, args
->width
,
754 DIV_ROUND_UP(args
->bpp
, 8), 0);
755 args
->size
= args
->pitch
* args
->height
;
756 args
->size
= ALIGN(args
->size
, PAGE_SIZE
);
758 r
= radeon_gem_object_create(rdev
, args
->size
, 0,
759 RADEON_GEM_DOMAIN_VRAM
, 0,
764 r
= drm_gem_handle_create(file_priv
, gobj
, &handle
);
765 /* drop reference from allocate - handle holds it now */
766 drm_gem_object_put_unlocked(gobj
);
770 args
->handle
= handle
;
774 #if defined(CONFIG_DEBUG_FS)
775 static int radeon_debugfs_gem_info(struct seq_file
*m
, void *data
)
777 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
778 struct drm_device
*dev
= node
->minor
->dev
;
779 struct radeon_device
*rdev
= dev
->dev_private
;
780 struct radeon_bo
*rbo
;
783 mutex_lock(&rdev
->gem
.mutex
);
784 list_for_each_entry(rbo
, &rdev
->gem
.objects
, list
) {
786 const char *placement
;
788 domain
= radeon_mem_type_to_domain(rbo
->tbo
.mem
.mem_type
);
790 case RADEON_GEM_DOMAIN_VRAM
:
793 case RADEON_GEM_DOMAIN_GTT
:
796 case RADEON_GEM_DOMAIN_CPU
:
801 seq_printf(m
, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
802 i
, radeon_bo_size(rbo
) >> 10, radeon_bo_size(rbo
) >> 20,
803 placement
, (unsigned long)rbo
->pid
);
806 mutex_unlock(&rdev
->gem
.mutex
);
810 static struct drm_info_list radeon_debugfs_gem_list
[] = {
811 {"radeon_gem_info", &radeon_debugfs_gem_info
, 0, NULL
},
815 int radeon_gem_debugfs_init(struct radeon_device
*rdev
)
817 #if defined(CONFIG_DEBUG_FS)
818 return radeon_debugfs_add_files(rdev
, radeon_debugfs_gem_list
, 1);