drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16 #include <linux/sys_soc.h>
  17
  18 #include <drm/drmP.h>
  19 #include <drm/drm_atomic.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_gem_cma_helper.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 #include "rcar_du_crtc.h"
  28 #include "rcar_du_drv.h"
  29 #include "rcar_du_kms.h"
  30 #include "rcar_du_plane.h"
  31 #include "rcar_du_regs.h"
  32 #include "rcar_du_vsp.h"
  33
  34 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  35 {
  36         struct rcar_du_device *rcdu = rcrtc->group->dev;
  37
  38         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  39 }
  40
  41 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  42 {
  43         struct rcar_du_device *rcdu = rcrtc->group->dev;
  44
  45         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  46 }
  47
  48 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  49 {
  50         struct rcar_du_device *rcdu = rcrtc->group->dev;
  51
  52         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  53                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  54 }
  55
  56 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  57 {
  58         struct rcar_du_device *rcdu = rcrtc->group->dev;
  59
  60         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  61                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  62 }
  63
  64 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  65                                  u32 clr, u32 set)
  66 {
  67         struct rcar_du_device *rcdu = rcrtc->group->dev;
  68         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  69
  70         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  71 }
  72
  73 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  74 {
  75         int ret;
  76
  77         ret = clk_prepare_enable(rcrtc->clock);
  78         if (ret < 0)
  79                 return ret;
  80
  81         ret = clk_prepare_enable(rcrtc->extclock);
  82         if (ret < 0)
  83                 goto error_clock;
  84
  85         ret = rcar_du_group_get(rcrtc->group);
  86         if (ret < 0)
  87                 goto error_group;
  88
  89         return 0;
  90
  91 error_group:
  92         clk_disable_unprepare(rcrtc->extclock);
  93 error_clock:
  94         clk_disable_unprepare(rcrtc->clock);
  95         return ret;
  96 }
  97
  98 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  99 {
 100         rcar_du_group_put(rcrtc->group);
 101
 102         clk_disable_unprepare(rcrtc->extclock);
 103         clk_disable_unprepare(rcrtc->clock);
 104 }
 105
 106 /* -----------------------------------------------------------------------------
 107  * Hardware Setup
 108  */
 109
 110 struct dpll_info {
 111         unsigned int output;
 112         unsigned int fdpll;
 113         unsigned int n;
 114         unsigned int m;
 115 };
 116
 117 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
 118                                  struct dpll_info *dpll,
 119                                  unsigned long input,
 120                                  unsigned long target)
 121 {
 122         unsigned long best_diff = (unsigned long)-1;
 123         unsigned long diff;
 124         unsigned int fdpll;
 125         unsigned int m;
 126         unsigned int n;
 127
 128         for (n = 39; n < 120; n++) {
 129                 for (m = 0; m < 4; m++) {
 130                         for (fdpll = 1; fdpll < 32; fdpll++) {
 131                                 unsigned long output;
 132
 133                                 output = input * (n + 1) / (m + 1)
 134                                        / (fdpll + 1);
 135                                 if (output >= 400000000)
 136                                         continue;
 137
 138                                 diff = abs((long)output - (long)target);
 139                                 if (best_diff > diff) {
 140                                         best_diff = diff;
 141                                         dpll->n = n;
 142                                         dpll->m = m;
 143                                         dpll->fdpll = fdpll;
 144                                         dpll->output = output;
 145                                 }
 146
 147                                 if (diff == 0)
 148                                         goto done;
 149                         }
 150                 }
 151         }
 152
 153 done:
 154         dev_dbg(rcrtc->group->dev->dev,
 155                 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
 156                  dpll->output, dpll->fdpll, dpll->n, dpll->m,
 157                  best_diff);
 158 }
 159
 160 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
 161         { .soc_id = "r8a7795", .revision = "ES1.*" },
 162         { /* sentinel */ }
 163 };
 164
 165 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 166 {
 167         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 168         struct rcar_du_device *rcdu = rcrtc->group->dev;
 169         unsigned long mode_clock = mode->clock * 1000;
 170         unsigned long clk;
 171         u32 value;
 172         u32 escr;
 173         u32 div;
 174
 175         /*
 176          * Compute the clock divisor and select the internal or external dot
 177          * clock based on the requested frequency.
 178          */
 179         clk = clk_get_rate(rcrtc->clock);
 180         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 181         div = clamp(div, 1U, 64U) - 1;
 182         escr = div | ESCR_DCLKSEL_CLKS;
 183
 184         if (rcrtc->extclock) {
 185                 struct dpll_info dpll = { 0 };
 186                 unsigned long extclk;
 187                 unsigned long extrate;
 188                 unsigned long rate;
 189                 u32 extdiv;
 190
 191                 extclk = clk_get_rate(rcrtc->extclock);
 192                 if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
 193                         unsigned long target = mode_clock;
 194
 195                         /*
 196                          * The H3 ES1.x exhibits dot clock duty cycle stability
 197                          * issues. We can work around them by configuring the
 198                          * DPLL to twice the desired frequency, coupled with a
 199                          * /2 post-divider. This isn't needed on other SoCs and
 200                          * breaks HDMI output on M3-W for a currently unknown
 201                          * reason, so restrict the workaround to H3 ES1.x.
 202                          */
 203                         if (soc_device_match(rcar_du_r8a7795_es1))
 204                                 target *= 2;
 205
 206                         rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
 207                         extclk = dpll.output;
 208                 }
 209
 210                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 211                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 212
 213                 rate = clk / (div + 1);
 214                 extrate = extclk / (extdiv + 1);
 215
 216                 if (abs((long)extrate - (long)mode_clock) <
 217                     abs((long)rate - (long)mode_clock)) {
 218
 219                         if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
 220                                 u32 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
 221                                            | DPLLCR_FDPLL(dpll.fdpll)
 222                                            | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
 223                                            | DPLLCR_STBY;
 224
 225                                 if (rcrtc->index == 1)
 226                                         dpllcr |= DPLLCR_PLCS1
 227                                                |  DPLLCR_INCS_DOTCLKIN1;
 228                                 else
 229                                         dpllcr |= DPLLCR_PLCS0
 230                                                |  DPLLCR_INCS_DOTCLKIN0;
 231
 232                                 rcar_du_group_write(rcrtc->group, DPLLCR,
 233                                                     dpllcr);
 234                         }
 235
 236                         escr = ESCR_DCLKSEL_DCLKIN | extdiv;
 237                 }
 238
 239                 dev_dbg(rcrtc->group->dev->dev,
 240                         "mode clock %lu extrate %lu rate %lu ESCR 0x%08x\n",
 241                         mode_clock, extrate, rate, escr);
 242         }
 243
 244         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 245                             escr);
 246         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 247
 248         /* Signal polarities */
 249         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
 250               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 251               | DSMR_DIPM_DISP | DSMR_CSPM;
 252         rcar_du_crtc_write(rcrtc, DSMR, value);
 253
 254         /* Display timings */
 255         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 256         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 257                                         mode->hdisplay - 19);
 258         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 259                                         mode->hsync_start - 1);
 260         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 261
 262         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 263                                         mode->crtc_vsync_end - 2);
 264         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 265                                         mode->crtc_vsync_end +
 266                                         mode->crtc_vdisplay - 2);
 267         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 268                                         mode->crtc_vsync_end +
 269                                         mode->crtc_vsync_start - 1);
 270         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 271
 272         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 273         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 274 }
 275
 276 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 277                                enum rcar_du_output output)
 278 {
 279         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 280         struct rcar_du_device *rcdu = rcrtc->group->dev;
 281
 282         /*
 283          * Store the route from the CRTC output to the DU output. The DU will be
 284          * configured when starting the CRTC.
 285          */
 286         rcrtc->outputs |= BIT(output);
 287
 288         /*
 289          * Store RGB routing to DPAD0, the hardware will be configured when
 290          * starting the CRTC.
 291          */
 292         if (output == RCAR_DU_OUTPUT_DPAD0)
 293                 rcdu->dpad0_source = rcrtc->index;
 294 }
 295
 296 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 297 {
 298         return plane->plane.state->normalized_zpos;
 299 }
 300
 301 static const struct rcar_du_format_info *
 302 plane_format(struct rcar_du_plane *plane)
 303 {
 304         return to_rcar_plane_state(plane->plane.state)->format;
 305 }
 306
 307 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 308 {
 309         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 310         struct rcar_du_device *rcdu = rcrtc->group->dev;
 311         unsigned int num_planes = 0;
 312         unsigned int dptsr_planes;
 313         unsigned int hwplanes = 0;
 314         unsigned int prio = 0;
 315         unsigned int i;
 316         u32 dspr = 0;
 317
 318         for (i = 0; i < rcrtc->group->num_planes; ++i) {
 319                 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
 320                 unsigned int j;
 321
 322                 if (plane->plane.state->crtc != &rcrtc->crtc ||
 323                     !plane->plane.state->visible)
 324                         continue;
 325
 326                 /* Insert the plane in the sorted planes array. */
 327                 for (j = num_planes++; j > 0; --j) {
 328                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 329                                 break;
 330                         planes[j] = planes[j-1];
 331                 }
 332
 333                 planes[j] = plane;
 334                 prio += plane_format(plane)->planes * 4;
 335         }
 336
 337         for (i = 0; i < num_planes; ++i) {
 338                 struct rcar_du_plane *plane = planes[i];
 339                 struct drm_plane_state *state = plane->plane.state;
 340                 unsigned int index = to_rcar_plane_state(state)->hwindex;
 341
 342                 prio -= 4;
 343                 dspr |= (index + 1) << prio;
 344                 hwplanes |= 1 << index;
 345
 346                 if (plane_format(plane)->planes == 2) {
 347                         index = (index + 1) % 8;
 348
 349                         prio -= 4;
 350                         dspr |= (index + 1) << prio;
 351                         hwplanes |= 1 << index;
 352                 }
 353         }
 354
 355         /* If VSP+DU integration is enabled the plane assignment is fixed. */
 356         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 357                 if (rcdu->info->gen < 3) {
 358                         dspr = (rcrtc->index % 2) + 1;
 359                         hwplanes = 1 << (rcrtc->index % 2);
 360                 } else {
 361                         dspr = (rcrtc->index % 2) ? 3 : 1;
 362                         hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
 363                 }
 364         }
 365
 366         /*
 367          * Update the planes to display timing and dot clock generator
 368          * associations.
 369          *
 370          * Updating the DPTSR register requires restarting the CRTC group,
 371          * resulting in visible flicker. To mitigate the issue only update the
 372          * association if needed by enabled planes. Planes being disabled will
 373          * keep their current association.
 374          */
 375         mutex_lock(&rcrtc->group->lock);
 376
 377         dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
 378                      : rcrtc->group->dptsr_planes & ~hwplanes;
 379
 380         if (dptsr_planes != rcrtc->group->dptsr_planes) {
 381                 rcar_du_group_write(rcrtc->group, DPTSR,
 382                                     (dptsr_planes << 16) | dptsr_planes);
 383                 rcrtc->group->dptsr_planes = dptsr_planes;
 384
 385                 if (rcrtc->group->used_crtcs)
 386                         rcar_du_group_restart(rcrtc->group);
 387         }
 388
 389         /* Restart the group if plane sources have changed. */
 390         if (rcrtc->group->need_restart)
 391                 rcar_du_group_restart(rcrtc->group);
 392
 393         mutex_unlock(&rcrtc->group->lock);
 394
 395         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 396                             dspr);
 397 }
 398
 399 /* -----------------------------------------------------------------------------
 400  * Page Flip
 401  */
 402
 403 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 404 {
 405         struct drm_pending_vblank_event *event;
 406         struct drm_device *dev = rcrtc->crtc.dev;
 407         unsigned long flags;
 408
 409         spin_lock_irqsave(&dev->event_lock, flags);
 410         event = rcrtc->event;
 411         rcrtc->event = NULL;
 412         spin_unlock_irqrestore(&dev->event_lock, flags);
 413
 414         if (event == NULL)
 415                 return;
 416
 417         spin_lock_irqsave(&dev->event_lock, flags);
 418         drm_crtc_send_vblank_event(&rcrtc->crtc, event);
 419         wake_up(&rcrtc->flip_wait);
 420         spin_unlock_irqrestore(&dev->event_lock, flags);
 421
 422         drm_crtc_vblank_put(&rcrtc->crtc);
 423 }
 424
 425 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 426 {
 427         struct drm_device *dev = rcrtc->crtc.dev;
 428         unsigned long flags;
 429         bool pending;
 430
 431         spin_lock_irqsave(&dev->event_lock, flags);
 432         pending = rcrtc->event != NULL;
 433         spin_unlock_irqrestore(&dev->event_lock, flags);
 434
 435         return pending;
 436 }
 437
 438 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 439 {
 440         struct rcar_du_device *rcdu = rcrtc->group->dev;
 441
 442         if (wait_event_timeout(rcrtc->flip_wait,
 443                                !rcar_du_crtc_page_flip_pending(rcrtc),
 444                                msecs_to_jiffies(50)))
 445                 return;
 446
 447         dev_warn(rcdu->dev, "page flip timeout\n");
 448
 449         rcar_du_crtc_finish_page_flip(rcrtc);
 450 }
 451
 452 /* -----------------------------------------------------------------------------
 453  * Start/Stop and Suspend/Resume
 454  */
 455
 456 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
 457 {
 458         /* Set display off and background to black */
 459         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 460         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 461
 462         /* Configure display timings and output routing */
 463         rcar_du_crtc_set_display_timing(rcrtc);
 464         rcar_du_group_set_routing(rcrtc->group);
 465
 466         /* Start with all planes disabled. */
 467         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 468
 469         /* Enable the VSP compositor. */
 470         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 471                 rcar_du_vsp_enable(rcrtc);
 472
 473         /* Turn vertical blanking interrupt reporting on. */
 474         drm_crtc_vblank_on(&rcrtc->crtc);
 475 }
 476
 477 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 478 {
 479         bool interlaced;
 480
 481         /*
 482          * Select master sync mode. This enables display operation in master
 483          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 484          * actively driven).
 485          */
 486         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 487         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 488                              (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 489                              DSYSR_TVM_MASTER);
 490
 491         rcar_du_group_start_stop(rcrtc->group, true);
 492 }
 493
 494 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
 495 {
 496         struct rcar_du_device *rcdu = rcrtc->group->dev;
 497         struct drm_crtc *crtc = &rcrtc->crtc;
 498         u32 status;
 499
 500         /* Make sure vblank interrupts are enabled. */
 501         drm_crtc_vblank_get(crtc);
 502
 503         /*
 504          * Disable planes and calculate how many vertical blanking interrupts we
 505          * have to wait for. If a vertical blanking interrupt has been triggered
 506          * but not processed yet, we don't know whether it occurred before or
 507          * after the planes got disabled. We thus have to wait for two vblank
 508          * interrupts in that case.
 509          */
 510         spin_lock_irq(&rcrtc->vblank_lock);
 511         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 512         status = rcar_du_crtc_read(rcrtc, DSSR);
 513         rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
 514         spin_unlock_irq(&rcrtc->vblank_lock);
 515
 516         if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
 517                                 msecs_to_jiffies(100)))
 518                 dev_warn(rcdu->dev, "vertical blanking timeout\n");
 519
 520         drm_crtc_vblank_put(crtc);
 521 }
 522
 523 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 524 {
 525         struct drm_crtc *crtc = &rcrtc->crtc;
 526
 527         /*
 528          * Disable all planes and wait for the change to take effect. This is
 529          * required as the plane enable registers are updated on vblank, and no
 530          * vblank will occur once the CRTC is stopped. Disabling planes when
 531          * starting the CRTC thus wouldn't be enough as it would start scanning
 532          * out immediately from old frame buffers until the next vblank.
 533          *
 534          * This increases the CRTC stop delay, especially when multiple CRTCs
 535          * are stopped in one operation as we now wait for one vblank per CRTC.
 536          * Whether this can be improved needs to be researched.
 537          */
 538         rcar_du_crtc_disable_planes(rcrtc);
 539
 540         /*
 541          * Disable vertical blanking interrupt reporting. We first need to wait
 542          * for page flip completion before stopping the CRTC as userspace
 543          * expects page flips to eventually complete.
 544          */
 545         rcar_du_crtc_wait_page_flip(rcrtc);
 546         drm_crtc_vblank_off(crtc);
 547
 548         /* Disable the VSP compositor. */
 549         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 550                 rcar_du_vsp_disable(rcrtc);
 551
 552         /*
 553          * Select switch sync mode. This stops display operation and configures
 554          * the HSYNC and VSYNC signals as inputs.
 555          */
 556         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 557
 558         rcar_du_group_start_stop(rcrtc->group, false);
 559 }
 560
 561 /* -----------------------------------------------------------------------------
 562  * CRTC Functions
 563  */
 564
 565 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
 566                                        struct drm_crtc_state *old_state)
 567 {
 568         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 569
 570         /*
 571          * If the CRTC has already been setup by the .atomic_begin() handler we
 572          * can skip the setup stage.
 573          */
 574         if (!rcrtc->initialized) {
 575                 rcar_du_crtc_get(rcrtc);
 576                 rcar_du_crtc_setup(rcrtc);
 577                 rcrtc->initialized = true;
 578         }
 579
 580         rcar_du_crtc_start(rcrtc);
 581 }
 582
 583 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
 584                                         struct drm_crtc_state *old_state)
 585 {
 586         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 587
 588         rcar_du_crtc_stop(rcrtc);
 589         rcar_du_crtc_put(rcrtc);
 590
 591         spin_lock_irq(&crtc->dev->event_lock);
 592         if (crtc->state->event) {
 593                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 594                 crtc->state->event = NULL;
 595         }
 596         spin_unlock_irq(&crtc->dev->event_lock);
 597
 598         rcrtc->initialized = false;
 599         rcrtc->outputs = 0;
 600 }
 601
 602 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
 603                                       struct drm_crtc_state *old_crtc_state)
 604 {
 605         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 606
 607         WARN_ON(!crtc->state->enable);
 608
 609         /*
 610          * If a mode set is in progress we can be called with the CRTC disabled.
 611          * We then need to first setup the CRTC in order to configure planes.
 612          * The .atomic_enable() handler will notice and skip the CRTC setup.
 613          */
 614         if (!rcrtc->initialized) {
 615                 rcar_du_crtc_get(rcrtc);
 616                 rcar_du_crtc_setup(rcrtc);
 617                 rcrtc->initialized = true;
 618         }
 619
 620         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 621                 rcar_du_vsp_atomic_begin(rcrtc);
 622 }
 623
 624 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
 625                                       struct drm_crtc_state *old_crtc_state)
 626 {
 627         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 628         struct drm_device *dev = rcrtc->crtc.dev;
 629         unsigned long flags;
 630
 631         rcar_du_crtc_update_planes(rcrtc);
 632
 633         if (crtc->state->event) {
 634                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 635
 636                 spin_lock_irqsave(&dev->event_lock, flags);
 637                 rcrtc->event = crtc->state->event;
 638                 crtc->state->event = NULL;
 639                 spin_unlock_irqrestore(&dev->event_lock, flags);
 640         }
 641
 642         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 643                 rcar_du_vsp_atomic_flush(rcrtc);
 644 }
 645
 646 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 647         .atomic_begin = rcar_du_crtc_atomic_begin,
 648         .atomic_flush = rcar_du_crtc_atomic_flush,
 649         .atomic_enable = rcar_du_crtc_atomic_enable,
 650         .atomic_disable = rcar_du_crtc_atomic_disable,
 651 };
 652
 653 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
 654 {
 655         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 656
 657         rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 658         rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 659         rcrtc->vblank_enable = true;
 660
 661         return 0;
 662 }
 663
 664 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
 665 {
 666         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 667
 668         rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 669         rcrtc->vblank_enable = false;
 670 }
 671
 672 static const struct drm_crtc_funcs crtc_funcs = {
 673         .reset = drm_atomic_helper_crtc_reset,
 674         .destroy = drm_crtc_cleanup,
 675         .set_config = drm_atomic_helper_set_config,
 676         .page_flip = drm_atomic_helper_page_flip,
 677         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 678         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 679         .enable_vblank = rcar_du_crtc_enable_vblank,
 680         .disable_vblank = rcar_du_crtc_disable_vblank,
 681 };
 682
 683 /* -----------------------------------------------------------------------------
 684  * Interrupt Handling
 685  */
 686
 687 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 688 {
 689         struct rcar_du_crtc *rcrtc = arg;
 690         struct rcar_du_device *rcdu = rcrtc->group->dev;
 691         irqreturn_t ret = IRQ_NONE;
 692         u32 status;
 693
 694         spin_lock(&rcrtc->vblank_lock);
 695
 696         status = rcar_du_crtc_read(rcrtc, DSSR);
 697         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 698
 699         if (status & DSSR_VBK) {
 700                 /*
 701                  * Wake up the vblank wait if the counter reaches 0. This must
 702                  * be protected by the vblank_lock to avoid races in
 703                  * rcar_du_crtc_disable_planes().
 704                  */
 705                 if (rcrtc->vblank_count) {
 706                         if (--rcrtc->vblank_count == 0)
 707                                 wake_up(&rcrtc->vblank_wait);
 708                 }
 709         }
 710
 711         spin_unlock(&rcrtc->vblank_lock);
 712
 713         if (status & DSSR_VBK) {
 714                 if (rcdu->info->gen < 3) {
 715                         drm_crtc_handle_vblank(&rcrtc->crtc);
 716                         rcar_du_crtc_finish_page_flip(rcrtc);
 717                 }
 718
 719                 ret = IRQ_HANDLED;
 720         }
 721
 722         return ret;
 723 }
 724
 725 /* -----------------------------------------------------------------------------
 726  * Initialization
 727  */
 728
 729 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 730 {
 731         static const unsigned int mmio_offsets[] = {
 732                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
 733         };
 734
 735         struct rcar_du_device *rcdu = rgrp->dev;
 736         struct platform_device *pdev = to_platform_device(rcdu->dev);
 737         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 738         struct drm_crtc *crtc = &rcrtc->crtc;
 739         struct drm_plane *primary;
 740         unsigned int irqflags;
 741         struct clk *clk;
 742         char clk_name[9];
 743         char *name;
 744         int irq;
 745         int ret;
 746
 747         /* Get the CRTC clock and the optional external clock. */
 748         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 749                 sprintf(clk_name, "du.%u", index);
 750                 name = clk_name;
 751         } else {
 752                 name = NULL;
 753         }
 754
 755         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 756         if (IS_ERR(rcrtc->clock)) {
 757                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 758                 return PTR_ERR(rcrtc->clock);
 759         }
 760
 761         sprintf(clk_name, "dclkin.%u", index);
 762         clk = devm_clk_get(rcdu->dev, clk_name);
 763         if (!IS_ERR(clk)) {
 764                 rcrtc->extclock = clk;
 765         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 766                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 767                 return -EPROBE_DEFER;
 768         }
 769
 770         init_waitqueue_head(&rcrtc->flip_wait);
 771         init_waitqueue_head(&rcrtc->vblank_wait);
 772         spin_lock_init(&rcrtc->vblank_lock);
 773
 774         rcrtc->group = rgrp;
 775         rcrtc->mmio_offset = mmio_offsets[index];
 776         rcrtc->index = index;
 777
 778         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
 779                 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
 780         else
 781                 primary = &rgrp->planes[index % 2].plane;
 782
 783         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary,
 784                                         NULL, &crtc_funcs, NULL);
 785         if (ret < 0)
 786                 return ret;
 787
 788         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 789
 790         /* Start with vertical blanking interrupt reporting disabled. */
 791         drm_crtc_vblank_off(crtc);
 792
 793         /* Register the interrupt handler. */
 794         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 795                 irq = platform_get_irq(pdev, index);
 796                 irqflags = 0;
 797         } else {
 798                 irq = platform_get_irq(pdev, 0);
 799                 irqflags = IRQF_SHARED;
 800         }
 801
 802         if (irq < 0) {
 803                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 804                 return irq;
 805         }
 806
 807         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 808                                dev_name(rcdu->dev), rcrtc);
 809         if (ret < 0) {
 810                 dev_err(rcdu->dev,
 811                         "failed to register IRQ for CRTC %u\n", index);
 812                 return ret;
 813         }
 814
 815         return 0;
 816 }