drivers/gpu/drm/sun4i/sun4i_dotclock.c

   1 /*
   2  * Copyright (C) 2016 Free Electrons
   3  * Copyright (C) 2016 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15
  16 #include "sun4i_tcon.h"
  17 #include "sun4i_dotclock.h"
  18
  19 struct sun4i_dclk {
  20         struct clk_hw           hw;
  21         struct regmap           *regmap;
  22         struct sun4i_tcon       *tcon;
  23 };
  24
  25 static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
  26 {
  27         return container_of(hw, struct sun4i_dclk, hw);
  28 }
  29
  30 static void sun4i_dclk_disable(struct clk_hw *hw)
  31 {
  32         struct sun4i_dclk *dclk = hw_to_dclk(hw);
  33
  34         regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  35                            BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
  36 }
  37
  38 static int sun4i_dclk_enable(struct clk_hw *hw)
  39 {
  40         struct sun4i_dclk *dclk = hw_to_dclk(hw);
  41
  42         return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  43                                   BIT(SUN4I_TCON0_DCLK_GATE_BIT),
  44                                   BIT(SUN4I_TCON0_DCLK_GATE_BIT));
  45 }
  46
  47 static int sun4i_dclk_is_enabled(struct clk_hw *hw)
  48 {
  49         struct sun4i_dclk *dclk = hw_to_dclk(hw);
  50         u32 val;
  51
  52         regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  53
  54         return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
  55 }
  56
  57 static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
  58                                             unsigned long parent_rate)
  59 {
  60         struct sun4i_dclk *dclk = hw_to_dclk(hw);
  61         u32 val;
  62
  63         regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  64
  65         val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
  66         val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
  67
  68         if (!val)
  69                 val = 1;
  70
  71         return parent_rate / val;
  72 }
  73
  74 static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
  75                                   unsigned long *parent_rate)
  76 {
  77         struct sun4i_dclk *dclk = hw_to_dclk(hw);
  78         struct sun4i_tcon *tcon = dclk->tcon;
  79         unsigned long best_parent = 0;
  80         u8 best_div = 1;
  81         int i;
  82
  83         for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) {
  84                 unsigned long ideal = rate * i;
  85                 unsigned long rounded;
  86
  87                 rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
  88                                             ideal);
  89
  90                 if (rounded == ideal) {
  91                         best_parent = rounded;
  92                         best_div = i;
  93                         goto out;
  94                 }
  95
  96                 if (abs(rate - rounded / i) <
  97                     abs(rate - best_parent / best_div)) {
  98                         best_parent = rounded;
  99                         best_div = i;
 100                 }
 101         }
 102
 103 out:
 104         *parent_rate = best_parent;
 105
 106         return best_parent / best_div;
 107 }
 108
 109 static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 110                                unsigned long parent_rate)
 111 {
 112         struct sun4i_dclk *dclk = hw_to_dclk(hw);
 113         u8 div = parent_rate / rate;
 114
 115         return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
 116                                   GENMASK(6, 0), div);
 117 }
 118
 119 static int sun4i_dclk_get_phase(struct clk_hw *hw)
 120 {
 121         struct sun4i_dclk *dclk = hw_to_dclk(hw);
 122         u32 val;
 123
 124         regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
 125
 126         val >>= 28;
 127         val &= 3;
 128
 129         return val * 120;
 130 }
 131
 132 static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
 133 {
 134         struct sun4i_dclk *dclk = hw_to_dclk(hw);
 135
 136         regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
 137                            GENMASK(29, 28),
 138                            degrees / 120);
 139
 140         return 0;
 141 }
 142
 143 static const struct clk_ops sun4i_dclk_ops = {
 144         .disable        = sun4i_dclk_disable,
 145         .enable         = sun4i_dclk_enable,
 146         .is_enabled     = sun4i_dclk_is_enabled,
 147
 148         .recalc_rate    = sun4i_dclk_recalc_rate,
 149         .round_rate     = sun4i_dclk_round_rate,
 150         .set_rate       = sun4i_dclk_set_rate,
 151
 152         .get_phase      = sun4i_dclk_get_phase,
 153         .set_phase      = sun4i_dclk_set_phase,
 154 };
 155
 156 int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
 157 {
 158         const char *clk_name, *parent_name;
 159         struct clk_init_data init;
 160         struct sun4i_dclk *dclk;
 161         int ret;
 162
 163         parent_name = __clk_get_name(tcon->sclk0);
 164         ret = of_property_read_string_index(dev->of_node,
 165                                             "clock-output-names", 0,
 166                                             &clk_name);
 167         if (ret)
 168                 return ret;
 169
 170         dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
 171         if (!dclk)
 172                 return -ENOMEM;
 173         dclk->tcon = tcon;
 174
 175         init.name = clk_name;
 176         init.ops = &sun4i_dclk_ops;
 177         init.parent_names = &parent_name;
 178         init.num_parents = 1;
 179         init.flags = CLK_SET_RATE_PARENT;
 180
 181         dclk->regmap = tcon->regs;
 182         dclk->hw.init = &init;
 183
 184         tcon->dclk = clk_register(dev, &dclk->hw);
 185         if (IS_ERR(tcon->dclk))
 186                 return PTR_ERR(tcon->dclk);
 187
 188         return 0;
 189 }
 190 EXPORT_SYMBOL(sun4i_dclk_create);
 191
 192 int sun4i_dclk_free(struct sun4i_tcon *tcon)
 193 {
 194         clk_unregister(tcon->dclk);
 195         return 0;
 196 }
 197 EXPORT_SYMBOL(sun4i_dclk_free);