drivers/gpu/drm/sun4i/sun4i_tcon.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_encoder.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_of.h>
  20
  21 #include <uapi/drm/drm_mode.h>
  22
  23 #include <linux/component.h>
  24 #include <linux/ioport.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30
  31 #include "sun4i_crtc.h"
  32 #include "sun4i_dotclock.h"
  33 #include "sun4i_drv.h"
  34 #include "sun4i_lvds.h"
  35 #include "sun4i_rgb.h"
  36 #include "sun4i_tcon.h"
  37 #include "sunxi_engine.h"
  38
  39 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
  40 {
  41         struct drm_connector *connector;
  42         struct drm_connector_list_iter iter;
  43
  44         drm_connector_list_iter_begin(encoder->dev, &iter);
  45         drm_for_each_connector_iter(connector, &iter)
  46                 if (connector->encoder == encoder) {
  47                         drm_connector_list_iter_end(&iter);
  48                         return connector;
  49                 }
  50         drm_connector_list_iter_end(&iter);
  51
  52         return NULL;
  53 }
  54
  55 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
  56 {
  57         struct drm_connector *connector;
  58         struct drm_display_info *info;
  59
  60         connector = sun4i_tcon_get_connector(encoder);
  61         if (!connector)
  62                 return -EINVAL;
  63
  64         info = &connector->display_info;
  65         if (info->num_bus_formats != 1)
  66                 return -EINVAL;
  67
  68         switch (info->bus_formats[0]) {
  69         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  70                 return 18;
  71
  72         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  73         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  74                 return 24;
  75         }
  76
  77         return -EINVAL;
  78 }
  79
  80 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  81                                           bool enabled)
  82 {
  83         struct clk *clk;
  84
  85         switch (channel) {
  86         case 0:
  87                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  88                                    SUN4I_TCON0_CTL_TCON_ENABLE,
  89                                    enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
  90                 clk = tcon->dclk;
  91                 break;
  92         case 1:
  93                 WARN_ON(!tcon->quirks->has_channel_1);
  94                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  95                                    SUN4I_TCON1_CTL_TCON_ENABLE,
  96                                    enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
  97                 clk = tcon->sclk1;
  98                 break;
  99         default:
 100                 DRM_WARN("Unknown channel... doing nothing\n");
 101                 return;
 102         }
 103
 104         if (enabled)
 105                 clk_prepare_enable(clk);
 106         else
 107                 clk_disable_unprepare(clk);
 108 }
 109
 110 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
 111                                        const struct drm_encoder *encoder,
 112                                        bool enabled)
 113 {
 114         if (enabled) {
 115                 u8 val;
 116
 117                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 118                                    SUN4I_TCON0_LVDS_IF_EN,
 119                                    SUN4I_TCON0_LVDS_IF_EN);
 120
 121                 /*
 122                  * As their name suggest, these values only apply to the A31
 123                  * and later SoCs. We'll have to rework this when merging
 124                  * support for the older SoCs.
 125                  */
 126                 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 127                              SUN6I_TCON0_LVDS_ANA0_C(2) |
 128                              SUN6I_TCON0_LVDS_ANA0_V(3) |
 129                              SUN6I_TCON0_LVDS_ANA0_PD(2) |
 130                              SUN6I_TCON0_LVDS_ANA0_EN_LDO);
 131                 udelay(2);
 132
 133                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 134                                    SUN6I_TCON0_LVDS_ANA0_EN_MB,
 135                                    SUN6I_TCON0_LVDS_ANA0_EN_MB);
 136                 udelay(2);
 137
 138                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 139                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
 140                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
 141
 142                 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
 143                         val = 7;
 144                 else
 145                         val = 0xf;
 146
 147                 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 148                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
 149                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
 150         } else {
 151                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 152                                    SUN4I_TCON0_LVDS_IF_EN, 0);
 153         }
 154 }
 155
 156 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
 157                            const struct drm_encoder *encoder,
 158                            bool enabled)
 159 {
 160         bool is_lvds = false;
 161         int channel;
 162
 163         switch (encoder->encoder_type) {
 164         case DRM_MODE_ENCODER_LVDS:
 165                 is_lvds = true;
 166                 /* Fallthrough */
 167         case DRM_MODE_ENCODER_NONE:
 168                 channel = 0;
 169                 break;
 170         case DRM_MODE_ENCODER_TMDS:
 171         case DRM_MODE_ENCODER_TVDAC:
 172                 channel = 1;
 173                 break;
 174         default:
 175                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 176                 return;
 177         }
 178
 179         if (is_lvds && !enabled)
 180                 sun4i_tcon_lvds_set_status(tcon, encoder, false);
 181
 182         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 183                            SUN4I_TCON_GCTL_TCON_ENABLE,
 184                            enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
 185
 186         if (is_lvds && enabled)
 187                 sun4i_tcon_lvds_set_status(tcon, encoder, true);
 188
 189         sun4i_tcon_channel_set_status(tcon, channel, enabled);
 190 }
 191
 192 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 193 {
 194         u32 mask, val = 0;
 195
 196         DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 197
 198         mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
 199                SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
 200
 201         if (enable)
 202                 val = mask;
 203
 204         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
 205 }
 206 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 207
 208 /*
 209  * This function is a helper for TCON output muxing. The TCON output
 210  * muxing control register in earlier SoCs (without the TCON TOP block)
 211  * are located in TCON0. This helper returns a pointer to TCON0's
 212  * sun4i_tcon structure, or NULL if not found.
 213  */
 214 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
 215 {
 216         struct sun4i_drv *drv = drm->dev_private;
 217         struct sun4i_tcon *tcon;
 218
 219         list_for_each_entry(tcon, &drv->tcon_list, list)
 220                 if (tcon->id == 0)
 221                         return tcon;
 222
 223         dev_warn(drm->dev,
 224                  "TCON0 not found, display output muxing may not work\n");
 225
 226         return NULL;
 227 }
 228
 229 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
 230                         const struct drm_encoder *encoder)
 231 {
 232         int ret = -ENOTSUPP;
 233
 234         if (tcon->quirks->set_mux)
 235                 ret = tcon->quirks->set_mux(tcon, encoder);
 236
 237         DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
 238                          encoder->name, encoder->crtc->name, ret);
 239 }
 240
 241 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
 242                                     int channel)
 243 {
 244         int delay = mode->vtotal - mode->vdisplay;
 245
 246         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 247                 delay /= 2;
 248
 249         if (channel == 1)
 250                 delay -= 2;
 251
 252         delay = min(delay, 30);
 253
 254         DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
 255
 256         return delay;
 257 }
 258
 259 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 260                                         const struct drm_display_mode *mode)
 261 {
 262         /* Configure the dot clock */
 263         clk_set_rate_exclusive(tcon->dclk, mode->crtc_clock * 1000);
 264
 265         /* Set the resolution */
 266         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
 267                      SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
 268                      SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
 269 }
 270
 271 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 272                                       const struct drm_encoder *encoder,
 273                                       const struct drm_display_mode *mode)
 274 {
 275         unsigned int bp;
 276         u8 clk_delay;
 277         u32 reg, val = 0;
 278
 279         tcon->dclk_min_div = 7;
 280         tcon->dclk_max_div = 7;
 281         sun4i_tcon0_mode_set_common(tcon, mode);
 282
 283         /* Adjust clock delay */
 284         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 285         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 286                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 287                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 288
 289         /*
 290          * This is called a backporch in the register documentation,
 291          * but it really is the back porch + hsync
 292          */
 293         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 294         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 295                          mode->crtc_htotal, bp);
 296
 297         /* Set horizontal display timings */
 298         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 299                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
 300                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 301
 302         /*
 303          * This is called a backporch in the register documentation,
 304          * but it really is the back porch + hsync
 305          */
 306         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 307         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 308                          mode->crtc_vtotal, bp);
 309
 310         /* Set vertical display timings */
 311         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 312                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 313                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 314
 315         reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
 316                 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
 317                 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
 318         if (sun4i_tcon_get_pixel_depth(encoder) == 24)
 319                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
 320         else
 321                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
 322
 323         regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
 324
 325         /* Setup the polarity of the various signals */
 326         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 327                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 328
 329         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 330                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 331
 332         regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
 333
 334         /* Map output pins to channel 0 */
 335         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 336                            SUN4I_TCON_GCTL_IOMAP_MASK,
 337                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 338
 339         /* Enable the output on the pins */
 340         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
 341 }
 342
 343 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
 344                                      const struct drm_display_mode *mode)
 345 {
 346         unsigned int bp, hsync, vsync;
 347         u8 clk_delay;
 348         u32 val = 0;
 349
 350         tcon->dclk_min_div = 6;
 351         tcon->dclk_max_div = 127;
 352         sun4i_tcon0_mode_set_common(tcon, mode);
 353
 354         /* Adjust clock delay */
 355         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 356         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 357                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 358                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 359
 360         /*
 361          * This is called a backporch in the register documentation,
 362          * but it really is the back porch + hsync
 363          */
 364         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 365         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 366                          mode->crtc_htotal, bp);
 367
 368         /* Set horizontal display timings */
 369         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 370                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
 371                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 372
 373         /*
 374          * This is called a backporch in the register documentation,
 375          * but it really is the back porch + hsync
 376          */
 377         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 378         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 379                          mode->crtc_vtotal, bp);
 380
 381         /* Set vertical display timings */
 382         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 383                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 384                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 385
 386         /* Set Hsync and Vsync length */
 387         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 388         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 389         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 390         regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
 391                      SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
 392                      SUN4I_TCON0_BASIC3_H_SYNC(hsync));
 393
 394         /* Setup the polarity of the various signals */
 395         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 396                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 397
 398         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 399                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 400
 401         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
 402                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
 403                            val);
 404
 405         /* Map output pins to channel 0 */
 406         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 407                            SUN4I_TCON_GCTL_IOMAP_MASK,
 408                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 409
 410         /* Enable the output on the pins */
 411         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
 412 }
 413
 414 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 415                                  const struct drm_display_mode *mode)
 416 {
 417         unsigned int bp, hsync, vsync, vtotal;
 418         u8 clk_delay;
 419         u32 val;
 420
 421         WARN_ON(!tcon->quirks->has_channel_1);
 422
 423         /* Configure the dot clock */
 424         clk_set_rate_exclusive(tcon->sclk1, mode->crtc_clock * 1000);
 425
 426         /* Adjust clock delay */
 427         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
 428         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 429                            SUN4I_TCON1_CTL_CLK_DELAY_MASK,
 430                            SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
 431
 432         /* Set interlaced mode */
 433         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 434                 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
 435         else
 436                 val = 0;
 437         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 438                            SUN4I_TCON1_CTL_INTERLACE_ENABLE,
 439                            val);
 440
 441         /* Set the input resolution */
 442         regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
 443                      SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
 444                      SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
 445
 446         /* Set the upscaling resolution */
 447         regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
 448                      SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
 449                      SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
 450
 451         /* Set the output resolution */
 452         regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
 453                      SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
 454                      SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
 455
 456         /* Set horizontal display timings */
 457         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 458         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 459                          mode->htotal, bp);
 460         regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
 461                      SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
 462                      SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 463
 464         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 465         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 466                          mode->crtc_vtotal, bp);
 467
 468         /*
 469          * The vertical resolution needs to be doubled in all
 470          * cases. We could use crtc_vtotal and always multiply by two,
 471          * but that leads to a rounding error in interlace when vtotal
 472          * is odd.
 473          *
 474          * This happens with TV's PAL for example, where vtotal will
 475          * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
 476          * 624, which apparently confuses the hardware.
 477          *
 478          * To work around this, we will always use vtotal, and
 479          * multiply by two only if we're not in interlace.
 480          */
 481         vtotal = mode->vtotal;
 482         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
 483                 vtotal = vtotal * 2;
 484
 485         /* Set vertical display timings */
 486         regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
 487                      SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
 488                      SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
 489
 490         /* Set Hsync and Vsync length */
 491         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 492         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 493         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 494         regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
 495                      SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
 496                      SUN4I_TCON1_BASIC5_H_SYNC(hsync));
 497
 498         /* Map output pins to channel 1 */
 499         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 500                            SUN4I_TCON_GCTL_IOMAP_MASK,
 501                            SUN4I_TCON_GCTL_IOMAP_TCON1);
 502 }
 503
 504 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
 505                          const struct drm_encoder *encoder,
 506                          const struct drm_display_mode *mode)
 507 {
 508         switch (encoder->encoder_type) {
 509         case DRM_MODE_ENCODER_LVDS:
 510                 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
 511                 break;
 512         case DRM_MODE_ENCODER_NONE:
 513                 sun4i_tcon0_mode_set_rgb(tcon, mode);
 514                 sun4i_tcon_set_mux(tcon, 0, encoder);
 515                 break;
 516         case DRM_MODE_ENCODER_TVDAC:
 517         case DRM_MODE_ENCODER_TMDS:
 518                 sun4i_tcon1_mode_set(tcon, mode);
 519                 sun4i_tcon_set_mux(tcon, 1, encoder);
 520                 break;
 521         default:
 522                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 523         }
 524 }
 525 EXPORT_SYMBOL(sun4i_tcon_mode_set);
 526
 527 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
 528                                         struct sun4i_crtc *scrtc)
 529 {
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&dev->event_lock, flags);
 533         if (scrtc->event) {
 534                 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
 535                 drm_crtc_vblank_put(&scrtc->crtc);
 536                 scrtc->event = NULL;
 537         }
 538         spin_unlock_irqrestore(&dev->event_lock, flags);
 539 }
 540
 541 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 542 {
 543         struct sun4i_tcon *tcon = private;
 544         struct drm_device *drm = tcon->drm;
 545         struct sun4i_crtc *scrtc = tcon->crtc;
 546         unsigned int status;
 547
 548         regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 549
 550         if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
 551                         SUN4I_TCON_GINT0_VBLANK_INT(1))))
 552                 return IRQ_NONE;
 553
 554         drm_crtc_handle_vblank(&scrtc->crtc);
 555         sun4i_tcon_finish_page_flip(drm, scrtc);
 556
 557         /* Acknowledge the interrupt */
 558         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
 559                            SUN4I_TCON_GINT0_VBLANK_INT(0) |
 560                            SUN4I_TCON_GINT0_VBLANK_INT(1),
 561                            0);
 562
 563         return IRQ_HANDLED;
 564 }
 565
 566 static int sun4i_tcon_init_clocks(struct device *dev,
 567                                   struct sun4i_tcon *tcon)
 568 {
 569         tcon->clk = devm_clk_get(dev, "ahb");
 570         if (IS_ERR(tcon->clk)) {
 571                 dev_err(dev, "Couldn't get the TCON bus clock\n");
 572                 return PTR_ERR(tcon->clk);
 573         }
 574         clk_prepare_enable(tcon->clk);
 575
 576         tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
 577         if (IS_ERR(tcon->sclk0)) {
 578                 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
 579                 return PTR_ERR(tcon->sclk0);
 580         }
 581
 582         if (tcon->quirks->has_channel_1) {
 583                 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
 584                 if (IS_ERR(tcon->sclk1)) {
 585                         dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
 586                         return PTR_ERR(tcon->sclk1);
 587                 }
 588         }
 589
 590         return 0;
 591 }
 592
 593 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
 594 {
 595         clk_disable_unprepare(tcon->clk);
 596 }
 597
 598 static int sun4i_tcon_init_irq(struct device *dev,
 599                                struct sun4i_tcon *tcon)
 600 {
 601         struct platform_device *pdev = to_platform_device(dev);
 602         int irq, ret;
 603
 604         irq = platform_get_irq(pdev, 0);
 605         if (irq < 0) {
 606                 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
 607                 return irq;
 608         }
 609
 610         ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
 611                                dev_name(dev), tcon);
 612         if (ret) {
 613                 dev_err(dev, "Couldn't request the IRQ\n");
 614                 return ret;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static struct regmap_config sun4i_tcon_regmap_config = {
 621         .reg_bits       = 32,
 622         .val_bits       = 32,
 623         .reg_stride     = 4,
 624         .max_register   = 0x800,
 625 };
 626
 627 static int sun4i_tcon_init_regmap(struct device *dev,
 628                                   struct sun4i_tcon *tcon)
 629 {
 630         struct platform_device *pdev = to_platform_device(dev);
 631         struct resource *res;
 632         void __iomem *regs;
 633
 634         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 635         regs = devm_ioremap_resource(dev, res);
 636         if (IS_ERR(regs))
 637                 return PTR_ERR(regs);
 638
 639         tcon->regs = devm_regmap_init_mmio(dev, regs,
 640                                            &sun4i_tcon_regmap_config);
 641         if (IS_ERR(tcon->regs)) {
 642                 dev_err(dev, "Couldn't create the TCON regmap\n");
 643                 return PTR_ERR(tcon->regs);
 644         }
 645
 646         /* Make sure the TCON is disabled and all IRQs are off */
 647         regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
 648         regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
 649         regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
 650
 651         /* Disable IO lines and set them to tristate */
 652         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
 653         regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
 654
 655         return 0;
 656 }
 657
 658 /*
 659  * On SoCs with the old display pipeline design (Display Engine 1.0),
 660  * the TCON is always tied to just one backend. Hence we can traverse
 661  * the of_graph upwards to find the backend our tcon is connected to,
 662  * and take its ID as our own.
 663  *
 664  * We can either identify backends from their compatible strings, which
 665  * means maintaining a large list of them. Or, since the backend is
 666  * registered and binded before the TCON, we can just go through the
 667  * list of registered backends and compare the device node.
 668  *
 669  * As the structures now store engines instead of backends, here this
 670  * function in fact searches the corresponding engine, and the ID is
 671  * requested via the get_id function of the engine.
 672  */
 673 static struct sunxi_engine *
 674 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
 675                                 struct device_node *node)
 676 {
 677         struct device_node *port, *ep, *remote;
 678         struct sunxi_engine *engine = ERR_PTR(-EINVAL);
 679
 680         port = of_graph_get_port_by_id(node, 0);
 681         if (!port)
 682                 return ERR_PTR(-EINVAL);
 683
 684         /*
 685          * This only works if there is only one path from the TCON
 686          * to any display engine. Otherwise the probe order of the
 687          * TCONs and display engines is not guaranteed. They may
 688          * either bind to the wrong one, or worse, bind to the same
 689          * one if additional checks are not done.
 690          *
 691          * Bail out if there are multiple input connections.
 692          */
 693         if (of_get_available_child_count(port) != 1)
 694                 goto out_put_port;
 695
 696         /* Get the first connection without specifying an ID */
 697         ep = of_get_next_available_child(port, NULL);
 698         if (!ep)
 699                 goto out_put_port;
 700
 701         remote = of_graph_get_remote_port_parent(ep);
 702         if (!remote)
 703                 goto out_put_ep;
 704
 705         /* does this node match any registered engines? */
 706         list_for_each_entry(engine, &drv->engine_list, list)
 707                 if (remote == engine->node)
 708                         goto out_put_remote;
 709
 710         /* keep looking through upstream ports */
 711         engine = sun4i_tcon_find_engine_traverse(drv, remote);
 712
 713 out_put_remote:
 714         of_node_put(remote);
 715 out_put_ep:
 716         of_node_put(ep);
 717 out_put_port:
 718         of_node_put(port);
 719
 720         return engine;
 721 }
 722
 723 /*
 724  * The device tree binding says that the remote endpoint ID of any
 725  * connection between components, up to and including the TCON, of
 726  * the display pipeline should be equal to the actual ID of the local
 727  * component. Thus we can look at any one of the input connections of
 728  * the TCONs, and use that connection's remote endpoint ID as our own.
 729  *
 730  * Since the user of this function already finds the input port,
 731  * the port is passed in directly without further checks.
 732  */
 733 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
 734 {
 735         struct device_node *ep;
 736         int ret = -EINVAL;
 737
 738         /* try finding an upstream endpoint */
 739         for_each_available_child_of_node(port, ep) {
 740                 struct device_node *remote;
 741                 u32 reg;
 742
 743                 remote = of_graph_get_remote_endpoint(ep);
 744                 if (!remote)
 745                         continue;
 746
 747                 ret = of_property_read_u32(remote, "reg", &reg);
 748                 if (ret)
 749                         continue;
 750
 751                 ret = reg;
 752         }
 753
 754         return ret;
 755 }
 756
 757 /*
 758  * Once we know the TCON's id, we can look through the list of
 759  * engines to find a matching one. We assume all engines have
 760  * been probed and added to the list.
 761  */
 762 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
 763                                                         int id)
 764 {
 765         struct sunxi_engine *engine;
 766
 767         list_for_each_entry(engine, &drv->engine_list, list)
 768                 if (engine->id == id)
 769                         return engine;
 770
 771         return ERR_PTR(-EINVAL);
 772 }
 773
 774 /*
 775  * On SoCs with the old display pipeline design (Display Engine 1.0),
 776  * we assumed the TCON was always tied to just one backend. However
 777  * this proved not to be the case. On the A31, the TCON can select
 778  * either backend as its source. On the A20 (and likely on the A10),
 779  * the backend can choose which TCON to output to.
 780  *
 781  * The device tree binding says that the remote endpoint ID of any
 782  * connection between components, up to and including the TCON, of
 783  * the display pipeline should be equal to the actual ID of the local
 784  * component. Thus we should be able to look at any one of the input
 785  * connections of the TCONs, and use that connection's remote endpoint
 786  * ID as our own.
 787  *
 788  * However  the connections between the backend and TCON were assumed
 789  * to be always singular, and their endpoit IDs were all incorrectly
 790  * set to 0. This means for these old device trees, we cannot just look
 791  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
 792  * incorrectly identified as TCON0.
 793  *
 794  * This function first checks if the TCON node has 2 input endpoints.
 795  * If so, then the device tree is a corrected version, and it will use
 796  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
 797  * to fetch the ID and engine directly. If not, then it is likely an
 798  * old device trees, where the endpoint IDs were incorrect, but did not
 799  * have endpoint connections between the backend and TCON across
 800  * different display pipelines. It will fall back to the old method of
 801  * traversing the  of_graph to try and find a matching engine by device
 802  * node.
 803  *
 804  * In the case of single display pipeline device trees, either method
 805  * works.
 806  */
 807 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
 808                                                    struct device_node *node)
 809 {
 810         struct device_node *port;
 811         struct sunxi_engine *engine;
 812
 813         port = of_graph_get_port_by_id(node, 0);
 814         if (!port)
 815                 return ERR_PTR(-EINVAL);
 816
 817         /*
 818          * Is this a corrected device tree with cross pipeline
 819          * connections between the backend and TCON?
 820          */
 821         if (of_get_child_count(port) > 1) {
 822                 /* Get our ID directly from an upstream endpoint */
 823                 int id = sun4i_tcon_of_get_id_from_port(port);
 824
 825                 /* Get our engine by matching our ID */
 826                 engine = sun4i_tcon_get_engine_by_id(drv, id);
 827
 828                 of_node_put(port);
 829                 return engine;
 830         }
 831
 832         /* Fallback to old method by traversing input endpoints */
 833         of_node_put(port);
 834         return sun4i_tcon_find_engine_traverse(drv, node);
 835 }
 836
 837 static int sun4i_tcon_bind(struct device *dev, struct device *master,
 838                            void *data)
 839 {
 840         struct drm_device *drm = data;
 841         struct sun4i_drv *drv = drm->dev_private;
 842         struct sunxi_engine *engine;
 843         struct device_node *remote;
 844         struct sun4i_tcon *tcon;
 845         bool has_lvds_rst, has_lvds_alt, can_lvds;
 846         int ret;
 847
 848         engine = sun4i_tcon_find_engine(drv, dev->of_node);
 849         if (IS_ERR(engine)) {
 850                 dev_err(dev, "Couldn't find matching engine\n");
 851                 return -EPROBE_DEFER;
 852         }
 853
 854         tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
 855         if (!tcon)
 856                 return -ENOMEM;
 857         dev_set_drvdata(dev, tcon);
 858         tcon->drm = drm;
 859         tcon->dev = dev;
 860         tcon->id = engine->id;
 861         tcon->quirks = of_device_get_match_data(dev);
 862
 863         tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
 864         if (IS_ERR(tcon->lcd_rst)) {
 865                 dev_err(dev, "Couldn't get our reset line\n");
 866                 return PTR_ERR(tcon->lcd_rst);
 867         }
 868
 869         /* Make sure our TCON is reset */
 870         ret = reset_control_reset(tcon->lcd_rst);
 871         if (ret) {
 872                 dev_err(dev, "Couldn't deassert our reset line\n");
 873                 return ret;
 874         }
 875
 876         /*
 877          * This can only be made optional since we've had DT nodes
 878          * without the LVDS reset properties.
 879          *
 880          * If the property is missing, just disable LVDS, and print a
 881          * warning.
 882          */
 883         tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
 884         if (IS_ERR(tcon->lvds_rst)) {
 885                 dev_err(dev, "Couldn't get our reset line\n");
 886                 return PTR_ERR(tcon->lvds_rst);
 887         } else if (tcon->lvds_rst) {
 888                 has_lvds_rst = true;
 889                 reset_control_reset(tcon->lvds_rst);
 890         } else {
 891                 has_lvds_rst = false;
 892         }
 893
 894         /*
 895          * This can only be made optional since we've had DT nodes
 896          * without the LVDS reset properties.
 897          *
 898          * If the property is missing, just disable LVDS, and print a
 899          * warning.
 900          */
 901         if (tcon->quirks->has_lvds_alt) {
 902                 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
 903                 if (IS_ERR(tcon->lvds_pll)) {
 904                         if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
 905                                 has_lvds_alt = false;
 906                         } else {
 907                                 dev_err(dev, "Couldn't get the LVDS PLL\n");
 908                                 return PTR_ERR(tcon->lvds_pll);
 909                         }
 910                 } else {
 911                         has_lvds_alt = true;
 912                 }
 913         }
 914
 915         if (!has_lvds_rst || (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
 916                 dev_warn(dev,
 917                          "Missing LVDS properties, Please upgrade your DT\n");
 918                 dev_warn(dev, "LVDS output disabled\n");
 919                 can_lvds = false;
 920         } else {
 921                 can_lvds = true;
 922         }
 923
 924         ret = sun4i_tcon_init_clocks(dev, tcon);
 925         if (ret) {
 926                 dev_err(dev, "Couldn't init our TCON clocks\n");
 927                 goto err_assert_reset;
 928         }
 929
 930         ret = sun4i_tcon_init_regmap(dev, tcon);
 931         if (ret) {
 932                 dev_err(dev, "Couldn't init our TCON regmap\n");
 933                 goto err_free_clocks;
 934         }
 935
 936         ret = sun4i_dclk_create(dev, tcon);
 937         if (ret) {
 938                 dev_err(dev, "Couldn't create our TCON dot clock\n");
 939                 goto err_free_clocks;
 940         }
 941
 942         ret = sun4i_tcon_init_irq(dev, tcon);
 943         if (ret) {
 944                 dev_err(dev, "Couldn't init our TCON interrupts\n");
 945                 goto err_free_dotclock;
 946         }
 947
 948         tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
 949         if (IS_ERR(tcon->crtc)) {
 950                 dev_err(dev, "Couldn't create our CRTC\n");
 951                 ret = PTR_ERR(tcon->crtc);
 952                 goto err_free_dotclock;
 953         }
 954
 955         /*
 956          * If we have an LVDS panel connected to the TCON, we should
 957          * just probe the LVDS connector. Otherwise, just probe RGB as
 958          * we used to.
 959          */
 960         remote = of_graph_get_remote_node(dev->of_node, 1, 0);
 961         if (of_device_is_compatible(remote, "panel-lvds"))
 962                 if (can_lvds)
 963                         ret = sun4i_lvds_init(drm, tcon);
 964                 else
 965                         ret = -EINVAL;
 966         else
 967                 ret = sun4i_rgb_init(drm, tcon);
 968         of_node_put(remote);
 969
 970         if (ret < 0)
 971                 goto err_free_dotclock;
 972
 973         if (tcon->quirks->needs_de_be_mux) {
 974                 /*
 975                  * We assume there is no dynamic muxing of backends
 976                  * and TCONs, so we select the backend with same ID.
 977                  *
 978                  * While dynamic selection might be interesting, since
 979                  * the CRTC is tied to the TCON, while the layers are
 980                  * tied to the backends, this means, we will need to
 981                  * switch between groups of layers. There might not be
 982                  * a way to represent this constraint in DRM.
 983                  */
 984                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 985                                    SUN4I_TCON0_CTL_SRC_SEL_MASK,
 986                                    tcon->id);
 987                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 988                                    SUN4I_TCON1_CTL_SRC_SEL_MASK,
 989                                    tcon->id);
 990         }
 991
 992         list_add_tail(&tcon->list, &drv->tcon_list);
 993
 994         return 0;
 995
 996 err_free_dotclock:
 997         sun4i_dclk_free(tcon);
 998 err_free_clocks:
 999         sun4i_tcon_free_clocks(tcon);
1000 err_assert_reset:
1001         reset_control_assert(tcon->lcd_rst);
1002         return ret;
1003 }
1004
1005 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1006                               void *data)
1007 {
1008         struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1009
1010         list_del(&tcon->list);
1011         sun4i_dclk_free(tcon);
1012         sun4i_tcon_free_clocks(tcon);
1013 }
1014
1015 static const struct component_ops sun4i_tcon_ops = {
1016         .bind   = sun4i_tcon_bind,
1017         .unbind = sun4i_tcon_unbind,
1018 };
1019
1020 static int sun4i_tcon_probe(struct platform_device *pdev)
1021 {
1022         struct device_node *node = pdev->dev.of_node;
1023         struct drm_bridge *bridge;
1024         struct drm_panel *panel;
1025         int ret;
1026
1027         ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1028         if (ret == -EPROBE_DEFER)
1029                 return ret;
1030
1031         return component_add(&pdev->dev, &sun4i_tcon_ops);
1032 }
1033
1034 static int sun4i_tcon_remove(struct platform_device *pdev)
1035 {
1036         component_del(&pdev->dev, &sun4i_tcon_ops);
1037
1038         return 0;
1039 }
1040
1041 /* platform specific TCON muxing callbacks */
1042 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1043                                   const struct drm_encoder *encoder)
1044 {
1045         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1046         u32 shift;
1047
1048         if (!tcon0)
1049                 return -EINVAL;
1050
1051         switch (encoder->encoder_type) {
1052         case DRM_MODE_ENCODER_TMDS:
1053                 /* HDMI */
1054                 shift = 8;
1055                 break;
1056         default:
1057                 return -EINVAL;
1058         }
1059
1060         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1061                            0x3 << shift, tcon->id << shift);
1062
1063         return 0;
1064 }
1065
1066 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1067                                   const struct drm_encoder *encoder)
1068 {
1069         u32 val;
1070
1071         if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1072                 val = 1;
1073         else
1074                 val = 0;
1075
1076         /*
1077          * FIXME: Undocumented bits
1078          */
1079         return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1080 }
1081
1082 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1083                               const struct drm_encoder *encoder)
1084 {
1085         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1086         u32 shift;
1087
1088         if (!tcon0)
1089                 return -EINVAL;
1090
1091         switch (encoder->encoder_type) {
1092         case DRM_MODE_ENCODER_TMDS:
1093                 /* HDMI */
1094                 shift = 8;
1095                 break;
1096         default:
1097                 /* TODO A31 has MIPI DSI but A31s does not */
1098                 return -EINVAL;
1099         }
1100
1101         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1102                            0x3 << shift, tcon->id << shift);
1103
1104         return 0;
1105 }
1106
1107 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1108         .has_channel_1          = true,
1109         .set_mux                = sun4i_a10_tcon_set_mux,
1110 };
1111
1112 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1113         .has_channel_1          = true,
1114         .set_mux                = sun5i_a13_tcon_set_mux,
1115 };
1116
1117 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1118         .has_channel_1          = true,
1119         .has_lvds_alt           = true,
1120         .needs_de_be_mux        = true,
1121         .set_mux                = sun6i_tcon_set_mux,
1122 };
1123
1124 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1125         .has_channel_1          = true,
1126         .needs_de_be_mux        = true,
1127 };
1128
1129 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1130         .has_channel_1          = true,
1131         /* Same display pipeline structure as A10 */
1132         .set_mux                = sun4i_a10_tcon_set_mux,
1133 };
1134
1135 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1136         .has_lvds_alt           = true,
1137 };
1138
1139 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1140         /* nothing is supported */
1141 };
1142
1143 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1144         /* nothing is supported */
1145 };
1146
1147 /* sun4i_drv uses this list to check if a device node is a TCON */
1148 const struct of_device_id sun4i_tcon_of_table[] = {
1149         { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1150         { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1151         { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1152         { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1153         { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1154         { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1155         { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1156         { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1157         { }
1158 };
1159 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1160 EXPORT_SYMBOL(sun4i_tcon_of_table);
1161
1162 static struct platform_driver sun4i_tcon_platform_driver = {
1163         .probe          = sun4i_tcon_probe,
1164         .remove         = sun4i_tcon_remove,
1165         .driver         = {
1166                 .name           = "sun4i-tcon",
1167                 .of_match_table = sun4i_tcon_of_table,
1168         },
1169 };
1170 module_platform_driver(sun4i_tcon_platform_driver);
1171
1172 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1173 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1174 MODULE_LICENSE("GPL");