drivers/i2c/busses/i2c-altera.c

   1 /*
   2  *  Copyright Intel Corporation (C) 2017.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * Based on the i2c-axxia.c driver.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/clkdev.h>
  20 #include <linux/err.h>
  21 #include <linux/i2c.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/platform_device.h>
  28
  29 #define ALTR_I2C_TFR_CMD        0x00    /* Transfer Command register */
  30 #define     ALTR_I2C_TFR_CMD_STA        BIT(9)  /* send START before byte */
  31 #define     ALTR_I2C_TFR_CMD_STO        BIT(8)  /* send STOP after byte */
  32 #define     ALTR_I2C_TFR_CMD_RW_D       BIT(0)  /* Direction of transfer */
  33 #define ALTR_I2C_RX_DATA        0x04    /* RX data FIFO register */
  34 #define ALTR_I2C_CTRL           0x08    /* Control register */
  35 #define     ALTR_I2C_CTRL_RXT_SHFT      4       /* RX FIFO Threshold */
  36 #define     ALTR_I2C_CTRL_TCT_SHFT      2       /* TFER CMD FIFO Threshold */
  37 #define     ALTR_I2C_CTRL_BSPEED        BIT(1)  /* Bus Speed (1=Fast) */
  38 #define     ALTR_I2C_CTRL_EN    BIT(0)  /* Enable Core (1=Enable) */
  39 #define ALTR_I2C_ISER           0x0C    /* Interrupt Status Enable register */
  40 #define     ALTR_I2C_ISER_RXOF_EN       BIT(4)  /* Enable RX OVERFLOW IRQ */
  41 #define     ALTR_I2C_ISER_ARB_EN        BIT(3)  /* Enable ARB LOST IRQ */
  42 #define     ALTR_I2C_ISER_NACK_EN       BIT(2)  /* Enable NACK DET IRQ */
  43 #define     ALTR_I2C_ISER_RXRDY_EN      BIT(1)  /* Enable RX Ready IRQ */
  44 #define     ALTR_I2C_ISER_TXRDY_EN      BIT(0)  /* Enable TX Ready IRQ */
  45 #define ALTR_I2C_ISR            0x10    /* Interrupt Status register */
  46 #define     ALTR_I2C_ISR_RXOF           BIT(4)  /* RX OVERFLOW IRQ */
  47 #define     ALTR_I2C_ISR_ARB            BIT(3)  /* ARB LOST IRQ */
  48 #define     ALTR_I2C_ISR_NACK           BIT(2)  /* NACK DET IRQ */
  49 #define     ALTR_I2C_ISR_RXRDY          BIT(1)  /* RX Ready IRQ */
  50 #define     ALTR_I2C_ISR_TXRDY          BIT(0)  /* TX Ready IRQ */
  51 #define ALTR_I2C_STATUS         0x14    /* Status register */
  52 #define     ALTR_I2C_STAT_CORE          BIT(0)  /* Core Status (0=idle) */
  53 #define ALTR_I2C_TC_FIFO_LVL    0x18    /* Transfer FIFO LVL register */
  54 #define ALTR_I2C_RX_FIFO_LVL    0x1C    /* Receive FIFO LVL register */
  55 #define ALTR_I2C_SCL_LOW        0x20    /* SCL low count register */
  56 #define ALTR_I2C_SCL_HIGH       0x24    /* SCL high count register */
  57 #define ALTR_I2C_SDA_HOLD       0x28    /* SDA hold count register */
  58
  59 #define ALTR_I2C_ALL_IRQ        (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
  60                                  ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
  61                                  ALTR_I2C_ISR_TXRDY)
  62
  63 #define ALTR_I2C_THRESHOLD      0       /* IRQ Threshold at 1 element */
  64 #define ALTR_I2C_DFLT_FIFO_SZ   4
  65 #define ALTR_I2C_TIMEOUT        100000  /* 100ms */
  66 #define ALTR_I2C_XFER_TIMEOUT   (msecs_to_jiffies(250))
  67
  68 /**
  69  * altr_i2c_dev - I2C device context
  70  * @base: pointer to register struct
  71  * @msg: pointer to current message
  72  * @msg_len: number of bytes transferred in msg
  73  * @msg_err: error code for completed message
  74  * @msg_complete: xfer completion object
  75  * @dev: device reference
  76  * @adapter: core i2c abstraction
  77  * @i2c_clk: clock reference for i2c input clock
  78  * @bus_clk_rate: current i2c bus clock rate
  79  * @buf: ptr to msg buffer for easier use.
  80  * @fifo_size: size of the FIFO passed in.
  81  * @isr_mask: cached copy of local ISR enables.
  82  * @isr_status: cached copy of local ISR status.
  83  * @lock: spinlock for IRQ synchronization.
  84  */
  85 struct altr_i2c_dev {
  86         void __iomem *base;
  87         struct i2c_msg *msg;
  88         size_t msg_len;
  89         int msg_err;
  90         struct completion msg_complete;
  91         struct device *dev;
  92         struct i2c_adapter adapter;
  93         struct clk *i2c_clk;
  94         u32 bus_clk_rate;
  95         u8 *buf;
  96         u32 fifo_size;
  97         u32 isr_mask;
  98         u32 isr_status;
  99         spinlock_t lock;        /* IRQ synchronization */
 100 };
 101
 102 static void
 103 altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
 104 {
 105         unsigned long flags;
 106         u32 int_en;
 107
 108         spin_lock_irqsave(&idev->lock, flags);
 109
 110         int_en = readl(idev->base + ALTR_I2C_ISER);
 111         if (enable)
 112                 idev->isr_mask = int_en | mask;
 113         else
 114                 idev->isr_mask = int_en & ~mask;
 115
 116         writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
 117
 118         spin_unlock_irqrestore(&idev->lock, flags);
 119 }
 120
 121 static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
 122 {
 123         u32 int_en = readl(idev->base + ALTR_I2C_ISR);
 124
 125         writel(int_en | mask, idev->base + ALTR_I2C_ISR);
 126 }
 127
 128 static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
 129 {
 130         u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
 131
 132         writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
 133 }
 134
 135 static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
 136 {
 137         u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
 138
 139         writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
 140 }
 141
 142 static void altr_i2c_reset(struct altr_i2c_dev *idev)
 143 {
 144         altr_i2c_core_disable(idev);
 145         altr_i2c_core_enable(idev);
 146 }
 147
 148 static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
 149 {
 150         writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
 151 }
 152
 153 static void altr_i2c_init(struct altr_i2c_dev *idev)
 154 {
 155         u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
 156         u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
 157         u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
 158                   (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
 159         u32 t_high, t_low;
 160
 161         if (idev->bus_clk_rate <= 100000) {
 162                 tmp &= ~ALTR_I2C_CTRL_BSPEED;
 163                 /* Standard mode SCL 50/50 */
 164                 t_high = divisor * 1 / 2;
 165                 t_low = divisor * 1 / 2;
 166         } else {
 167                 tmp |= ALTR_I2C_CTRL_BSPEED;
 168                 /* Fast mode SCL 33/66 */
 169                 t_high = divisor * 1 / 3;
 170                 t_low = divisor * 2 / 3;
 171         }
 172         writel(tmp, idev->base + ALTR_I2C_CTRL);
 173
 174         dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
 175                 idev->bus_clk_rate, clk_mhz, divisor);
 176
 177         /* Reset controller */
 178         altr_i2c_reset(idev);
 179
 180         /* SCL High Time */
 181         writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
 182         /* SCL Low Time */
 183         writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
 184         /* SDA Hold Time, 300ns */
 185         writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD);
 186
 187         /* Mask all master interrupt bits */
 188         altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
 189 }
 190
 191 /**
 192  * altr_i2c_transfer - On the last byte to be transmitted, send
 193  * a Stop bit on the last byte.
 194  */
 195 static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
 196 {
 197         /* On the last byte to be transmitted, send STOP */
 198         if (idev->msg_len == 1)
 199                 data |= ALTR_I2C_TFR_CMD_STO;
 200         if (idev->msg_len > 0)
 201                 writel(data, idev->base + ALTR_I2C_TFR_CMD);
 202 }
 203
 204 /**
 205  * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
 206  * transfer. Send a Stop bit on the last byte.
 207  */
 208 static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
 209 {
 210         size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
 211         int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
 212
 213         while (bytes_to_transfer-- > 0) {
 214                 *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
 215                 idev->msg_len--;
 216                 altr_i2c_transfer(idev, 0);
 217         }
 218 }
 219
 220 /**
 221  * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
 222  * @return: Number of bytes left to transfer.
 223  */
 224 static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
 225 {
 226         size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
 227                                                        ALTR_I2C_TC_FIFO_LVL);
 228         int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
 229         int ret = idev->msg_len - bytes_to_transfer;
 230
 231         while (bytes_to_transfer-- > 0) {
 232                 altr_i2c_transfer(idev, *idev->buf++);
 233                 idev->msg_len--;
 234         }
 235
 236         return ret;
 237 }
 238
 239 static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
 240 {
 241         struct altr_i2c_dev *idev = _dev;
 242         irqreturn_t ret = IRQ_HANDLED;
 243
 244         /* Read IRQ status but only interested in Enabled IRQs. */
 245         idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
 246         if (idev->isr_status)
 247                 ret = IRQ_WAKE_THREAD;
 248
 249         return ret;
 250 }
 251
 252 static irqreturn_t altr_i2c_isr(int irq, void *_dev)
 253 {
 254         int ret;
 255         bool read, finish = false;
 256         struct altr_i2c_dev *idev = _dev;
 257         u32 status = idev->isr_status;
 258
 259         if (!idev->msg) {
 260                 dev_warn(idev->dev, "unexpected interrupt\n");
 261                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 262                 return IRQ_HANDLED;
 263         }
 264         read = (idev->msg->flags & I2C_M_RD) != 0;
 265
 266         /* handle Lost Arbitration */
 267         if (unlikely(status & ALTR_I2C_ISR_ARB)) {
 268                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
 269                 idev->msg_err = -EAGAIN;
 270                 finish = true;
 271         } else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
 272                 dev_dbg(idev->dev, "Could not get ACK\n");
 273                 idev->msg_err = -ENXIO;
 274                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
 275                 altr_i2c_stop(idev);
 276                 finish = true;
 277         } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
 278                 /* handle RX FIFO Overflow */
 279                 altr_i2c_empty_rx_fifo(idev);
 280                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
 281                 altr_i2c_stop(idev);
 282                 dev_err(idev->dev, "RX FIFO Overflow\n");
 283                 finish = true;
 284         } else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
 285                 /* RX FIFO needs service? */
 286                 altr_i2c_empty_rx_fifo(idev);
 287                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
 288                 if (!idev->msg_len)
 289                         finish = true;
 290         } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
 291                 /* TX FIFO needs service? */
 292                 altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
 293                 if (idev->msg_len > 0)
 294                         altr_i2c_fill_tx_fifo(idev);
 295                 else
 296                         finish = true;
 297         } else {
 298                 dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
 299                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 300         }
 301
 302         if (finish) {
 303                 /* Wait for the Core to finish */
 304                 ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
 305                                                 status,
 306                                                 !(status & ALTR_I2C_STAT_CORE),
 307                                                 1, ALTR_I2C_TIMEOUT);
 308                 if (ret)
 309                         dev_err(idev->dev, "message timeout\n");
 310                 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
 311                 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
 312                 complete(&idev->msg_complete);
 313                 dev_dbg(idev->dev, "Message Complete\n");
 314         }
 315
 316         return IRQ_HANDLED;
 317 }
 318
 319 static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
 320 {
 321         u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
 322         unsigned long time_left;
 323         u32 value;
 324         u8 addr = i2c_8bit_addr_from_msg(msg);
 325
 326         idev->msg = msg;
 327         idev->msg_len = msg->len;
 328         idev->buf = msg->buf;
 329         idev->msg_err = 0;
 330         reinit_completion(&idev->msg_complete);
 331         altr_i2c_core_enable(idev);
 332
 333         /* Make sure RX FIFO is empty */
 334         do {
 335                 readl(idev->base + ALTR_I2C_RX_DATA);
 336         } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
 337
 338         writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
 339
 340         if ((msg->flags & I2C_M_RD) != 0) {
 341                 imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
 342                 altr_i2c_int_enable(idev, imask, true);
 343                 /* write the first byte to start the RX */
 344                 altr_i2c_transfer(idev, 0);
 345         } else {
 346                 imask |= ALTR_I2C_ISR_TXRDY;
 347                 altr_i2c_int_enable(idev, imask, true);
 348                 altr_i2c_fill_tx_fifo(idev);
 349         }
 350
 351         time_left = wait_for_completion_timeout(&idev->msg_complete,
 352                                                 ALTR_I2C_XFER_TIMEOUT);
 353         altr_i2c_int_enable(idev, imask, false);
 354
 355         value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
 356         if (value)
 357                 dev_err(idev->dev, "Core Status not IDLE...\n");
 358
 359         if (time_left == 0) {
 360                 idev->msg_err = -ETIMEDOUT;
 361                 dev_dbg(idev->dev, "Transaction timed out.\n");
 362         }
 363
 364         altr_i2c_core_disable(idev);
 365
 366         return idev->msg_err;
 367 }
 368
 369 static int
 370 altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 371 {
 372         struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
 373         int i, ret;
 374
 375         for (i = 0; i < num; i++) {
 376                 ret = altr_i2c_xfer_msg(idev, msgs++);
 377                 if (ret)
 378                         return ret;
 379         }
 380         return num;
 381 }
 382
 383 static u32 altr_i2c_func(struct i2c_adapter *adap)
 384 {
 385         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 386 }
 387
 388 static const struct i2c_algorithm altr_i2c_algo = {
 389         .master_xfer = altr_i2c_xfer,
 390         .functionality = altr_i2c_func,
 391 };
 392
 393 static int altr_i2c_probe(struct platform_device *pdev)
 394 {
 395         struct altr_i2c_dev *idev = NULL;
 396         struct resource *res;
 397         int irq, ret;
 398         u32 val;
 399
 400         idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
 401         if (!idev)
 402                 return -ENOMEM;
 403
 404         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 405         idev->base = devm_ioremap_resource(&pdev->dev, res);
 406         if (IS_ERR(idev->base))
 407                 return PTR_ERR(idev->base);
 408
 409         irq = platform_get_irq(pdev, 0);
 410         if (irq < 0) {
 411                 dev_err(&pdev->dev, "missing interrupt resource\n");
 412                 return irq;
 413         }
 414
 415         idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
 416         if (IS_ERR(idev->i2c_clk)) {
 417                 dev_err(&pdev->dev, "missing clock\n");
 418                 return PTR_ERR(idev->i2c_clk);
 419         }
 420
 421         idev->dev = &pdev->dev;
 422         init_completion(&idev->msg_complete);
 423         spin_lock_init(&idev->lock);
 424
 425         val = device_property_read_u32(idev->dev, "fifo-size",
 426                                        &idev->fifo_size);
 427         if (val) {
 428                 dev_err(&pdev->dev, "FIFO size set to default of %d\n",
 429                         ALTR_I2C_DFLT_FIFO_SZ);
 430                 idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
 431         }
 432
 433         val = device_property_read_u32(idev->dev, "clock-frequency",
 434                                        &idev->bus_clk_rate);
 435         if (val) {
 436                 dev_err(&pdev->dev, "Default to 100kHz\n");
 437                 idev->bus_clk_rate = 100000;    /* default clock rate */
 438         }
 439
 440         if (idev->bus_clk_rate > 400000) {
 441                 dev_err(&pdev->dev, "invalid clock-frequency %d\n",
 442                         idev->bus_clk_rate);
 443                 return -EINVAL;
 444         }
 445
 446         ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
 447                                         altr_i2c_isr, IRQF_ONESHOT,
 448                                         pdev->name, idev);
 449         if (ret) {
 450                 dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
 451                 return ret;
 452         }
 453
 454         ret = clk_prepare_enable(idev->i2c_clk);
 455         if (ret) {
 456                 dev_err(&pdev->dev, "failed to enable clock\n");
 457                 return ret;
 458         }
 459
 460         altr_i2c_init(idev);
 461
 462         i2c_set_adapdata(&idev->adapter, idev);
 463         strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
 464         idev->adapter.owner = THIS_MODULE;
 465         idev->adapter.algo = &altr_i2c_algo;
 466         idev->adapter.dev.parent = &pdev->dev;
 467         idev->adapter.dev.of_node = pdev->dev.of_node;
 468
 469         platform_set_drvdata(pdev, idev);
 470
 471         ret = i2c_add_adapter(&idev->adapter);
 472         if (ret) {
 473                 clk_disable_unprepare(idev->i2c_clk);
 474                 return ret;
 475         }
 476         dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
 477
 478         return 0;
 479 }
 480
 481 static int altr_i2c_remove(struct platform_device *pdev)
 482 {
 483         struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
 484
 485         clk_disable_unprepare(idev->i2c_clk);
 486         i2c_del_adapter(&idev->adapter);
 487
 488         return 0;
 489 }
 490
 491 /* Match table for of_platform binding */
 492 static const struct of_device_id altr_i2c_of_match[] = {
 493         { .compatible = "altr,softip-i2c-v1.0" },
 494         {},
 495 };
 496 MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
 497
 498 static struct platform_driver altr_i2c_driver = {
 499         .probe = altr_i2c_probe,
 500         .remove = altr_i2c_remove,
 501         .driver = {
 502                 .name = "altera-i2c",
 503                 .of_match_table = altr_i2c_of_match,
 504         },
 505 };
 506
 507 module_platform_driver(altr_i2c_driver);
 508
 509 MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
 510 MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
 511 MODULE_LICENSE("GPL v2");