2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Braswell (SOC) 0x2292 32 hard yes yes yes
62 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
63 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
64 * DNV (SOC) 0x19df 32 hard yes yes yes
65 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
66 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
67 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
68 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
69 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
70 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
71 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
72 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
74 * Features supported by this driver:
78 * Block process call transaction no
79 * I2C block read transaction yes (doesn't use the block buffer)
81 * SMBus Host Notify yes
82 * Interrupt processing yes
84 * See the file Documentation/i2c/busses/i2c-i801 for details.
87 #include <linux/interrupt.h>
88 #include <linux/module.h>
89 #include <linux/pci.h>
90 #include <linux/kernel.h>
91 #include <linux/stddef.h>
92 #include <linux/delay.h>
93 #include <linux/ioport.h>
94 #include <linux/init.h>
95 #include <linux/i2c.h>
96 #include <linux/i2c-smbus.h>
97 #include <linux/acpi.h>
99 #include <linux/dmi.h>
100 #include <linux/slab.h>
101 #include <linux/wait.h>
102 #include <linux/err.h>
103 #include <linux/platform_device.h>
104 #include <linux/platform_data/itco_wdt.h>
105 #include <linux/pm_runtime.h>
107 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
108 #include <linux/gpio.h>
109 #include <linux/i2c-mux-gpio.h>
112 /* I801 SMBus address offsets */
113 #define SMBHSTSTS(p) (0 + (p)->smba)
114 #define SMBHSTCNT(p) (2 + (p)->smba)
115 #define SMBHSTCMD(p) (3 + (p)->smba)
116 #define SMBHSTADD(p) (4 + (p)->smba)
117 #define SMBHSTDAT0(p) (5 + (p)->smba)
118 #define SMBHSTDAT1(p) (6 + (p)->smba)
119 #define SMBBLKDAT(p) (7 + (p)->smba)
120 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
121 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
122 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
123 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
124 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
125 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
127 /* PCI Address Constants */
129 #define SMBPCICTL 0x004
130 #define SMBPCISTS 0x006
131 #define SMBHSTCFG 0x040
132 #define TCOBASE 0x050
135 #define ACPIBASE 0x040
136 #define ACPIBASE_SMI_OFF 0x030
137 #define ACPICTRL 0x044
138 #define ACPICTRL_EN 0x080
140 #define SBREG_BAR 0x10
141 #define SBREG_SMBCTRL 0xc6000c
143 /* Host status bits for SMBPCISTS */
144 #define SMBPCISTS_INTS BIT(3)
146 /* Control bits for SMBPCICTL */
147 #define SMBPCICTL_INTDIS BIT(10)
149 /* Host configuration bits for SMBHSTCFG */
150 #define SMBHSTCFG_HST_EN BIT(0)
151 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
152 #define SMBHSTCFG_I2C_EN BIT(2)
153 #define SMBHSTCFG_SPD_WD BIT(4)
155 /* TCO configuration bits for TCOCTL */
156 #define TCOCTL_EN BIT(8)
158 /* Auxiliary status register bits, ICH4+ only */
159 #define SMBAUXSTS_CRCE BIT(0)
160 #define SMBAUXSTS_STCO BIT(1)
162 /* Auxiliary control register bits, ICH4+ only */
163 #define SMBAUXCTL_CRC BIT(0)
164 #define SMBAUXCTL_E32B BIT(1)
167 #define MAX_RETRIES 400
169 /* I801 command constants */
170 #define I801_QUICK 0x00
171 #define I801_BYTE 0x04
172 #define I801_BYTE_DATA 0x08
173 #define I801_WORD_DATA 0x0C
174 #define I801_PROC_CALL 0x10 /* unimplemented */
175 #define I801_BLOCK_DATA 0x14
176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
178 /* I801 Host Control register bits */
179 #define SMBHSTCNT_INTREN BIT(0)
180 #define SMBHSTCNT_KILL BIT(1)
181 #define SMBHSTCNT_LAST_BYTE BIT(5)
182 #define SMBHSTCNT_START BIT(6)
183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
185 /* I801 Hosts Status register bits */
186 #define SMBHSTSTS_BYTE_DONE BIT(7)
187 #define SMBHSTSTS_INUSE_STS BIT(6)
188 #define SMBHSTSTS_SMBALERT_STS BIT(5)
189 #define SMBHSTSTS_FAILED BIT(4)
190 #define SMBHSTSTS_BUS_ERR BIT(3)
191 #define SMBHSTSTS_DEV_ERR BIT(2)
192 #define SMBHSTSTS_INTR BIT(1)
193 #define SMBHSTSTS_HOST_BUSY BIT(0)
195 /* Host Notify Status register bits */
196 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
198 /* Host Notify Command register bits */
199 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
201 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
204 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
207 /* Older devices have their ID defined in <linux/pci_ids.h> */
208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
224 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
228 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
233 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
234 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
236 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
237 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
238 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
239 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
241 struct i801_mux_config
{
246 unsigned gpios
[2]; /* Relative to gpio_chip->base */
251 struct i2c_adapter adapter
;
253 unsigned char original_hstcfg
;
254 unsigned char original_slvcmd
;
255 struct pci_dev
*pci_dev
;
256 unsigned int features
;
259 wait_queue_head_t waitq
;
262 /* Command state used by isr for byte-by-byte block transactions */
269 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
270 const struct i801_mux_config
*mux_drvdata
;
271 struct platform_device
*mux_pdev
;
273 struct platform_device
*tco_pdev
;
276 * If set to true the host controller registers are reserved for
277 * ACPI AML use. Protected by acpi_lock.
280 struct mutex acpi_lock
;
283 #define FEATURE_SMBUS_PEC BIT(0)
284 #define FEATURE_BLOCK_BUFFER BIT(1)
285 #define FEATURE_BLOCK_PROC BIT(2)
286 #define FEATURE_I2C_BLOCK_READ BIT(3)
287 #define FEATURE_IRQ BIT(4)
288 #define FEATURE_HOST_NOTIFY BIT(5)
289 /* Not really a feature, but it's convenient to handle it as such */
290 #define FEATURE_IDF BIT(15)
291 #define FEATURE_TCO BIT(16)
293 static const char *i801_feature_names
[] = {
296 "Block process call",
302 static unsigned int disable_features
;
303 module_param(disable_features
, uint
, S_IRUGO
| S_IWUSR
);
304 MODULE_PARM_DESC(disable_features
, "Disable selected driver features:\n"
305 "\t\t 0x01 disable SMBus PEC\n"
306 "\t\t 0x02 disable the block buffer\n"
307 "\t\t 0x08 disable the I2C block read functionality\n"
308 "\t\t 0x10 don't use interrupts\n"
309 "\t\t 0x20 disable SMBus Host Notify ");
311 /* Make sure the SMBus host is ready to start transmitting.
312 Return 0 if it is, -EBUSY if it is not. */
313 static int i801_check_pre(struct i801_priv
*priv
)
317 status
= inb_p(SMBHSTSTS(priv
));
318 if (status
& SMBHSTSTS_HOST_BUSY
) {
319 dev_err(&priv
->pci_dev
->dev
, "SMBus is busy, can't use it!\n");
323 status
&= STATUS_FLAGS
;
325 dev_dbg(&priv
->pci_dev
->dev
, "Clearing status flags (%02x)\n",
327 outb_p(status
, SMBHSTSTS(priv
));
328 status
= inb_p(SMBHSTSTS(priv
)) & STATUS_FLAGS
;
330 dev_err(&priv
->pci_dev
->dev
,
331 "Failed clearing status flags (%02x)\n",
338 * Clear CRC status if needed.
339 * During normal operation, i801_check_post() takes care
340 * of it after every operation. We do it here only in case
341 * the hardware was already in this state when the driver
344 if (priv
->features
& FEATURE_SMBUS_PEC
) {
345 status
= inb_p(SMBAUXSTS(priv
)) & SMBAUXSTS_CRCE
;
347 dev_dbg(&priv
->pci_dev
->dev
,
348 "Clearing aux status flags (%02x)\n", status
);
349 outb_p(status
, SMBAUXSTS(priv
));
350 status
= inb_p(SMBAUXSTS(priv
)) & SMBAUXSTS_CRCE
;
352 dev_err(&priv
->pci_dev
->dev
,
353 "Failed clearing aux status flags (%02x)\n",
364 * Convert the status register to an error code, and clear it.
365 * Note that status only contains the bits we want to clear, not the
366 * actual register value.
368 static int i801_check_post(struct i801_priv
*priv
, int status
)
373 * If the SMBus is still busy, we give up
374 * Note: This timeout condition only happens when using polling
375 * transactions. For interrupt operation, NAK/timeout is indicated by
378 if (unlikely(status
< 0)) {
379 dev_err(&priv
->pci_dev
->dev
, "Transaction timeout\n");
380 /* try to stop the current command */
381 dev_dbg(&priv
->pci_dev
->dev
, "Terminating the current operation\n");
382 outb_p(inb_p(SMBHSTCNT(priv
)) | SMBHSTCNT_KILL
,
384 usleep_range(1000, 2000);
385 outb_p(inb_p(SMBHSTCNT(priv
)) & (~SMBHSTCNT_KILL
),
388 /* Check if it worked */
389 status
= inb_p(SMBHSTSTS(priv
));
390 if ((status
& SMBHSTSTS_HOST_BUSY
) ||
391 !(status
& SMBHSTSTS_FAILED
))
392 dev_err(&priv
->pci_dev
->dev
,
393 "Failed terminating the transaction\n");
394 outb_p(STATUS_FLAGS
, SMBHSTSTS(priv
));
398 if (status
& SMBHSTSTS_FAILED
) {
400 dev_err(&priv
->pci_dev
->dev
, "Transaction failed\n");
402 if (status
& SMBHSTSTS_DEV_ERR
) {
404 * This may be a PEC error, check and clear it.
406 * AUXSTS is handled differently from HSTSTS.
407 * For HSTSTS, i801_isr() or i801_wait_intr()
408 * has already cleared the error bits in hardware,
409 * and we are passed a copy of the original value
411 * For AUXSTS, the hardware register is left
412 * for us to handle here.
413 * This is asymmetric, slightly iffy, but safe,
414 * since all this code is serialized and the CRCE
415 * bit is harmless as long as it's cleared before
416 * the next operation.
418 if ((priv
->features
& FEATURE_SMBUS_PEC
) &&
419 (inb_p(SMBAUXSTS(priv
)) & SMBAUXSTS_CRCE
)) {
420 outb_p(SMBAUXSTS_CRCE
, SMBAUXSTS(priv
));
422 dev_dbg(&priv
->pci_dev
->dev
, "PEC error\n");
425 dev_dbg(&priv
->pci_dev
->dev
, "No response\n");
428 if (status
& SMBHSTSTS_BUS_ERR
) {
430 dev_dbg(&priv
->pci_dev
->dev
, "Lost arbitration\n");
433 /* Clear status flags except BYTE_DONE, to be cleared by caller */
434 outb_p(status
, SMBHSTSTS(priv
));
439 /* Wait for BUSY being cleared and either INTR or an error flag being set */
440 static int i801_wait_intr(struct i801_priv
*priv
)
445 /* We will always wait for a fraction of a second! */
447 usleep_range(250, 500);
448 status
= inb_p(SMBHSTSTS(priv
));
449 } while (((status
& SMBHSTSTS_HOST_BUSY
) ||
450 !(status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_INTR
))) &&
451 (timeout
++ < MAX_RETRIES
));
453 if (timeout
> MAX_RETRIES
) {
454 dev_dbg(&priv
->pci_dev
->dev
, "INTR Timeout!\n");
457 return status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_INTR
);
460 /* Wait for either BYTE_DONE or an error flag being set */
461 static int i801_wait_byte_done(struct i801_priv
*priv
)
466 /* We will always wait for a fraction of a second! */
468 usleep_range(250, 500);
469 status
= inb_p(SMBHSTSTS(priv
));
470 } while (!(status
& (STATUS_ERROR_FLAGS
| SMBHSTSTS_BYTE_DONE
)) &&
471 (timeout
++ < MAX_RETRIES
));
473 if (timeout
> MAX_RETRIES
) {
474 dev_dbg(&priv
->pci_dev
->dev
, "BYTE_DONE Timeout!\n");
477 return status
& STATUS_ERROR_FLAGS
;
480 static int i801_transaction(struct i801_priv
*priv
, int xact
)
484 const struct i2c_adapter
*adap
= &priv
->adapter
;
486 result
= i801_check_pre(priv
);
490 if (priv
->features
& FEATURE_IRQ
) {
491 outb_p(xact
| SMBHSTCNT_INTREN
| SMBHSTCNT_START
,
493 result
= wait_event_timeout(priv
->waitq
,
494 (status
= priv
->status
),
498 dev_warn(&priv
->pci_dev
->dev
,
499 "Timeout waiting for interrupt!\n");
502 return i801_check_post(priv
, status
);
505 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
506 * SMBSCMD are passed in xact */
507 outb_p(xact
| SMBHSTCNT_START
, SMBHSTCNT(priv
));
509 status
= i801_wait_intr(priv
);
510 return i801_check_post(priv
, status
);
513 static int i801_block_transaction_by_block(struct i801_priv
*priv
,
514 union i2c_smbus_data
*data
,
515 char read_write
, int hwpec
)
520 inb_p(SMBHSTCNT(priv
)); /* reset the data buffer index */
522 /* Use 32-byte buffer to process this transaction */
523 if (read_write
== I2C_SMBUS_WRITE
) {
524 len
= data
->block
[0];
525 outb_p(len
, SMBHSTDAT0(priv
));
526 for (i
= 0; i
< len
; i
++)
527 outb_p(data
->block
[i
+1], SMBBLKDAT(priv
));
530 status
= i801_transaction(priv
, I801_BLOCK_DATA
|
531 (hwpec
? SMBHSTCNT_PEC_EN
: 0));
535 if (read_write
== I2C_SMBUS_READ
) {
536 len
= inb_p(SMBHSTDAT0(priv
));
537 if (len
< 1 || len
> I2C_SMBUS_BLOCK_MAX
)
540 data
->block
[0] = len
;
541 for (i
= 0; i
< len
; i
++)
542 data
->block
[i
+ 1] = inb_p(SMBBLKDAT(priv
));
547 static void i801_isr_byte_done(struct i801_priv
*priv
)
550 /* For SMBus block reads, length is received with first byte */
551 if (((priv
->cmd
& 0x1c) == I801_BLOCK_DATA
) &&
552 (priv
->count
== 0)) {
553 priv
->len
= inb_p(SMBHSTDAT0(priv
));
554 if (priv
->len
< 1 || priv
->len
> I2C_SMBUS_BLOCK_MAX
) {
555 dev_err(&priv
->pci_dev
->dev
,
556 "Illegal SMBus block read size %d\n",
559 priv
->len
= I2C_SMBUS_BLOCK_MAX
;
561 dev_dbg(&priv
->pci_dev
->dev
,
562 "SMBus block read size is %d\n",
565 priv
->data
[-1] = priv
->len
;
569 if (priv
->count
< priv
->len
)
570 priv
->data
[priv
->count
++] = inb(SMBBLKDAT(priv
));
572 dev_dbg(&priv
->pci_dev
->dev
,
573 "Discarding extra byte on block read\n");
575 /* Set LAST_BYTE for last byte of read transaction */
576 if (priv
->count
== priv
->len
- 1)
577 outb_p(priv
->cmd
| SMBHSTCNT_LAST_BYTE
,
579 } else if (priv
->count
< priv
->len
- 1) {
580 /* Write next byte, except for IRQ after last byte */
581 outb_p(priv
->data
[++priv
->count
], SMBBLKDAT(priv
));
584 /* Clear BYTE_DONE to continue with next byte */
585 outb_p(SMBHSTSTS_BYTE_DONE
, SMBHSTSTS(priv
));
588 static irqreturn_t
i801_host_notify_isr(struct i801_priv
*priv
)
592 addr
= inb_p(SMBNTFDADD(priv
)) >> 1;
595 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
596 * always returns 0. Our current implementation doesn't provide
597 * data, so we just ignore it.
599 i2c_handle_smbus_host_notify(&priv
->adapter
, addr
);
601 /* clear Host Notify bit and return */
602 outb_p(SMBSLVSTS_HST_NTFY_STS
, SMBSLVSTS(priv
));
607 * There are three kinds of interrupts:
609 * 1) i801 signals transaction completion with one of these interrupts:
611 * DEV_ERR - Invalid command, NAK or communication timeout
612 * BUS_ERR - SMI# transaction collision
613 * FAILED - transaction was canceled due to a KILL request
614 * When any of these occur, update ->status and wake up the waitq.
615 * ->status must be cleared before kicking off the next transaction.
617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
618 * occurs for each byte of a byte-by-byte to prepare the next byte.
620 * 3) Host Notify interrupts
622 static irqreturn_t
i801_isr(int irq
, void *dev_id
)
624 struct i801_priv
*priv
= dev_id
;
628 /* Confirm this is our interrupt */
629 pci_read_config_word(priv
->pci_dev
, SMBPCISTS
, &pcists
);
630 if (!(pcists
& SMBPCISTS_INTS
))
633 if (priv
->features
& FEATURE_HOST_NOTIFY
) {
634 status
= inb_p(SMBSLVSTS(priv
));
635 if (status
& SMBSLVSTS_HST_NTFY_STS
)
636 return i801_host_notify_isr(priv
);
639 status
= inb_p(SMBHSTSTS(priv
));
640 if (status
& SMBHSTSTS_BYTE_DONE
)
641 i801_isr_byte_done(priv
);
644 * Clear irq sources and report transaction result.
645 * ->status must be cleared before the next transaction is started.
647 status
&= SMBHSTSTS_INTR
| STATUS_ERROR_FLAGS
;
649 outb_p(status
, SMBHSTSTS(priv
));
650 priv
->status
= status
;
651 wake_up(&priv
->waitq
);
658 * For "byte-by-byte" block transactions:
659 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
660 * I2C read uses cmd=I801_I2C_BLOCK_DATA
662 static int i801_block_transaction_byte_by_byte(struct i801_priv
*priv
,
663 union i2c_smbus_data
*data
,
664 char read_write
, int command
,
671 const struct i2c_adapter
*adap
= &priv
->adapter
;
673 result
= i801_check_pre(priv
);
677 len
= data
->block
[0];
679 if (read_write
== I2C_SMBUS_WRITE
) {
680 outb_p(len
, SMBHSTDAT0(priv
));
681 outb_p(data
->block
[1], SMBBLKDAT(priv
));
684 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
&&
685 read_write
== I2C_SMBUS_READ
)
686 smbcmd
= I801_I2C_BLOCK_DATA
;
688 smbcmd
= I801_BLOCK_DATA
;
690 if (priv
->features
& FEATURE_IRQ
) {
691 priv
->is_read
= (read_write
== I2C_SMBUS_READ
);
692 if (len
== 1 && priv
->is_read
)
693 smbcmd
|= SMBHSTCNT_LAST_BYTE
;
694 priv
->cmd
= smbcmd
| SMBHSTCNT_INTREN
;
697 priv
->data
= &data
->block
[1];
699 outb_p(priv
->cmd
| SMBHSTCNT_START
, SMBHSTCNT(priv
));
700 result
= wait_event_timeout(priv
->waitq
,
701 (status
= priv
->status
),
705 dev_warn(&priv
->pci_dev
->dev
,
706 "Timeout waiting for interrupt!\n");
709 return i801_check_post(priv
, status
);
712 for (i
= 1; i
<= len
; i
++) {
713 if (i
== len
&& read_write
== I2C_SMBUS_READ
)
714 smbcmd
|= SMBHSTCNT_LAST_BYTE
;
715 outb_p(smbcmd
, SMBHSTCNT(priv
));
718 outb_p(inb(SMBHSTCNT(priv
)) | SMBHSTCNT_START
,
721 status
= i801_wait_byte_done(priv
);
725 if (i
== 1 && read_write
== I2C_SMBUS_READ
726 && command
!= I2C_SMBUS_I2C_BLOCK_DATA
) {
727 len
= inb_p(SMBHSTDAT0(priv
));
728 if (len
< 1 || len
> I2C_SMBUS_BLOCK_MAX
) {
729 dev_err(&priv
->pci_dev
->dev
,
730 "Illegal SMBus block read size %d\n",
733 while (inb_p(SMBHSTSTS(priv
)) &
735 outb_p(SMBHSTSTS_BYTE_DONE
,
737 outb_p(SMBHSTSTS_INTR
, SMBHSTSTS(priv
));
740 data
->block
[0] = len
;
743 /* Retrieve/store value in SMBBLKDAT */
744 if (read_write
== I2C_SMBUS_READ
)
745 data
->block
[i
] = inb_p(SMBBLKDAT(priv
));
746 if (read_write
== I2C_SMBUS_WRITE
&& i
+1 <= len
)
747 outb_p(data
->block
[i
+1], SMBBLKDAT(priv
));
749 /* signals SMBBLKDAT ready */
750 outb_p(SMBHSTSTS_BYTE_DONE
, SMBHSTSTS(priv
));
753 status
= i801_wait_intr(priv
);
755 return i801_check_post(priv
, status
);
758 static int i801_set_block_buffer_mode(struct i801_priv
*priv
)
760 outb_p(inb_p(SMBAUXCTL(priv
)) | SMBAUXCTL_E32B
, SMBAUXCTL(priv
));
761 if ((inb_p(SMBAUXCTL(priv
)) & SMBAUXCTL_E32B
) == 0)
766 /* Block transaction function */
767 static int i801_block_transaction(struct i801_priv
*priv
,
768 union i2c_smbus_data
*data
, char read_write
,
769 int command
, int hwpec
)
774 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
) {
775 if (read_write
== I2C_SMBUS_WRITE
) {
776 /* set I2C_EN bit in configuration register */
777 pci_read_config_byte(priv
->pci_dev
, SMBHSTCFG
, &hostc
);
778 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
,
779 hostc
| SMBHSTCFG_I2C_EN
);
780 } else if (!(priv
->features
& FEATURE_I2C_BLOCK_READ
)) {
781 dev_err(&priv
->pci_dev
->dev
,
782 "I2C block read is unsupported!\n");
787 if (read_write
== I2C_SMBUS_WRITE
788 || command
== I2C_SMBUS_I2C_BLOCK_DATA
) {
789 if (data
->block
[0] < 1)
791 if (data
->block
[0] > I2C_SMBUS_BLOCK_MAX
)
792 data
->block
[0] = I2C_SMBUS_BLOCK_MAX
;
794 data
->block
[0] = 32; /* max for SMBus block reads */
797 /* Experience has shown that the block buffer can only be used for
798 SMBus (not I2C) block transactions, even though the datasheet
799 doesn't mention this limitation. */
800 if ((priv
->features
& FEATURE_BLOCK_BUFFER
)
801 && command
!= I2C_SMBUS_I2C_BLOCK_DATA
802 && i801_set_block_buffer_mode(priv
) == 0)
803 result
= i801_block_transaction_by_block(priv
, data
,
806 result
= i801_block_transaction_byte_by_byte(priv
, data
,
810 if (command
== I2C_SMBUS_I2C_BLOCK_DATA
811 && read_write
== I2C_SMBUS_WRITE
) {
812 /* restore saved configuration register value */
813 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
, hostc
);
818 /* Return negative errno on error. */
819 static s32
i801_access(struct i2c_adapter
*adap
, u16 addr
,
820 unsigned short flags
, char read_write
, u8 command
,
821 int size
, union i2c_smbus_data
*data
)
825 int ret
= 0, xact
= 0;
826 struct i801_priv
*priv
= i2c_get_adapdata(adap
);
828 mutex_lock(&priv
->acpi_lock
);
829 if (priv
->acpi_reserved
) {
830 mutex_unlock(&priv
->acpi_lock
);
834 pm_runtime_get_sync(&priv
->pci_dev
->dev
);
836 hwpec
= (priv
->features
& FEATURE_SMBUS_PEC
) && (flags
& I2C_CLIENT_PEC
)
837 && size
!= I2C_SMBUS_QUICK
838 && size
!= I2C_SMBUS_I2C_BLOCK_DATA
;
841 case I2C_SMBUS_QUICK
:
842 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
847 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
849 if (read_write
== I2C_SMBUS_WRITE
)
850 outb_p(command
, SMBHSTCMD(priv
));
853 case I2C_SMBUS_BYTE_DATA
:
854 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
856 outb_p(command
, SMBHSTCMD(priv
));
857 if (read_write
== I2C_SMBUS_WRITE
)
858 outb_p(data
->byte
, SMBHSTDAT0(priv
));
859 xact
= I801_BYTE_DATA
;
861 case I2C_SMBUS_WORD_DATA
:
862 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
864 outb_p(command
, SMBHSTCMD(priv
));
865 if (read_write
== I2C_SMBUS_WRITE
) {
866 outb_p(data
->word
& 0xff, SMBHSTDAT0(priv
));
867 outb_p((data
->word
& 0xff00) >> 8, SMBHSTDAT1(priv
));
869 xact
= I801_WORD_DATA
;
871 case I2C_SMBUS_BLOCK_DATA
:
872 outb_p(((addr
& 0x7f) << 1) | (read_write
& 0x01),
874 outb_p(command
, SMBHSTCMD(priv
));
877 case I2C_SMBUS_I2C_BLOCK_DATA
:
879 * NB: page 240 of ICH5 datasheet shows that the R/#W
880 * bit should be cleared here, even when reading.
881 * However if SPD Write Disable is set (Lynx Point and later),
882 * the read will fail if we don't set the R/#W bit.
884 outb_p(((addr
& 0x7f) << 1) |
885 ((priv
->original_hstcfg
& SMBHSTCFG_SPD_WD
) ?
886 (read_write
& 0x01) : 0),
888 if (read_write
== I2C_SMBUS_READ
) {
889 /* NB: page 240 of ICH5 datasheet also shows
890 * that DATA1 is the cmd field when reading */
891 outb_p(command
, SMBHSTDAT1(priv
));
893 outb_p(command
, SMBHSTCMD(priv
));
897 dev_err(&priv
->pci_dev
->dev
, "Unsupported transaction %d\n",
903 if (hwpec
) /* enable/disable hardware PEC */
904 outb_p(inb_p(SMBAUXCTL(priv
)) | SMBAUXCTL_CRC
, SMBAUXCTL(priv
));
906 outb_p(inb_p(SMBAUXCTL(priv
)) & (~SMBAUXCTL_CRC
),
910 ret
= i801_block_transaction(priv
, data
, read_write
, size
,
913 ret
= i801_transaction(priv
, xact
);
915 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
916 time, so we forcibly disable it after every transaction. Turn off
917 E32B for the same reason. */
919 outb_p(inb_p(SMBAUXCTL(priv
)) &
920 ~(SMBAUXCTL_CRC
| SMBAUXCTL_E32B
), SMBAUXCTL(priv
));
926 if ((read_write
== I2C_SMBUS_WRITE
) || (xact
== I801_QUICK
))
929 switch (xact
& 0x7f) {
930 case I801_BYTE
: /* Result put in SMBHSTDAT0 */
932 data
->byte
= inb_p(SMBHSTDAT0(priv
));
935 data
->word
= inb_p(SMBHSTDAT0(priv
)) +
936 (inb_p(SMBHSTDAT1(priv
)) << 8);
941 pm_runtime_mark_last_busy(&priv
->pci_dev
->dev
);
942 pm_runtime_put_autosuspend(&priv
->pci_dev
->dev
);
943 mutex_unlock(&priv
->acpi_lock
);
948 static u32
i801_func(struct i2c_adapter
*adapter
)
950 struct i801_priv
*priv
= i2c_get_adapdata(adapter
);
952 return I2C_FUNC_SMBUS_QUICK
| I2C_FUNC_SMBUS_BYTE
|
953 I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
|
954 I2C_FUNC_SMBUS_BLOCK_DATA
| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
|
955 ((priv
->features
& FEATURE_SMBUS_PEC
) ? I2C_FUNC_SMBUS_PEC
: 0) |
956 ((priv
->features
& FEATURE_I2C_BLOCK_READ
) ?
957 I2C_FUNC_SMBUS_READ_I2C_BLOCK
: 0) |
958 ((priv
->features
& FEATURE_HOST_NOTIFY
) ?
959 I2C_FUNC_SMBUS_HOST_NOTIFY
: 0);
962 static void i801_enable_host_notify(struct i2c_adapter
*adapter
)
964 struct i801_priv
*priv
= i2c_get_adapdata(adapter
);
966 if (!(priv
->features
& FEATURE_HOST_NOTIFY
))
969 priv
->original_slvcmd
= inb_p(SMBSLVCMD(priv
));
971 if (!(SMBSLVCMD_HST_NTFY_INTREN
& priv
->original_slvcmd
))
972 outb_p(SMBSLVCMD_HST_NTFY_INTREN
| priv
->original_slvcmd
,
975 /* clear Host Notify bit to allow a new notification */
976 outb_p(SMBSLVSTS_HST_NTFY_STS
, SMBSLVSTS(priv
));
979 static void i801_disable_host_notify(struct i801_priv
*priv
)
981 if (!(priv
->features
& FEATURE_HOST_NOTIFY
))
984 outb_p(priv
->original_slvcmd
, SMBSLVCMD(priv
));
987 static const struct i2c_algorithm smbus_algorithm
= {
988 .smbus_xfer
= i801_access
,
989 .functionality
= i801_func
,
992 static const struct pci_device_id i801_ids
[] = {
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_3
) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_3
) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_2
) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_3
) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_3
) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_3
) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_4
) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_16
) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_17
) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_17
) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_5
) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_6
) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EP80579_1
) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_4
) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_5
) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS
) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS
) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS
) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0
) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1
) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2
) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS
) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS
) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS
) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS
) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS
) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS
) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0
) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1
) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2
) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS
) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS
) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS
) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS
) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS
) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS
) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS
) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS
) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CDF_SMBUS
) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_DNV_SMBUS
) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS
) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS
) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS
) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS
) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS
) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS
) },
1042 MODULE_DEVICE_TABLE(pci
, i801_ids
);
1044 #if defined CONFIG_X86 && defined CONFIG_DMI
1045 static unsigned char apanel_addr
;
1047 /* Scan the system ROM for the signature "FJKEYINF" */
1048 static __init
const void __iomem
*bios_signature(const void __iomem
*bios
)
1051 const unsigned char signature
[] = "FJKEYINF";
1053 for (offset
= 0; offset
< 0x10000; offset
+= 0x10) {
1054 if (check_signature(bios
+ offset
, signature
,
1055 sizeof(signature
)-1))
1056 return bios
+ offset
;
1061 static void __init
input_apanel_init(void)
1064 const void __iomem
*p
;
1066 bios
= ioremap(0xF0000, 0x10000); /* Can't fail */
1067 p
= bios_signature(bios
);
1069 /* just use the first address */
1070 apanel_addr
= readb(p
+ 8 + 3) >> 1;
1075 struct dmi_onboard_device_info
{
1078 unsigned short i2c_addr
;
1079 const char *i2c_type
;
1082 static const struct dmi_onboard_device_info dmi_devices
[] = {
1083 { "Syleus", DMI_DEV_TYPE_OTHER
, 0x73, "fscsyl" },
1084 { "Hermes", DMI_DEV_TYPE_OTHER
, 0x73, "fscher" },
1085 { "Hades", DMI_DEV_TYPE_OTHER
, 0x73, "fschds" },
1088 static void dmi_check_onboard_device(u8 type
, const char *name
,
1089 struct i2c_adapter
*adap
)
1092 struct i2c_board_info info
;
1094 for (i
= 0; i
< ARRAY_SIZE(dmi_devices
); i
++) {
1095 /* & ~0x80, ignore enabled/disabled bit */
1096 if ((type
& ~0x80) != dmi_devices
[i
].type
)
1098 if (strcasecmp(name
, dmi_devices
[i
].name
))
1101 memset(&info
, 0, sizeof(struct i2c_board_info
));
1102 info
.addr
= dmi_devices
[i
].i2c_addr
;
1103 strlcpy(info
.type
, dmi_devices
[i
].i2c_type
, I2C_NAME_SIZE
);
1104 i2c_new_device(adap
, &info
);
1109 /* We use our own function to check for onboard devices instead of
1110 dmi_find_device() as some buggy BIOS's have the devices we are interested
1111 in marked as disabled */
1112 static void dmi_check_onboard_devices(const struct dmi_header
*dm
, void *adap
)
1119 count
= (dm
->length
- sizeof(struct dmi_header
)) / 2;
1120 for (i
= 0; i
< count
; i
++) {
1121 const u8
*d
= (char *)(dm
+ 1) + (i
* 2);
1122 const char *name
= ((char *) dm
) + dm
->length
;
1129 while (s
> 0 && name
[0]) {
1130 name
+= strlen(name
) + 1;
1133 if (name
[0] == 0) /* Bogus string reference */
1136 dmi_check_onboard_device(type
, name
, adap
);
1140 /* Register optional slaves */
1141 static void i801_probe_optional_slaves(struct i801_priv
*priv
)
1143 /* Only register slaves on main SMBus channel */
1144 if (priv
->features
& FEATURE_IDF
)
1148 struct i2c_board_info info
;
1150 memset(&info
, 0, sizeof(struct i2c_board_info
));
1151 info
.addr
= apanel_addr
;
1152 strlcpy(info
.type
, "fujitsu_apanel", I2C_NAME_SIZE
);
1153 i2c_new_device(&priv
->adapter
, &info
);
1156 if (dmi_name_in_vendors("FUJITSU"))
1157 dmi_walk(dmi_check_onboard_devices
, &priv
->adapter
);
1160 static void __init
input_apanel_init(void) {}
1161 static void i801_probe_optional_slaves(struct i801_priv
*priv
) {}
1162 #endif /* CONFIG_X86 && CONFIG_DMI */
1164 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1165 static struct i801_mux_config i801_mux_config_asus_z8_d12
= {
1166 .gpio_chip
= "gpio_ich",
1167 .values
= { 0x02, 0x03 },
1169 .classes
= { I2C_CLASS_SPD
, I2C_CLASS_SPD
},
1170 .gpios
= { 52, 53 },
1174 static struct i801_mux_config i801_mux_config_asus_z8_d18
= {
1175 .gpio_chip
= "gpio_ich",
1176 .values
= { 0x02, 0x03, 0x01 },
1178 .classes
= { I2C_CLASS_SPD
, I2C_CLASS_SPD
, I2C_CLASS_SPD
},
1179 .gpios
= { 52, 53 },
1183 static const struct dmi_system_id mux_dmi_table
[] = {
1186 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1187 DMI_MATCH(DMI_BOARD_NAME
, "Z8NA-D6(C)"),
1189 .driver_data
= &i801_mux_config_asus_z8_d12
,
1193 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1194 DMI_MATCH(DMI_BOARD_NAME
, "Z8P(N)E-D12(X)"),
1196 .driver_data
= &i801_mux_config_asus_z8_d12
,
1200 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1201 DMI_MATCH(DMI_BOARD_NAME
, "Z8NH-D12"),
1203 .driver_data
= &i801_mux_config_asus_z8_d12
,
1207 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1208 DMI_MATCH(DMI_BOARD_NAME
, "Z8PH-D12/IFB"),
1210 .driver_data
= &i801_mux_config_asus_z8_d12
,
1214 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1215 DMI_MATCH(DMI_BOARD_NAME
, "Z8NR-D12"),
1217 .driver_data
= &i801_mux_config_asus_z8_d12
,
1221 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1222 DMI_MATCH(DMI_BOARD_NAME
, "Z8P(N)H-D12"),
1224 .driver_data
= &i801_mux_config_asus_z8_d12
,
1228 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1229 DMI_MATCH(DMI_BOARD_NAME
, "Z8PG-D18"),
1231 .driver_data
= &i801_mux_config_asus_z8_d18
,
1235 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1236 DMI_MATCH(DMI_BOARD_NAME
, "Z8PE-D18"),
1238 .driver_data
= &i801_mux_config_asus_z8_d18
,
1242 DMI_MATCH(DMI_BOARD_VENDOR
, "ASUSTeK Computer INC."),
1243 DMI_MATCH(DMI_BOARD_NAME
, "Z8PS-D12"),
1245 .driver_data
= &i801_mux_config_asus_z8_d12
,
1250 /* Setup multiplexing if needed */
1251 static int i801_add_mux(struct i801_priv
*priv
)
1253 struct device
*dev
= &priv
->adapter
.dev
;
1254 const struct i801_mux_config
*mux_config
;
1255 struct i2c_mux_gpio_platform_data gpio_data
;
1258 if (!priv
->mux_drvdata
)
1260 mux_config
= priv
->mux_drvdata
;
1262 /* Prepare the platform data */
1263 memset(&gpio_data
, 0, sizeof(struct i2c_mux_gpio_platform_data
));
1264 gpio_data
.parent
= priv
->adapter
.nr
;
1265 gpio_data
.values
= mux_config
->values
;
1266 gpio_data
.n_values
= mux_config
->n_values
;
1267 gpio_data
.classes
= mux_config
->classes
;
1268 gpio_data
.gpio_chip
= mux_config
->gpio_chip
;
1269 gpio_data
.gpios
= mux_config
->gpios
;
1270 gpio_data
.n_gpios
= mux_config
->n_gpios
;
1271 gpio_data
.idle
= I2C_MUX_GPIO_NO_IDLE
;
1273 /* Register the mux device */
1274 priv
->mux_pdev
= platform_device_register_data(dev
, "i2c-mux-gpio",
1275 PLATFORM_DEVID_AUTO
, &gpio_data
,
1276 sizeof(struct i2c_mux_gpio_platform_data
));
1277 if (IS_ERR(priv
->mux_pdev
)) {
1278 err
= PTR_ERR(priv
->mux_pdev
);
1279 priv
->mux_pdev
= NULL
;
1280 dev_err(dev
, "Failed to register i2c-mux-gpio device\n");
1287 static void i801_del_mux(struct i801_priv
*priv
)
1290 platform_device_unregister(priv
->mux_pdev
);
1293 static unsigned int i801_get_adapter_class(struct i801_priv
*priv
)
1295 const struct dmi_system_id
*id
;
1296 const struct i801_mux_config
*mux_config
;
1297 unsigned int class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
1300 id
= dmi_first_match(mux_dmi_table
);
1302 /* Remove branch classes from trunk */
1303 mux_config
= id
->driver_data
;
1304 for (i
= 0; i
< mux_config
->n_values
; i
++)
1305 class &= ~mux_config
->classes
[i
];
1307 /* Remember for later */
1308 priv
->mux_drvdata
= mux_config
;
1314 static inline int i801_add_mux(struct i801_priv
*priv
) { return 0; }
1315 static inline void i801_del_mux(struct i801_priv
*priv
) { }
1317 static inline unsigned int i801_get_adapter_class(struct i801_priv
*priv
)
1319 return I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
1323 static const struct itco_wdt_platform_data tco_platform_data
= {
1324 .name
= "Intel PCH",
1328 static DEFINE_SPINLOCK(p2sb_spinlock
);
1330 static void i801_add_tco(struct i801_priv
*priv
)
1332 struct pci_dev
*pci_dev
= priv
->pci_dev
;
1333 struct resource tco_res
[3], *res
;
1334 struct platform_device
*pdev
;
1336 u32 tco_base
, tco_ctl
;
1337 u32 base_addr
, ctrl_val
;
1341 if (!(priv
->features
& FEATURE_TCO
))
1344 pci_read_config_dword(pci_dev
, TCOBASE
, &tco_base
);
1345 pci_read_config_dword(pci_dev
, TCOCTL
, &tco_ctl
);
1346 if (!(tco_ctl
& TCOCTL_EN
))
1349 memset(tco_res
, 0, sizeof(tco_res
));
1351 res
= &tco_res
[ICH_RES_IO_TCO
];
1352 res
->start
= tco_base
& ~1;
1353 res
->end
= res
->start
+ 32 - 1;
1354 res
->flags
= IORESOURCE_IO
;
1357 * Power Management registers.
1359 devfn
= PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 2);
1360 pci_bus_read_config_dword(pci_dev
->bus
, devfn
, ACPIBASE
, &base_addr
);
1362 res
= &tco_res
[ICH_RES_IO_SMI
];
1363 res
->start
= (base_addr
& ~1) + ACPIBASE_SMI_OFF
;
1364 res
->end
= res
->start
+ 3;
1365 res
->flags
= IORESOURCE_IO
;
1368 * Enable the ACPI I/O space.
1370 pci_bus_read_config_dword(pci_dev
->bus
, devfn
, ACPICTRL
, &ctrl_val
);
1371 ctrl_val
|= ACPICTRL_EN
;
1372 pci_bus_write_config_dword(pci_dev
->bus
, devfn
, ACPICTRL
, ctrl_val
);
1375 * We must access the NO_REBOOT bit over the Primary to Sideband
1376 * bridge (P2SB). The BIOS prevents the P2SB device from being
1377 * enumerated by the PCI subsystem, so we need to unhide/hide it
1378 * to lookup the P2SB BAR.
1380 spin_lock(&p2sb_spinlock
);
1382 devfn
= PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 1);
1384 /* Unhide the P2SB device, if it is hidden */
1385 pci_bus_read_config_byte(pci_dev
->bus
, devfn
, 0xe1, &hidden
);
1387 pci_bus_write_config_byte(pci_dev
->bus
, devfn
, 0xe1, 0x0);
1389 pci_bus_read_config_dword(pci_dev
->bus
, devfn
, SBREG_BAR
, &base_addr
);
1390 base64_addr
= base_addr
& 0xfffffff0;
1392 pci_bus_read_config_dword(pci_dev
->bus
, devfn
, SBREG_BAR
+ 0x4, &base_addr
);
1393 base64_addr
|= (u64
)base_addr
<< 32;
1395 /* Hide the P2SB device, if it was hidden before */
1397 pci_bus_write_config_byte(pci_dev
->bus
, devfn
, 0xe1, hidden
);
1398 spin_unlock(&p2sb_spinlock
);
1400 res
= &tco_res
[ICH_RES_MEM_OFF
];
1401 res
->start
= (resource_size_t
)base64_addr
+ SBREG_SMBCTRL
;
1402 res
->end
= res
->start
+ 3;
1403 res
->flags
= IORESOURCE_MEM
;
1405 pdev
= platform_device_register_resndata(&pci_dev
->dev
, "iTCO_wdt", -1,
1406 tco_res
, 3, &tco_platform_data
,
1407 sizeof(tco_platform_data
));
1409 dev_warn(&pci_dev
->dev
, "failed to create iTCO device\n");
1413 priv
->tco_pdev
= pdev
;
1418 i801_acpi_io_handler(u32 function
, acpi_physical_address address
, u32 bits
,
1419 u64
*value
, void *handler_context
, void *region_context
)
1421 struct i801_priv
*priv
= handler_context
;
1422 struct pci_dev
*pdev
= priv
->pci_dev
;
1426 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1427 * further access from the driver itself. This device is now owned
1428 * by the system firmware.
1430 mutex_lock(&priv
->acpi_lock
);
1432 if (!priv
->acpi_reserved
) {
1433 priv
->acpi_reserved
= true;
1435 dev_warn(&pdev
->dev
, "BIOS is accessing SMBus registers\n");
1436 dev_warn(&pdev
->dev
, "Driver SMBus register access inhibited\n");
1439 * BIOS is accessing the host controller so prevent it from
1440 * suspending automatically from now on.
1442 pm_runtime_get_sync(&pdev
->dev
);
1445 if ((function
& ACPI_IO_MASK
) == ACPI_READ
)
1446 status
= acpi_os_read_port(address
, (u32
*)value
, bits
);
1448 status
= acpi_os_write_port(address
, (u32
)*value
, bits
);
1450 mutex_unlock(&priv
->acpi_lock
);
1455 static int i801_acpi_probe(struct i801_priv
*priv
)
1457 struct acpi_device
*adev
;
1460 adev
= ACPI_COMPANION(&priv
->pci_dev
->dev
);
1462 status
= acpi_install_address_space_handler(adev
->handle
,
1463 ACPI_ADR_SPACE_SYSTEM_IO
, i801_acpi_io_handler
,
1465 if (ACPI_SUCCESS(status
))
1469 return acpi_check_resource_conflict(&priv
->pci_dev
->resource
[SMBBAR
]);
1472 static void i801_acpi_remove(struct i801_priv
*priv
)
1474 struct acpi_device
*adev
;
1476 adev
= ACPI_COMPANION(&priv
->pci_dev
->dev
);
1480 acpi_remove_address_space_handler(adev
->handle
,
1481 ACPI_ADR_SPACE_SYSTEM_IO
, i801_acpi_io_handler
);
1483 mutex_lock(&priv
->acpi_lock
);
1484 if (priv
->acpi_reserved
)
1485 pm_runtime_put(&priv
->pci_dev
->dev
);
1486 mutex_unlock(&priv
->acpi_lock
);
1489 static inline int i801_acpi_probe(struct i801_priv
*priv
) { return 0; }
1490 static inline void i801_acpi_remove(struct i801_priv
*priv
) { }
1493 static int i801_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1497 struct i801_priv
*priv
;
1499 priv
= devm_kzalloc(&dev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1503 i2c_set_adapdata(&priv
->adapter
, priv
);
1504 priv
->adapter
.owner
= THIS_MODULE
;
1505 priv
->adapter
.class = i801_get_adapter_class(priv
);
1506 priv
->adapter
.algo
= &smbus_algorithm
;
1507 priv
->adapter
.dev
.parent
= &dev
->dev
;
1508 ACPI_COMPANION_SET(&priv
->adapter
.dev
, ACPI_COMPANION(&dev
->dev
));
1509 priv
->adapter
.retries
= 3;
1510 mutex_init(&priv
->acpi_lock
);
1512 priv
->pci_dev
= dev
;
1513 switch (dev
->device
) {
1514 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS
:
1515 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS
:
1516 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS
:
1517 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS
:
1518 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS
:
1519 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS
:
1520 case PCI_DEVICE_ID_INTEL_CDF_SMBUS
:
1521 case PCI_DEVICE_ID_INTEL_DNV_SMBUS
:
1522 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS
:
1523 priv
->features
|= FEATURE_I2C_BLOCK_READ
;
1524 priv
->features
|= FEATURE_IRQ
;
1525 priv
->features
|= FEATURE_SMBUS_PEC
;
1526 priv
->features
|= FEATURE_BLOCK_BUFFER
;
1527 /* If we have ACPI based watchdog use that instead */
1528 if (!acpi_has_watchdog())
1529 priv
->features
|= FEATURE_TCO
;
1530 priv
->features
|= FEATURE_HOST_NOTIFY
;
1533 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0
:
1534 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1
:
1535 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2
:
1536 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0
:
1537 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1
:
1538 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2
:
1539 priv
->features
|= FEATURE_IDF
;
1542 priv
->features
|= FEATURE_I2C_BLOCK_READ
;
1543 priv
->features
|= FEATURE_IRQ
;
1545 case PCI_DEVICE_ID_INTEL_82801DB_3
:
1546 priv
->features
|= FEATURE_SMBUS_PEC
;
1547 priv
->features
|= FEATURE_BLOCK_BUFFER
;
1549 case PCI_DEVICE_ID_INTEL_82801CA_3
:
1550 priv
->features
|= FEATURE_HOST_NOTIFY
;
1552 case PCI_DEVICE_ID_INTEL_82801BA_2
:
1553 case PCI_DEVICE_ID_INTEL_82801AB_3
:
1554 case PCI_DEVICE_ID_INTEL_82801AA_3
:
1558 /* Disable features on user request */
1559 for (i
= 0; i
< ARRAY_SIZE(i801_feature_names
); i
++) {
1560 if (priv
->features
& disable_features
& (1 << i
))
1561 dev_notice(&dev
->dev
, "%s disabled by user\n",
1562 i801_feature_names
[i
]);
1564 priv
->features
&= ~disable_features
;
1566 err
= pcim_enable_device(dev
);
1568 dev_err(&dev
->dev
, "Failed to enable SMBus PCI device (%d)\n",
1572 pcim_pin_device(dev
);
1574 /* Determine the address of the SMBus area */
1575 priv
->smba
= pci_resource_start(dev
, SMBBAR
);
1578 "SMBus base address uninitialized, upgrade BIOS\n");
1582 if (i801_acpi_probe(priv
))
1585 err
= pcim_iomap_regions(dev
, 1 << SMBBAR
,
1586 dev_driver_string(&dev
->dev
));
1589 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1591 (unsigned long long)pci_resource_end(dev
, SMBBAR
));
1592 i801_acpi_remove(priv
);
1596 pci_read_config_byte(priv
->pci_dev
, SMBHSTCFG
, &temp
);
1597 priv
->original_hstcfg
= temp
;
1598 temp
&= ~SMBHSTCFG_I2C_EN
; /* SMBus timing */
1599 if (!(temp
& SMBHSTCFG_HST_EN
)) {
1600 dev_info(&dev
->dev
, "Enabling SMBus device\n");
1601 temp
|= SMBHSTCFG_HST_EN
;
1603 pci_write_config_byte(priv
->pci_dev
, SMBHSTCFG
, temp
);
1605 if (temp
& SMBHSTCFG_SMB_SMI_EN
) {
1606 dev_dbg(&dev
->dev
, "SMBus using interrupt SMI#\n");
1607 /* Disable SMBus interrupt feature if SMBus using SMI# */
1608 priv
->features
&= ~FEATURE_IRQ
;
1610 if (temp
& SMBHSTCFG_SPD_WD
)
1611 dev_info(&dev
->dev
, "SPD Write Disable is set\n");
1613 /* Clear special mode bits */
1614 if (priv
->features
& (FEATURE_SMBUS_PEC
| FEATURE_BLOCK_BUFFER
))
1615 outb_p(inb_p(SMBAUXCTL(priv
)) &
1616 ~(SMBAUXCTL_CRC
| SMBAUXCTL_E32B
), SMBAUXCTL(priv
));
1618 /* Default timeout in interrupt mode: 200 ms */
1619 priv
->adapter
.timeout
= HZ
/ 5;
1621 if (dev
->irq
== IRQ_NOTCONNECTED
)
1622 priv
->features
&= ~FEATURE_IRQ
;
1624 if (priv
->features
& FEATURE_IRQ
) {
1627 /* Complain if an interrupt is already pending */
1628 pci_read_config_word(priv
->pci_dev
, SMBPCISTS
, &pcists
);
1629 if (pcists
& SMBPCISTS_INTS
)
1630 dev_warn(&dev
->dev
, "An interrupt is pending!\n");
1632 /* Check if interrupts have been disabled */
1633 pci_read_config_word(priv
->pci_dev
, SMBPCICTL
, &pcictl
);
1634 if (pcictl
& SMBPCICTL_INTDIS
) {
1635 dev_info(&dev
->dev
, "Interrupts are disabled\n");
1636 priv
->features
&= ~FEATURE_IRQ
;
1640 if (priv
->features
& FEATURE_IRQ
) {
1641 init_waitqueue_head(&priv
->waitq
);
1643 err
= devm_request_irq(&dev
->dev
, dev
->irq
, i801_isr
,
1645 dev_driver_string(&dev
->dev
), priv
);
1647 dev_err(&dev
->dev
, "Failed to allocate irq %d: %d\n",
1649 priv
->features
&= ~FEATURE_IRQ
;
1652 dev_info(&dev
->dev
, "SMBus using %s\n",
1653 priv
->features
& FEATURE_IRQ
? "PCI interrupt" : "polling");
1657 snprintf(priv
->adapter
.name
, sizeof(priv
->adapter
.name
),
1658 "SMBus I801 adapter at %04lx", priv
->smba
);
1659 err
= i2c_add_adapter(&priv
->adapter
);
1661 i801_acpi_remove(priv
);
1665 i801_enable_host_notify(&priv
->adapter
);
1667 i801_probe_optional_slaves(priv
);
1668 /* We ignore errors - multiplexing is optional */
1671 pci_set_drvdata(dev
, priv
);
1673 pm_runtime_set_autosuspend_delay(&dev
->dev
, 1000);
1674 pm_runtime_use_autosuspend(&dev
->dev
);
1675 pm_runtime_put_autosuspend(&dev
->dev
);
1676 pm_runtime_allow(&dev
->dev
);
1681 static void i801_remove(struct pci_dev
*dev
)
1683 struct i801_priv
*priv
= pci_get_drvdata(dev
);
1685 pm_runtime_forbid(&dev
->dev
);
1686 pm_runtime_get_noresume(&dev
->dev
);
1688 i801_disable_host_notify(priv
);
1690 i2c_del_adapter(&priv
->adapter
);
1691 i801_acpi_remove(priv
);
1692 pci_write_config_byte(dev
, SMBHSTCFG
, priv
->original_hstcfg
);
1694 platform_device_unregister(priv
->tco_pdev
);
1697 * do not call pci_disable_device(dev) since it can cause hard hangs on
1698 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1703 static int i801_suspend(struct device
*dev
)
1705 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1706 struct i801_priv
*priv
= pci_get_drvdata(pci_dev
);
1708 pci_write_config_byte(pci_dev
, SMBHSTCFG
, priv
->original_hstcfg
);
1712 static int i801_resume(struct device
*dev
)
1714 struct pci_dev
*pci_dev
= to_pci_dev(dev
);
1715 struct i801_priv
*priv
= pci_get_drvdata(pci_dev
);
1717 i801_enable_host_notify(&priv
->adapter
);
1723 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops
, i801_suspend
,
1726 static struct pci_driver i801_driver
= {
1727 .name
= "i801_smbus",
1728 .id_table
= i801_ids
,
1729 .probe
= i801_probe
,
1730 .remove
= i801_remove
,
1736 static int __init
i2c_i801_init(void)
1738 if (dmi_name_in_vendors("FUJITSU"))
1739 input_apanel_init();
1740 return pci_register_driver(&i801_driver
);
1743 static void __exit
i2c_i801_exit(void)
1745 pci_unregister_driver(&i801_driver
);
1748 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1749 MODULE_DESCRIPTION("I801 SMBus driver");
1750 MODULE_LICENSE("GPL");
1752 module_init(i2c_i801_init
);
1753 module_exit(i2c_i801_exit
);