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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / i2c / busses / i2c-qup.c
blob08f8e01076423854124a1fb12a8cf608bd174314
1 /*
2 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014, Sony Mobile Communications AB.
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/acpi.h>
18 #include <linux/atomic.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dmapool.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/scatterlist.h>
33
34 /* QUP Registers */
35 #define QUP_CONFIG 0x000
36 #define QUP_STATE 0x004
37 #define QUP_IO_MODE 0x008
38 #define QUP_SW_RESET 0x00c
39 #define QUP_OPERATIONAL 0x018
40 #define QUP_ERROR_FLAGS 0x01c
41 #define QUP_ERROR_FLAGS_EN 0x020
42 #define QUP_OPERATIONAL_MASK 0x028
43 #define QUP_HW_VERSION 0x030
44 #define QUP_MX_OUTPUT_CNT 0x100
45 #define QUP_OUT_FIFO_BASE 0x110
46 #define QUP_MX_WRITE_CNT 0x150
47 #define QUP_MX_INPUT_CNT 0x200
48 #define QUP_MX_READ_CNT 0x208
49 #define QUP_IN_FIFO_BASE 0x218
50 #define QUP_I2C_CLK_CTL 0x400
51 #define QUP_I2C_STATUS 0x404
52 #define QUP_I2C_MASTER_GEN 0x408
53
54 /* QUP States and reset values */
55 #define QUP_RESET_STATE 0
56 #define QUP_RUN_STATE 1
57 #define QUP_PAUSE_STATE 3
58 #define QUP_STATE_MASK 3
59
60 #define QUP_STATE_VALID BIT(2)
61 #define QUP_I2C_MAST_GEN BIT(4)
62 #define QUP_I2C_FLUSH BIT(6)
63
64 #define QUP_OPERATIONAL_RESET 0x000ff0
65 #define QUP_I2C_STATUS_RESET 0xfffffc
66
67 /* QUP OPERATIONAL FLAGS */
68 #define QUP_I2C_NACK_FLAG BIT(3)
69 #define QUP_OUT_NOT_EMPTY BIT(4)
70 #define QUP_IN_NOT_EMPTY BIT(5)
71 #define QUP_OUT_FULL BIT(6)
72 #define QUP_OUT_SVC_FLAG BIT(8)
73 #define QUP_IN_SVC_FLAG BIT(9)
74 #define QUP_MX_OUTPUT_DONE BIT(10)
75 #define QUP_MX_INPUT_DONE BIT(11)
76
77 /* I2C mini core related values */
78 #define QUP_CLOCK_AUTO_GATE BIT(13)
79 #define I2C_MINI_CORE (2 << 8)
80 #define I2C_N_VAL 15
81 #define I2C_N_VAL_V2 7
82
83 /* Most significant word offset in FIFO port */
84 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
85
86 /* Packing/Unpacking words in FIFOs, and IO modes */
87 #define QUP_OUTPUT_BLK_MODE (1 << 10)
88 #define QUP_OUTPUT_BAM_MODE (3 << 10)
89 #define QUP_INPUT_BLK_MODE (1 << 12)
90 #define QUP_INPUT_BAM_MODE (3 << 12)
91 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
92 #define QUP_UNPACK_EN BIT(14)
93 #define QUP_PACK_EN BIT(15)
94
95 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
96 #define QUP_V2_TAGS_EN 1
97
98 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
99 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
100 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
101 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
102
103 /* QUP tags */
104 #define QUP_TAG_START (1 << 8)
105 #define QUP_TAG_DATA (2 << 8)
106 #define QUP_TAG_STOP (3 << 8)
107 #define QUP_TAG_REC (4 << 8)
108 #define QUP_BAM_INPUT_EOT 0x93
109 #define QUP_BAM_FLUSH_STOP 0x96
110
111 /* QUP v2 tags */
112 #define QUP_TAG_V2_START 0x81
113 #define QUP_TAG_V2_DATAWR 0x82
114 #define QUP_TAG_V2_DATAWR_STOP 0x83
115 #define QUP_TAG_V2_DATARD 0x85
116 #define QUP_TAG_V2_DATARD_STOP 0x87
117
118 /* Status, Error flags */
119 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
120 #define I2C_STATUS_BUS_ACTIVE BIT(8)
121 #define I2C_STATUS_ERROR_MASK 0x38000fc
122 #define QUP_STATUS_ERROR_FLAGS 0x7c
123
124 #define QUP_READ_LIMIT 256
125 #define SET_BIT 0x1
126 #define RESET_BIT 0x0
127 #define ONE_BYTE 0x1
128 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
129
130 #define MX_TX_RX_LEN SZ_64K
131 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
132
133 /* Max timeout in ms for 32k bytes */
134 #define TOUT_MAX 300
135
136 /* Default values. Use these if FW query fails */
137 #define DEFAULT_CLK_FREQ 100000
138 #define DEFAULT_SRC_CLK 20000000
139
140 struct qup_i2c_block {
141 int count;
142 int pos;
143 int tx_tag_len;
144 int rx_tag_len;
145 int data_len;
146 u8 tags[6];
147 };
148
149 struct qup_i2c_tag {
150 u8 *start;
151 dma_addr_t addr;
152 };
153
154 struct qup_i2c_bam {
155 struct qup_i2c_tag tag;
156 struct dma_chan *dma;
157 struct scatterlist *sg;
158 };
159
160 struct qup_i2c_dev {
161 struct device *dev;
162 void __iomem *base;
163 int irq;
164 struct clk *clk;
165 struct clk *pclk;
166 struct i2c_adapter adap;
167
168 int clk_ctl;
169 int out_fifo_sz;
170 int in_fifo_sz;
171 int out_blk_sz;
172 int in_blk_sz;
173
174 unsigned long one_byte_t;
175 struct qup_i2c_block blk;
176
177 struct i2c_msg *msg;
178 /* Current posion in user message buffer */
179 int pos;
180 /* I2C protocol errors */
181 u32 bus_err;
182 /* QUP core errors */
183 u32 qup_err;
184
185 /* To check if this is the last msg */
186 bool is_last;
187
188 /* To configure when bus is in run state */
189 int config_run;
190
191 /* dma parameters */
192 bool is_dma;
193 struct dma_pool *dpool;
194 struct qup_i2c_tag start_tag;
195 struct qup_i2c_bam brx;
196 struct qup_i2c_bam btx;
197
198 struct completion xfer;
199 };
200
201 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
202 {
203 struct qup_i2c_dev *qup = dev;
204 u32 bus_err;
205 u32 qup_err;
206 u32 opflags;
207
208 bus_err = readl(qup->base + QUP_I2C_STATUS);
209 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
210 opflags = readl(qup->base + QUP_OPERATIONAL);
211
212 if (!qup->msg) {
213 /* Clear Error interrupt */
214 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
215 return IRQ_HANDLED;
216 }
217
218 bus_err &= I2C_STATUS_ERROR_MASK;
219 qup_err &= QUP_STATUS_ERROR_FLAGS;
220
221 /* Clear the error bits in QUP_ERROR_FLAGS */
222 if (qup_err)
223 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
224
225 /* Clear the error bits in QUP_I2C_STATUS */
226 if (bus_err)
227 writel(bus_err, qup->base + QUP_I2C_STATUS);
228
229 /* Reset the QUP State in case of error */
230 if (qup_err || bus_err) {
231 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
232 goto done;
233 }
234
235 if (opflags & QUP_IN_SVC_FLAG)
236 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
237
238 if (opflags & QUP_OUT_SVC_FLAG)
239 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
240
241 done:
242 qup->qup_err = qup_err;
243 qup->bus_err = bus_err;
244 complete(&qup->xfer);
245 return IRQ_HANDLED;
246 }
247
248 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
249 u32 req_state, u32 req_mask)
250 {
251 int retries = 1;
252 u32 state;
253
254 /*
255 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
256 * cycles. So retry once after a 1uS delay.
257 */
258 do {
259 state = readl(qup->base + QUP_STATE);
260
261 if (state & QUP_STATE_VALID &&
262 (state & req_mask) == req_state)
263 return 0;
264
265 udelay(1);
266 } while (retries--);
267
268 return -ETIMEDOUT;
269 }
270
271 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
272 {
273 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
274 }
275
276 static void qup_i2c_flush(struct qup_i2c_dev *qup)
277 {
278 u32 val = readl(qup->base + QUP_STATE);
279
280 val |= QUP_I2C_FLUSH;
281 writel(val, qup->base + QUP_STATE);
282 }
283
284 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
285 {
286 return qup_i2c_poll_state_mask(qup, 0, 0);
287 }
288
289 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
290 {
291 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
292 }
293
294 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
295 {
296 if (qup_i2c_poll_state_valid(qup) != 0)
297 return -EIO;
298
299 writel(state, qup->base + QUP_STATE);
300
301 if (qup_i2c_poll_state(qup, state) != 0)
302 return -EIO;
303 return 0;
304 }
305
306 /**
307 * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
308 * @qup: The qup_i2c_dev device
309 * @op: The bit/event to wait on
310 * @val: value of the bit to wait on, 0 or 1
311 * @len: The length the bytes to be transferred
312 */
313 static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
314 int len)
315 {
316 unsigned long timeout;
317 u32 opflags;
318 u32 status;
319 u32 shift = __ffs(op);
320 int ret = 0;
321
322 len *= qup->one_byte_t;
323 /* timeout after a wait of twice the max time */
324 timeout = jiffies + len * 4;
325
326 for (;;) {
327 opflags = readl(qup->base + QUP_OPERATIONAL);
328 status = readl(qup->base + QUP_I2C_STATUS);
329
330 if (((opflags & op) >> shift) == val) {
331 if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
332 if (!(status & I2C_STATUS_BUS_ACTIVE)) {
333 ret = 0;
334 goto done;
335 }
336 } else {
337 ret = 0;
338 goto done;
339 }
340 }
341
342 if (time_after(jiffies, timeout)) {
343 ret = -ETIMEDOUT;
344 goto done;
345 }
346 usleep_range(len, len * 2);
347 }
348
349 done:
350 if (qup->bus_err || qup->qup_err)
351 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
352
353 return ret;
354 }
355
356 static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
357 struct i2c_msg *msg)
358 {
359 /* Number of entries to shift out, including the tags */
360 int total = msg->len + qup->blk.tx_tag_len;
361
362 total |= qup->config_run;
363
364 if (total < qup->out_fifo_sz) {
365 /* FIFO mode */
366 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
367 writel(total, qup->base + QUP_MX_WRITE_CNT);
368 } else {
369 /* BLOCK mode (transfer data on chunks) */
370 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
371 qup->base + QUP_IO_MODE);
372 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
373 }
374 }
375
376 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
377 {
378 /* Number of entries to shift out, including the start */
379 int total = msg->len + 1;
380
381 if (total < qup->out_fifo_sz) {
382 /* FIFO mode */
383 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
384 writel(total, qup->base + QUP_MX_WRITE_CNT);
385 } else {
386 /* BLOCK mode (transfer data on chunks) */
387 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
388 qup->base + QUP_IO_MODE);
389 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
390 }
391 }
392
393 static int check_for_fifo_space(struct qup_i2c_dev *qup)
394 {
395 int ret;
396
397 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
398 if (ret)
399 goto out;
400
401 ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
402 RESET_BIT, 4 * ONE_BYTE);
403 if (ret) {
404 /* Fifo is full. Drain out the fifo */
405 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
406 if (ret)
407 goto out;
408
409 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY,
410 RESET_BIT, 256 * ONE_BYTE);
411 if (ret) {
412 dev_err(qup->dev, "timeout for fifo out full");
413 goto out;
414 }
415
416 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
417 if (ret)
418 goto out;
419 }
420
421 out:
422 return ret;
423 }
424
425 static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
426 {
427 u32 addr = msg->addr << 1;
428 u32 qup_tag;
429 int idx;
430 u32 val;
431 int ret = 0;
432
433 if (qup->pos == 0) {
434 val = QUP_TAG_START | addr;
435 idx = 1;
436 } else {
437 val = 0;
438 idx = 0;
439 }
440
441 while (qup->pos < msg->len) {
442 /* Check that there's space in the FIFO for our pair */
443 ret = check_for_fifo_space(qup);
444 if (ret)
445 return ret;
446
447 if (qup->pos == msg->len - 1)
448 qup_tag = QUP_TAG_STOP;
449 else
450 qup_tag = QUP_TAG_DATA;
451
452 if (idx & 1)
453 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
454 else
455 val = qup_tag | msg->buf[qup->pos];
456
457 /* Write out the pair and the last odd value */
458 if (idx & 1 || qup->pos == msg->len - 1)
459 writel(val, qup->base + QUP_OUT_FIFO_BASE);
460
461 qup->pos++;
462 idx++;
463 }
464
465 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
466
467 return ret;
468 }
469
470 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
471 struct i2c_msg *msg)
472 {
473 memset(&qup->blk, 0, sizeof(qup->blk));
474
475 qup->blk.data_len = msg->len;
476 qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
477
478 /* 4 bytes for first block and 2 writes for rest */
479 qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
480
481 /* There are 2 tag bytes that are read in to fifo for every block */
482 if (msg->flags & I2C_M_RD)
483 qup->blk.rx_tag_len = qup->blk.count * 2;
484 }
485
486 static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
487 int dlen, u8 *dbuf)
488 {
489 u32 val = 0, idx = 0, pos = 0, i = 0, t;
490 int len = tlen + dlen;
491 u8 *buf = tbuf;
492 int ret = 0;
493
494 while (len > 0) {
495 ret = check_for_fifo_space(qup);
496 if (ret)
497 return ret;
498
499 t = (len >= 4) ? 4 : len;
500
501 while (idx < t) {
502 if (!i && (pos >= tlen)) {
503 buf = dbuf;
504 pos = 0;
505 i = 1;
506 }
507 val |= buf[pos++] << (idx++ * 8);
508 }
509
510 writel(val, qup->base + QUP_OUT_FIFO_BASE);
511 idx = 0;
512 val = 0;
513 len -= 4;
514 }
515
516 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
517
518 return ret;
519 }
520
521 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
522 {
523 int data_len;
524
525 if (qup->blk.data_len > QUP_READ_LIMIT)
526 data_len = QUP_READ_LIMIT;
527 else
528 data_len = qup->blk.data_len;
529
530 return data_len;
531 }
532
533 static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
534 {
535 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
536 }
537
538 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
539 struct i2c_msg *msg)
540 {
541 int len = 0;
542
543 if (msg->len > 1) {
544 tags[len++] = QUP_TAG_V2_DATARD_STOP;
545 tags[len++] = qup_i2c_get_data_len(qup) - 1;
546 } else {
547 tags[len++] = QUP_TAG_V2_START;
548 tags[len++] = addr & 0xff;
549
550 if (msg->flags & I2C_M_TEN)
551 tags[len++] = addr >> 8;
552
553 tags[len++] = QUP_TAG_V2_DATARD;
554 /* Read 1 byte indicating the length of the SMBus message */
555 tags[len++] = 1;
556 }
557 return len;
558 }
559
560 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
561 struct i2c_msg *msg, int is_dma)
562 {
563 u16 addr = i2c_8bit_addr_from_msg(msg);
564 int len = 0;
565 int data_len;
566
567 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
568
569 /* Handle tags for SMBus block read */
570 if (qup_i2c_check_msg_len(msg))
571 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
572
573 if (qup->blk.pos == 0) {
574 tags[len++] = QUP_TAG_V2_START;
575 tags[len++] = addr & 0xff;
576
577 if (msg->flags & I2C_M_TEN)
578 tags[len++] = addr >> 8;
579 }
580
581 /* Send _STOP commands for the last block */
582 if (last) {
583 if (msg->flags & I2C_M_RD)
584 tags[len++] = QUP_TAG_V2_DATARD_STOP;
585 else
586 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
587 } else {
588 if (msg->flags & I2C_M_RD)
589 tags[len++] = QUP_TAG_V2_DATARD;
590 else
591 tags[len++] = QUP_TAG_V2_DATAWR;
592 }
593
594 data_len = qup_i2c_get_data_len(qup);
595
596 /* 0 implies 256 bytes */
597 if (data_len == QUP_READ_LIMIT)
598 tags[len++] = 0;
599 else
600 tags[len++] = data_len;
601
602 if ((msg->flags & I2C_M_RD) && last && is_dma) {
603 tags[len++] = QUP_BAM_INPUT_EOT;
604 tags[len++] = QUP_BAM_FLUSH_STOP;
605 }
606
607 return len;
608 }
609
610 static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
611 {
612 int data_len = 0, tag_len, index;
613 int ret;
614
615 tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
616 index = msg->len - qup->blk.data_len;
617
618 /* only tags are written for read */
619 if (!(msg->flags & I2C_M_RD))
620 data_len = qup_i2c_get_data_len(qup);
621
622 ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
623 data_len, &msg->buf[index]);
624 qup->blk.data_len -= data_len;
625
626 return ret;
627 }
628
629 static void qup_i2c_bam_cb(void *data)
630 {
631 struct qup_i2c_dev *qup = data;
632
633 complete(&qup->xfer);
634 }
635
636 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
637 unsigned int buflen, struct qup_i2c_dev *qup,
638 int dir)
639 {
640 int ret;
641
642 sg_set_buf(sg, buf, buflen);
643 ret = dma_map_sg(qup->dev, sg, 1, dir);
644 if (!ret)
645 return -EINVAL;
646
647 return 0;
648 }
649
650 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
651 {
652 if (qup->btx.dma)
653 dma_release_channel(qup->btx.dma);
654 if (qup->brx.dma)
655 dma_release_channel(qup->brx.dma);
656 qup->btx.dma = NULL;
657 qup->brx.dma = NULL;
658 }
659
660 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
661 {
662 int err;
663
664 if (!qup->btx.dma) {
665 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
666 if (IS_ERR(qup->btx.dma)) {
667 err = PTR_ERR(qup->btx.dma);
668 qup->btx.dma = NULL;
669 dev_err(qup->dev, "\n tx channel not available");
670 return err;
671 }
672 }
673
674 if (!qup->brx.dma) {
675 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
676 if (IS_ERR(qup->brx.dma)) {
677 dev_err(qup->dev, "\n rx channel not available");
678 err = PTR_ERR(qup->brx.dma);
679 qup->brx.dma = NULL;
680 qup_i2c_rel_dma(qup);
681 return err;
682 }
683 }
684 return 0;
685 }
686
687 static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
688 int num)
689 {
690 struct dma_async_tx_descriptor *txd, *rxd = NULL;
691 int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
692 dma_cookie_t cookie_rx, cookie_tx;
693 u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
694 u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
695 u8 *tags;
696
697 while (idx < num) {
698 tx_len = 0, len = 0, i = 0;
699
700 qup->is_last = (idx == (num - 1));
701
702 qup_i2c_set_blk_data(qup, msg);
703
704 blocks = qup->blk.count;
705 rem = msg->len - (blocks - 1) * limit;
706
707 if (msg->flags & I2C_M_RD) {
708 rx_nents += (blocks * 2) + 1;
709 tx_nents += 1;
710
711 while (qup->blk.pos < blocks) {
712 tlen = (i == (blocks - 1)) ? rem : limit;
713 tags = &qup->start_tag.start[off + len];
714 len += qup_i2c_set_tags(tags, qup, msg, 1);
715 qup->blk.data_len -= tlen;
716
717 /* scratch buf to read the start and len tags */
718 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
719 &qup->brx.tag.start[0],
720 2, qup, DMA_FROM_DEVICE);
721
722 if (ret)
723 return ret;
724
725 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
726 &msg->buf[limit * i],
727 tlen, qup,
728 DMA_FROM_DEVICE);
729 if (ret)
730 return ret;
731
732 i++;
733 qup->blk.pos = i;
734 }
735 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
736 &qup->start_tag.start[off],
737 len, qup, DMA_TO_DEVICE);
738 if (ret)
739 return ret;
740
741 off += len;
742 /* scratch buf to read the BAM EOT and FLUSH tags */
743 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
744 &qup->brx.tag.start[0],
745 2, qup, DMA_FROM_DEVICE);
746 if (ret)
747 return ret;
748 } else {
749 tx_nents += (blocks * 2);
750
751 while (qup->blk.pos < blocks) {
752 tlen = (i == (blocks - 1)) ? rem : limit;
753 tags = &qup->start_tag.start[off + tx_len];
754 len = qup_i2c_set_tags(tags, qup, msg, 1);
755 qup->blk.data_len -= tlen;
756
757 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
758 tags, len,
759 qup, DMA_TO_DEVICE);
760 if (ret)
761 return ret;
762
763 tx_len += len;
764 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
765 &msg->buf[limit * i],
766 tlen, qup, DMA_TO_DEVICE);
767 if (ret)
768 return ret;
769 i++;
770 qup->blk.pos = i;
771 }
772 off += tx_len;
773
774 if (idx == (num - 1)) {
775 len = 1;
776 if (rx_nents) {
777 qup->btx.tag.start[0] =
778 QUP_BAM_INPUT_EOT;
779 len++;
780 }
781 qup->btx.tag.start[len - 1] =
782 QUP_BAM_FLUSH_STOP;
783 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
784 &qup->btx.tag.start[0],
785 len, qup, DMA_TO_DEVICE);
786 if (ret)
787 return ret;
788 tx_nents += 1;
789 }
790 }
791 idx++;
792 msg++;
793 }
794
795 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
796 DMA_MEM_TO_DEV,
797 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
798 if (!txd) {
799 dev_err(qup->dev, "failed to get tx desc\n");
800 ret = -EINVAL;
801 goto desc_err;
802 }
803
804 if (!rx_nents) {
805 txd->callback = qup_i2c_bam_cb;
806 txd->callback_param = qup;
807 }
808
809 cookie_tx = dmaengine_submit(txd);
810 if (dma_submit_error(cookie_tx)) {
811 ret = -EINVAL;
812 goto desc_err;
813 }
814
815 dma_async_issue_pending(qup->btx.dma);
816
817 if (rx_nents) {
818 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
819 rx_nents, DMA_DEV_TO_MEM,
820 DMA_PREP_INTERRUPT);
821 if (!rxd) {
822 dev_err(qup->dev, "failed to get rx desc\n");
823 ret = -EINVAL;
824
825 /* abort TX descriptors */
826 dmaengine_terminate_all(qup->btx.dma);
827 goto desc_err;
828 }
829
830 rxd->callback = qup_i2c_bam_cb;
831 rxd->callback_param = qup;
832 cookie_rx = dmaengine_submit(rxd);
833 if (dma_submit_error(cookie_rx)) {
834 ret = -EINVAL;
835 goto desc_err;
836 }
837
838 dma_async_issue_pending(qup->brx.dma);
839 }
840
841 if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
842 dev_err(qup->dev, "normal trans timed out\n");
843 ret = -ETIMEDOUT;
844 }
845
846 if (ret || qup->bus_err || qup->qup_err) {
847 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
848 dev_err(qup->dev, "change to run state timed out");
849 goto desc_err;
850 }
851
852 if (rx_nents)
853 writel(QUP_BAM_INPUT_EOT,
854 qup->base + QUP_OUT_FIFO_BASE);
855
856 writel(QUP_BAM_FLUSH_STOP, qup->base + QUP_OUT_FIFO_BASE);
857
858 qup_i2c_flush(qup);
859
860 /* wait for remaining interrupts to occur */
861 if (!wait_for_completion_timeout(&qup->xfer, HZ))
862 dev_err(qup->dev, "flush timed out\n");
863
864 qup_i2c_rel_dma(qup);
865
866 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
867 }
868
869 desc_err:
870 dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
871
872 if (rx_nents)
873 dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
874 DMA_FROM_DEVICE);
875
876 return ret;
877 }
878
879 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
880 int num)
881 {
882 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
883 int ret = 0;
884
885 enable_irq(qup->irq);
886 ret = qup_i2c_req_dma(qup);
887
888 if (ret)
889 goto out;
890
891 writel(0, qup->base + QUP_MX_INPUT_CNT);
892 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
893
894 /* set BAM mode */
895 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
896
897 /* mask fifo irqs */
898 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
899
900 /* set RUN STATE */
901 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
902 if (ret)
903 goto out;
904
905 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
906
907 qup->msg = msg;
908 ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
909 out:
910 disable_irq(qup->irq);
911
912 qup->msg = NULL;
913 return ret;
914 }
915
916 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
917 struct i2c_msg *msg)
918 {
919 unsigned long left;
920 int ret = 0;
921
922 left = wait_for_completion_timeout(&qup->xfer, HZ);
923 if (!left) {
924 writel(1, qup->base + QUP_SW_RESET);
925 ret = -ETIMEDOUT;
926 }
927
928 if (qup->bus_err || qup->qup_err)
929 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
930
931 return ret;
932 }
933
934 static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
935 {
936 int ret = 0;
937
938 qup->msg = msg;
939 qup->pos = 0;
940 enable_irq(qup->irq);
941 qup_i2c_set_blk_data(qup, msg);
942 qup_i2c_set_write_mode_v2(qup, msg);
943
944 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
945 if (ret)
946 goto err;
947
948 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
949
950 do {
951 ret = qup_i2c_issue_xfer_v2(qup, msg);
952 if (ret)
953 goto err;
954
955 ret = qup_i2c_wait_for_complete(qup, msg);
956 if (ret)
957 goto err;
958
959 qup->blk.pos++;
960 } while (qup->blk.pos < qup->blk.count);
961
962 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
963
964 err:
965 disable_irq(qup->irq);
966 qup->msg = NULL;
967
968 return ret;
969 }
970
971 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
972 {
973 int ret;
974
975 qup->msg = msg;
976 qup->pos = 0;
977
978 enable_irq(qup->irq);
979
980 qup_i2c_set_write_mode(qup, msg);
981
982 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
983 if (ret)
984 goto err;
985
986 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
987
988 do {
989 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
990 if (ret)
991 goto err;
992
993 ret = qup_i2c_issue_write(qup, msg);
994 if (ret)
995 goto err;
996
997 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
998 if (ret)
999 goto err;
1000
1001 ret = qup_i2c_wait_for_complete(qup, msg);
1002 if (ret)
1003 goto err;
1004 } while (qup->pos < msg->len);
1005
1006 /* Wait for the outstanding data in the fifo to drain */
1007 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
1008 err:
1009 disable_irq(qup->irq);
1010 qup->msg = NULL;
1011
1012 return ret;
1013 }
1014
1015 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
1016 {
1017 if (len < qup->in_fifo_sz) {
1018 /* FIFO mode */
1019 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
1020 writel(len, qup->base + QUP_MX_READ_CNT);
1021 } else {
1022 /* BLOCK mode (transfer data on chunks) */
1023 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
1024 qup->base + QUP_IO_MODE);
1025 writel(len, qup->base + QUP_MX_INPUT_CNT);
1026 }
1027 }
1028
1029 static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
1030 {
1031 int tx_len = qup->blk.tx_tag_len;
1032
1033 len += qup->blk.rx_tag_len;
1034 len |= qup->config_run;
1035 tx_len |= qup->config_run;
1036
1037 if (len < qup->in_fifo_sz) {
1038 /* FIFO mode */
1039 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
1040 writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
1041 writel(len, qup->base + QUP_MX_READ_CNT);
1042 } else {
1043 /* BLOCK mode (transfer data on chunks) */
1044 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
1045 qup->base + QUP_IO_MODE);
1046 writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
1047 writel(len, qup->base + QUP_MX_INPUT_CNT);
1048 }
1049 }
1050
1051 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1052 {
1053 u32 addr, len, val;
1054
1055 addr = i2c_8bit_addr_from_msg(msg);
1056
1057 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
1058 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
1059
1060 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
1061 writel(val, qup->base + QUP_OUT_FIFO_BASE);
1062 }
1063
1064
1065 static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1066 {
1067 u32 val = 0;
1068 int idx;
1069 int ret = 0;
1070
1071 for (idx = 0; qup->pos < msg->len; idx++) {
1072 if ((idx & 1) == 0) {
1073 /* Check that FIFO have data */
1074 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1075 SET_BIT, 4 * ONE_BYTE);
1076 if (ret)
1077 return ret;
1078
1079 /* Reading 2 words at time */
1080 val = readl(qup->base + QUP_IN_FIFO_BASE);
1081
1082 msg->buf[qup->pos++] = val & 0xFF;
1083 } else {
1084 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
1085 }
1086 }
1087
1088 return ret;
1089 }
1090
1091 static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
1092 struct i2c_msg *msg)
1093 {
1094 u32 val;
1095 int idx, pos = 0, ret = 0, total, msg_offset = 0;
1096
1097 /*
1098 * If the message length is already read in
1099 * the first byte of the buffer, account for
1100 * that by setting the offset
1101 */
1102 if (qup_i2c_check_msg_len(msg) && (msg->len > 1))
1103 msg_offset = 1;
1104 total = qup_i2c_get_data_len(qup);
1105 total -= msg_offset;
1106
1107 /* 2 extra bytes for read tags */
1108 while (pos < (total + 2)) {
1109 /* Check that FIFO have data */
1110 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1111 SET_BIT, 4 * ONE_BYTE);
1112 if (ret) {
1113 dev_err(qup->dev, "timeout for fifo not empty");
1114 return ret;
1115 }
1116 val = readl(qup->base + QUP_IN_FIFO_BASE);
1117
1118 for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
1119 /* first 2 bytes are tag bytes */
1120 if (pos < 2)
1121 continue;
1122
1123 if (pos >= (total + 2))
1124 goto out;
1125 msg->buf[qup->pos + msg_offset] = val & 0xff;
1126 qup->pos++;
1127 }
1128 }
1129
1130 out:
1131 qup->blk.data_len -= total;
1132
1133 return ret;
1134 }
1135
1136 static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1137 {
1138 int ret = 0;
1139
1140 qup->msg = msg;
1141 qup->pos = 0;
1142 enable_irq(qup->irq);
1143 qup_i2c_set_blk_data(qup, msg);
1144 qup_i2c_set_read_mode_v2(qup, msg->len);
1145
1146 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1147 if (ret)
1148 goto err;
1149
1150 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1151
1152 do {
1153 ret = qup_i2c_issue_xfer_v2(qup, msg);
1154 if (ret)
1155 goto err;
1156
1157 ret = qup_i2c_wait_for_complete(qup, msg);
1158 if (ret)
1159 goto err;
1160
1161 ret = qup_i2c_read_fifo_v2(qup, msg);
1162 if (ret)
1163 goto err;
1164
1165 qup->blk.pos++;
1166
1167 /* Handle SMBus block read length */
1168 if (qup_i2c_check_msg_len(msg) && (msg->len == 1)) {
1169 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) {
1170 ret = -EPROTO;
1171 goto err;
1172 }
1173 msg->len += msg->buf[0];
1174 qup->pos = 0;
1175 qup_i2c_set_blk_data(qup, msg);
1176 /* set tag length for block read */
1177 qup->blk.tx_tag_len = 2;
1178 qup_i2c_set_read_mode_v2(qup, msg->buf[0]);
1179 }
1180 } while (qup->blk.pos < qup->blk.count);
1181
1182 err:
1183 disable_irq(qup->irq);
1184 qup->msg = NULL;
1185
1186 return ret;
1187 }
1188
1189 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1190 {
1191 int ret;
1192
1193 qup->msg = msg;
1194 qup->pos = 0;
1195
1196 enable_irq(qup->irq);
1197 qup_i2c_set_read_mode(qup, msg->len);
1198
1199 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1200 if (ret)
1201 goto err;
1202
1203 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1204
1205 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1206 if (ret)
1207 goto err;
1208
1209 qup_i2c_issue_read(qup, msg);
1210
1211 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1212 if (ret)
1213 goto err;
1214
1215 do {
1216 ret = qup_i2c_wait_for_complete(qup, msg);
1217 if (ret)
1218 goto err;
1219
1220 ret = qup_i2c_read_fifo(qup, msg);
1221 if (ret)
1222 goto err;
1223 } while (qup->pos < msg->len);
1224
1225 err:
1226 disable_irq(qup->irq);
1227 qup->msg = NULL;
1228
1229 return ret;
1230 }
1231
1232 static int qup_i2c_xfer(struct i2c_adapter *adap,
1233 struct i2c_msg msgs[],
1234 int num)
1235 {
1236 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1237 int ret, idx;
1238
1239 ret = pm_runtime_get_sync(qup->dev);
1240 if (ret < 0)
1241 goto out;
1242
1243 qup->bus_err = 0;
1244 qup->qup_err = 0;
1245
1246 writel(1, qup->base + QUP_SW_RESET);
1247 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1248 if (ret)
1249 goto out;
1250
1251 /* Configure QUP as I2C mini core */
1252 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1253
1254 for (idx = 0; idx < num; idx++) {
1255 if (msgs[idx].len == 0) {
1256 ret = -EINVAL;
1257 goto out;
1258 }
1259
1260 if (qup_i2c_poll_state_i2c_master(qup)) {
1261 ret = -EIO;
1262 goto out;
1263 }
1264
1265 if (qup_i2c_check_msg_len(&msgs[idx])) {
1266 ret = -EINVAL;
1267 goto out;
1268 }
1269
1270 if (msgs[idx].flags & I2C_M_RD)
1271 ret = qup_i2c_read_one(qup, &msgs[idx]);
1272 else
1273 ret = qup_i2c_write_one(qup, &msgs[idx]);
1274
1275 if (ret)
1276 break;
1277
1278 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1279 if (ret)
1280 break;
1281 }
1282
1283 if (ret == 0)
1284 ret = num;
1285 out:
1286
1287 pm_runtime_mark_last_busy(qup->dev);
1288 pm_runtime_put_autosuspend(qup->dev);
1289
1290 return ret;
1291 }
1292
1293 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1294 struct i2c_msg msgs[],
1295 int num)
1296 {
1297 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1298 int ret, len, idx = 0, use_dma = 0;
1299
1300 qup->bus_err = 0;
1301 qup->qup_err = 0;
1302
1303 ret = pm_runtime_get_sync(qup->dev);
1304 if (ret < 0)
1305 goto out;
1306
1307 writel(1, qup->base + QUP_SW_RESET);
1308 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1309 if (ret)
1310 goto out;
1311
1312 /* Configure QUP as I2C mini core */
1313 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1314 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1315
1316 if ((qup->is_dma)) {
1317 /* All i2c_msgs should be transferred using either dma or cpu */
1318 for (idx = 0; idx < num; idx++) {
1319 if (msgs[idx].len == 0) {
1320 ret = -EINVAL;
1321 goto out;
1322 }
1323
1324 len = (msgs[idx].len > qup->out_fifo_sz) ||
1325 (msgs[idx].len > qup->in_fifo_sz);
1326
1327 if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
1328 use_dma = 1;
1329 } else {
1330 use_dma = 0;
1331 break;
1332 }
1333 }
1334 }
1335
1336 idx = 0;
1337
1338 do {
1339 if (msgs[idx].len == 0) {
1340 ret = -EINVAL;
1341 goto out;
1342 }
1343
1344 if (qup_i2c_poll_state_i2c_master(qup)) {
1345 ret = -EIO;
1346 goto out;
1347 }
1348
1349 qup->is_last = (idx == (num - 1));
1350 if (idx)
1351 qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
1352 else
1353 qup->config_run = 0;
1354
1355 reinit_completion(&qup->xfer);
1356
1357 if (use_dma) {
1358 ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
1359 } else {
1360 if (msgs[idx].flags & I2C_M_RD)
1361 ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
1362 else
1363 ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
1364 }
1365 } while ((idx++ < (num - 1)) && !use_dma && !ret);
1366
1367 if (!ret)
1368 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1369
1370 if (ret == 0)
1371 ret = num;
1372 out:
1373 pm_runtime_mark_last_busy(qup->dev);
1374 pm_runtime_put_autosuspend(qup->dev);
1375
1376 return ret;
1377 }
1378
1379 static u32 qup_i2c_func(struct i2c_adapter *adap)
1380 {
1381 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1382 }
1383
1384 static const struct i2c_algorithm qup_i2c_algo = {
1385 .master_xfer = qup_i2c_xfer,
1386 .functionality = qup_i2c_func,
1387 };
1388
1389 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1390 .master_xfer = qup_i2c_xfer_v2,
1391 .functionality = qup_i2c_func,
1392 };
1393
1394 /*
1395 * The QUP block will issue a NACK and STOP on the bus when reaching
1396 * the end of the read, the length of the read is specified as one byte
1397 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1398 */
1399 static const struct i2c_adapter_quirks qup_i2c_quirks = {
1400 .max_read_len = QUP_READ_LIMIT,
1401 };
1402
1403 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1404 {
1405 clk_prepare_enable(qup->clk);
1406 clk_prepare_enable(qup->pclk);
1407 }
1408
1409 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1410 {
1411 u32 config;
1412
1413 qup_i2c_change_state(qup, QUP_RESET_STATE);
1414 clk_disable_unprepare(qup->clk);
1415 config = readl(qup->base + QUP_CONFIG);
1416 config |= QUP_CLOCK_AUTO_GATE;
1417 writel(config, qup->base + QUP_CONFIG);
1418 clk_disable_unprepare(qup->pclk);
1419 }
1420
1421 static int qup_i2c_probe(struct platform_device *pdev)
1422 {
1423 static const int blk_sizes[] = {4, 16, 32};
1424 struct qup_i2c_dev *qup;
1425 unsigned long one_bit_t;
1426 struct resource *res;
1427 u32 io_mode, hw_ver, size;
1428 int ret, fs_div, hs_div;
1429 u32 src_clk_freq = DEFAULT_SRC_CLK;
1430 u32 clk_freq = DEFAULT_CLK_FREQ;
1431 int blocks;
1432
1433 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1434 if (!qup)
1435 return -ENOMEM;
1436
1437 qup->dev = &pdev->dev;
1438 init_completion(&qup->xfer);
1439 platform_set_drvdata(pdev, qup);
1440
1441 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1442 if (ret) {
1443 dev_notice(qup->dev, "using default clock-frequency %d",
1444 DEFAULT_CLK_FREQ);
1445 }
1446
1447 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1448 qup->adap.algo = &qup_i2c_algo;
1449 qup->adap.quirks = &qup_i2c_quirks;
1450 } else {
1451 qup->adap.algo = &qup_i2c_algo_v2;
1452 ret = qup_i2c_req_dma(qup);
1453
1454 if (ret == -EPROBE_DEFER)
1455 goto fail_dma;
1456 else if (ret != 0)
1457 goto nodma;
1458
1459 blocks = (MX_BLOCKS << 1) + 1;
1460 qup->btx.sg = devm_kzalloc(&pdev->dev,
1461 sizeof(*qup->btx.sg) * blocks,
1462 GFP_KERNEL);
1463 if (!qup->btx.sg) {
1464 ret = -ENOMEM;
1465 goto fail_dma;
1466 }
1467 sg_init_table(qup->btx.sg, blocks);
1468
1469 qup->brx.sg = devm_kzalloc(&pdev->dev,
1470 sizeof(*qup->brx.sg) * blocks,
1471 GFP_KERNEL);
1472 if (!qup->brx.sg) {
1473 ret = -ENOMEM;
1474 goto fail_dma;
1475 }
1476 sg_init_table(qup->brx.sg, blocks);
1477
1478 /* 2 tag bytes for each block + 5 for start, stop tags */
1479 size = blocks * 2 + 5;
1480
1481 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1482 size, GFP_KERNEL);
1483 if (!qup->start_tag.start) {
1484 ret = -ENOMEM;
1485 goto fail_dma;
1486 }
1487
1488 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1489 if (!qup->brx.tag.start) {
1490 ret = -ENOMEM;
1491 goto fail_dma;
1492 }
1493
1494 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1495 if (!qup->btx.tag.start) {
1496 ret = -ENOMEM;
1497 goto fail_dma;
1498 }
1499 qup->is_dma = true;
1500 }
1501
1502 nodma:
1503 /* We support frequencies up to FAST Mode (400KHz) */
1504 if (!clk_freq || clk_freq > 400000) {
1505 dev_err(qup->dev, "clock frequency not supported %d\n",
1506 clk_freq);
1507 return -EINVAL;
1508 }
1509
1510 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1511 qup->base = devm_ioremap_resource(qup->dev, res);
1512 if (IS_ERR(qup->base))
1513 return PTR_ERR(qup->base);
1514
1515 qup->irq = platform_get_irq(pdev, 0);
1516 if (qup->irq < 0) {
1517 dev_err(qup->dev, "No IRQ defined\n");
1518 return qup->irq;
1519 }
1520
1521 if (has_acpi_companion(qup->dev)) {
1522 ret = device_property_read_u32(qup->dev,
1523 "src-clock-hz", &src_clk_freq);
1524 if (ret) {
1525 dev_notice(qup->dev, "using default src-clock-hz %d",
1526 DEFAULT_SRC_CLK);
1527 }
1528 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1529 } else {
1530 qup->clk = devm_clk_get(qup->dev, "core");
1531 if (IS_ERR(qup->clk)) {
1532 dev_err(qup->dev, "Could not get core clock\n");
1533 return PTR_ERR(qup->clk);
1534 }
1535
1536 qup->pclk = devm_clk_get(qup->dev, "iface");
1537 if (IS_ERR(qup->pclk)) {
1538 dev_err(qup->dev, "Could not get iface clock\n");
1539 return PTR_ERR(qup->pclk);
1540 }
1541 qup_i2c_enable_clocks(qup);
1542 src_clk_freq = clk_get_rate(qup->clk);
1543 }
1544
1545 /*
1546 * Bootloaders might leave a pending interrupt on certain QUP's,
1547 * so we reset the core before registering for interrupts.
1548 */
1549 writel(1, qup->base + QUP_SW_RESET);
1550 ret = qup_i2c_poll_state_valid(qup);
1551 if (ret)
1552 goto fail;
1553
1554 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1555 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1556 if (ret) {
1557 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1558 goto fail;
1559 }
1560 disable_irq(qup->irq);
1561
1562 hw_ver = readl(qup->base + QUP_HW_VERSION);
1563 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1564
1565 io_mode = readl(qup->base + QUP_IO_MODE);
1566
1567 /*
1568 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1569 * associated with each byte written/received
1570 */
1571 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1572 if (size >= ARRAY_SIZE(blk_sizes)) {
1573 ret = -EIO;
1574 goto fail;
1575 }
1576 qup->out_blk_sz = blk_sizes[size] / 2;
1577
1578 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1579 if (size >= ARRAY_SIZE(blk_sizes)) {
1580 ret = -EIO;
1581 goto fail;
1582 }
1583 qup->in_blk_sz = blk_sizes[size] / 2;
1584
1585 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1586 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1587
1588 size = QUP_INPUT_FIFO_SIZE(io_mode);
1589 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1590
1591 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1592 hs_div = 3;
1593 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1594
1595 /*
1596 * Time it takes for a byte to be clocked out on the bus.
1597 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1598 */
1599 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1600 qup->one_byte_t = one_bit_t * 9;
1601
1602 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1603 qup->in_blk_sz, qup->in_fifo_sz,
1604 qup->out_blk_sz, qup->out_fifo_sz);
1605
1606 i2c_set_adapdata(&qup->adap, qup);
1607 qup->adap.dev.parent = qup->dev;
1608 qup->adap.dev.of_node = pdev->dev.of_node;
1609 qup->is_last = true;
1610
1611 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1612
1613 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1614 pm_runtime_use_autosuspend(qup->dev);
1615 pm_runtime_set_active(qup->dev);
1616 pm_runtime_enable(qup->dev);
1617
1618 ret = i2c_add_adapter(&qup->adap);
1619 if (ret)
1620 goto fail_runtime;
1621
1622 return 0;
1623
1624 fail_runtime:
1625 pm_runtime_disable(qup->dev);
1626 pm_runtime_set_suspended(qup->dev);
1627 fail:
1628 qup_i2c_disable_clocks(qup);
1629 fail_dma:
1630 if (qup->btx.dma)
1631 dma_release_channel(qup->btx.dma);
1632 if (qup->brx.dma)
1633 dma_release_channel(qup->brx.dma);
1634 return ret;
1635 }
1636
1637 static int qup_i2c_remove(struct platform_device *pdev)
1638 {
1639 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1640
1641 if (qup->is_dma) {
1642 dma_release_channel(qup->btx.dma);
1643 dma_release_channel(qup->brx.dma);
1644 }
1645
1646 disable_irq(qup->irq);
1647 qup_i2c_disable_clocks(qup);
1648 i2c_del_adapter(&qup->adap);
1649 pm_runtime_disable(qup->dev);
1650 pm_runtime_set_suspended(qup->dev);
1651 return 0;
1652 }
1653
1654 #ifdef CONFIG_PM
1655 static int qup_i2c_pm_suspend_runtime(struct device *device)
1656 {
1657 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1658
1659 dev_dbg(device, "pm_runtime: suspending...\n");
1660 qup_i2c_disable_clocks(qup);
1661 return 0;
1662 }
1663
1664 static int qup_i2c_pm_resume_runtime(struct device *device)
1665 {
1666 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1667
1668 dev_dbg(device, "pm_runtime: resuming...\n");
1669 qup_i2c_enable_clocks(qup);
1670 return 0;
1671 }
1672 #endif
1673
1674 #ifdef CONFIG_PM_SLEEP
1675 static int qup_i2c_suspend(struct device *device)
1676 {
1677 if (!pm_runtime_suspended(device))
1678 return qup_i2c_pm_suspend_runtime(device);
1679 return 0;
1680 }
1681
1682 static int qup_i2c_resume(struct device *device)
1683 {
1684 qup_i2c_pm_resume_runtime(device);
1685 pm_runtime_mark_last_busy(device);
1686 pm_request_autosuspend(device);
1687 return 0;
1688 }
1689 #endif
1690
1691 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1692 SET_SYSTEM_SLEEP_PM_OPS(
1693 qup_i2c_suspend,
1694 qup_i2c_resume)
1695 SET_RUNTIME_PM_OPS(
1696 qup_i2c_pm_suspend_runtime,
1697 qup_i2c_pm_resume_runtime,
1698 NULL)
1699 };
1700
1701 static const struct of_device_id qup_i2c_dt_match[] = {
1702 { .compatible = "qcom,i2c-qup-v1.1.1" },
1703 { .compatible = "qcom,i2c-qup-v2.1.1" },
1704 { .compatible = "qcom,i2c-qup-v2.2.1" },
1705 {}
1706 };
1707 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1708
1709 #if IS_ENABLED(CONFIG_ACPI)
1710 static const struct acpi_device_id qup_i2c_acpi_match[] = {
1711 { "QCOM8010"},
1712 { },
1713 };
1714 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1715 #endif
1716
1717 static struct platform_driver qup_i2c_driver = {
1718 .probe = qup_i2c_probe,
1719 .remove = qup_i2c_remove,
1720 .driver = {
1721 .name = "i2c_qup",
1722 .pm = &qup_i2c_qup_pm_ops,
1723 .of_match_table = qup_i2c_dt_match,
1724 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
1725 },
1726 };
1727
1728 module_platform_driver(qup_i2c_driver);
1729
1730 MODULE_LICENSE("GPL v2");
1731 MODULE_ALIAS("platform:i2c_qup");
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