drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-mux.h>
  15 #include <linux/kfifo.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/mutex.h>
  18 #include <linux/iio/iio.h>
  19 #include <linux/iio/buffer.h>
  20 #include <linux/regmap.h>
  21 #include <linux/iio/sysfs.h>
  22 #include <linux/iio/kfifo_buf.h>
  23 #include <linux/iio/trigger.h>
  24 #include <linux/iio/triggered_buffer.h>
  25 #include <linux/iio/trigger_consumer.h>
  26 #include <linux/platform_data/invensense_mpu6050.h>
  27
  28 /**
  29  *  struct inv_mpu6050_reg_map - Notable registers.
  30  *  @sample_rate_div:   Divider applied to gyro output rate.
  31  *  @lpf:               Configures internal low pass filter.
  32  *  @accel_lpf:         Configures accelerometer low pass filter.
  33  *  @user_ctrl:         Enables/resets the FIFO.
  34  *  @fifo_en:           Determines which data will appear in FIFO.
  35  *  @gyro_config:       gyro config register.
  36  *  @accl_config:       accel config register
  37  *  @fifo_count_h:      Upper byte of FIFO count.
  38  *  @fifo_r_w:          FIFO register.
  39  *  @raw_gyro:          Address of first gyro register.
  40  *  @raw_accl:          Address of first accel register.
  41  *  @temperature:       temperature register
  42  *  @int_enable:        Interrupt enable register.
  43  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  44  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  45  *  @int_pin_cfg;       Controls interrupt pin configuration.
  46  *  @accl_offset:       Controls the accelerometer calibration offset.
  47  *  @gyro_offset:       Controls the gyroscope calibration offset.
  48  */
  49 struct inv_mpu6050_reg_map {
  50         u8 sample_rate_div;
  51         u8 lpf;
  52         u8 accel_lpf;
  53         u8 user_ctrl;
  54         u8 fifo_en;
  55         u8 gyro_config;
  56         u8 accl_config;
  57         u8 fifo_count_h;
  58         u8 fifo_r_w;
  59         u8 raw_gyro;
  60         u8 raw_accl;
  61         u8 temperature;
  62         u8 int_enable;
  63         u8 pwr_mgmt_1;
  64         u8 pwr_mgmt_2;
  65         u8 int_pin_cfg;
  66         u8 accl_offset;
  67         u8 gyro_offset;
  68 };
  69
  70 /*device enum */
  71 enum inv_devices {
  72         INV_MPU6050,
  73         INV_MPU6500,
  74         INV_MPU6000,
  75         INV_MPU9150,
  76         INV_MPU9250,
  77         INV_ICM20608,
  78         INV_NUM_PARTS
  79 };
  80
  81 /**
  82  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  83  *  @fsr:               Full scale range.
  84  *  @lpf:               Digital low pass filter frequency.
  85  *  @accl_fs:           accel full scale range.
  86  *  @accl_fifo_enable:  enable accel data output
  87  *  @gyro_fifo_enable:  enable gyro data output
  88  *  @fifo_rate:         FIFO update rate.
  89  */
  90 struct inv_mpu6050_chip_config {
  91         unsigned int fsr:2;
  92         unsigned int lpf:3;
  93         unsigned int accl_fs:2;
  94         unsigned int accl_fifo_enable:1;
  95         unsigned int gyro_fifo_enable:1;
  96         u16 fifo_rate;
  97 };
  98
  99 /**
 100  *  struct inv_mpu6050_hw - Other important hardware information.
 101  *  @whoami:    Self identification byte from WHO_AM_I register
 102  *  @name:      name of the chip.
 103  *  @reg:   register map of the chip.
 104  *  @config:    configuration of the chip.
 105  */
 106 struct inv_mpu6050_hw {
 107         u8 whoami;
 108         u8 *name;
 109         const struct inv_mpu6050_reg_map *reg;
 110         const struct inv_mpu6050_chip_config *config;
 111 };
 112
 113 /*
 114  *  struct inv_mpu6050_state - Driver state variables.
 115  *  @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
 116  *  @lock:              Chip access lock.
 117  *  @trig:              IIO trigger.
 118  *  @chip_config:       Cached attribute information.
 119  *  @reg:               Map of important registers.
 120  *  @hw:                Other hardware-specific information.
 121  *  @chip_type:         chip type.
 122  *  @time_stamp_lock:   spin lock to time stamp.
 123  *  @plat_data:         platform data (deprecated in favor of @orientation).
 124  *  @orientation:       sensor chip orientation relative to main hardware.
 125  *  @timestamps:        kfifo queue to store time stamp.
 126  *  @map                regmap pointer.
 127  *  @irq                interrupt number.
 128  */
 129 struct inv_mpu6050_state {
 130 #define TIMESTAMP_FIFO_SIZE 16
 131         struct mutex lock;
 132         struct iio_trigger  *trig;
 133         struct inv_mpu6050_chip_config chip_config;
 134         const struct inv_mpu6050_reg_map *reg;
 135         const struct inv_mpu6050_hw *hw;
 136         enum   inv_devices chip_type;
 137         spinlock_t time_stamp_lock;
 138         struct i2c_mux_core *muxc;
 139         struct i2c_client *mux_client;
 140         unsigned int powerup_count;
 141         struct inv_mpu6050_platform_data plat_data;
 142         struct iio_mount_matrix orientation;
 143         DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
 144         struct regmap *map;
 145         int irq;
 146 };
 147
 148 /*register and associated bit definition*/
 149 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 150 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 151
 152 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 153 #define INV_MPU6050_REG_CONFIG              0x1A
 154 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 155 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 156
 157 #define INV_MPU6050_REG_FIFO_EN             0x23
 158 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 159 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 160
 161 #define INV_MPU6050_REG_INT_ENABLE          0x38
 162 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 163 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 164
 165 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 166 #define INV_MPU6050_REG_TEMPERATURE         0x41
 167 #define INV_MPU6050_REG_RAW_GYRO            0x43
 168
 169 #define INV_MPU6050_REG_USER_CTRL           0x6A
 170 #define INV_MPU6050_BIT_FIFO_RST            0x04
 171 #define INV_MPU6050_BIT_DMP_RST             0x08
 172 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 173 #define INV_MPU6050_BIT_FIFO_EN             0x40
 174 #define INV_MPU6050_BIT_DMP_EN              0x80
 175 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 176
 177 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 178 #define INV_MPU6050_BIT_H_RESET             0x80
 179 #define INV_MPU6050_BIT_SLEEP               0x40
 180 #define INV_MPU6050_BIT_CLK_MASK            0x7
 181
 182 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 183 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 184 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 185
 186 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 187 #define INV_MPU6050_REG_FIFO_R_W            0x74
 188
 189 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 190 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 191 #define INV_MPU6050_FIFO_THRESHOLD           500
 192
 193 /* mpu6500 registers */
 194 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 195 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 196
 197 /* delay time in milliseconds */
 198 #define INV_MPU6050_POWER_UP_TIME            100
 199 #define INV_MPU6050_TEMP_UP_TIME             100
 200 #define INV_MPU6050_SENSOR_UP_TIME           30
 201
 202 /* delay time in microseconds */
 203 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 204 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 205
 206 #define INV_MPU6050_TEMP_OFFSET              12421
 207 #define INV_MPU6050_TEMP_SCALE               2941
 208 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 209 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 210 #define INV_MPU6050_THREE_AXIS               3
 211 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 212 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 213
 214 /* 6 + 6 round up and plus 8 */
 215 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 216
 217 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 218 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 219 #define INV_MPU6050_INT_PIN_CFG         0
 220
 221 /* init parameters */
 222 #define INV_MPU6050_INIT_FIFO_RATE           50
 223 #define INV_MPU6050_TIME_STAMP_TOR           5
 224 #define INV_MPU6050_MAX_FIFO_RATE            1000
 225 #define INV_MPU6050_MIN_FIFO_RATE            4
 226 #define INV_MPU6050_ONE_K_HZ                 1000
 227
 228 #define INV_MPU6050_REG_WHOAMI                  117
 229
 230 #define INV_MPU6000_WHOAMI_VALUE                0x68
 231 #define INV_MPU6050_WHOAMI_VALUE                0x68
 232 #define INV_MPU6500_WHOAMI_VALUE                0x70
 233 #define INV_MPU9150_WHOAMI_VALUE                0x68
 234 #define INV_MPU9250_WHOAMI_VALUE                0x71
 235 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 236
 237 /* scan element definition */
 238 enum inv_mpu6050_scan {
 239         INV_MPU6050_SCAN_ACCL_X,
 240         INV_MPU6050_SCAN_ACCL_Y,
 241         INV_MPU6050_SCAN_ACCL_Z,
 242         INV_MPU6050_SCAN_GYRO_X,
 243         INV_MPU6050_SCAN_GYRO_Y,
 244         INV_MPU6050_SCAN_GYRO_Z,
 245         INV_MPU6050_SCAN_TIMESTAMP,
 246 };
 247
 248 enum inv_mpu6050_filter_e {
 249         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 250         INV_MPU6050_FILTER_188HZ,
 251         INV_MPU6050_FILTER_98HZ,
 252         INV_MPU6050_FILTER_42HZ,
 253         INV_MPU6050_FILTER_20HZ,
 254         INV_MPU6050_FILTER_10HZ,
 255         INV_MPU6050_FILTER_5HZ,
 256         INV_MPU6050_FILTER_2100HZ_NOLPF,
 257         NUM_MPU6050_FILTER
 258 };
 259
 260 /* IIO attribute address */
 261 enum INV_MPU6050_IIO_ATTR_ADDR {
 262         ATTR_GYRO_MATRIX,
 263         ATTR_ACCL_MATRIX,
 264 };
 265
 266 enum inv_mpu6050_accl_fs_e {
 267         INV_MPU6050_FS_02G = 0,
 268         INV_MPU6050_FS_04G,
 269         INV_MPU6050_FS_08G,
 270         INV_MPU6050_FS_16G,
 271         NUM_ACCL_FSR
 272 };
 273
 274 enum inv_mpu6050_fsr_e {
 275         INV_MPU6050_FSR_250DPS = 0,
 276         INV_MPU6050_FSR_500DPS,
 277         INV_MPU6050_FSR_1000DPS,
 278         INV_MPU6050_FSR_2000DPS,
 279         NUM_MPU6050_FSR
 280 };
 281
 282 enum inv_mpu6050_clock_sel_e {
 283         INV_CLK_INTERNAL = 0,
 284         INV_CLK_PLL,
 285         NUM_CLK
 286 };
 287
 288 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
 289 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 290 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
 291 void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
 292 int inv_reset_fifo(struct iio_dev *indio_dev);
 293 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 294 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 295 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 296 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 297 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 298 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 299                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 300 int inv_mpu_core_remove(struct device *dev);
 301 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 302 extern const struct dev_pm_ops inv_mpu_pmops;