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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / cxgb4 / qp.c
blobde77b6027d695da106004fdee247bfc8f1479e84
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
56
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62 {
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77 }
78
79 static void free_ird(struct c4iw_dev *dev, int ird)
80 {
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84 }
85
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87 {
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92 }
93
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95 {
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97 }
98
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100 {
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103 }
104
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106 {
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111 }
112
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114 {
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126 }
127
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129 {
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137 }
138
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140 {
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147 }
148
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151 {
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166 }
167
168 /*
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
171 * for mapping.
172 */
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
176 {
177 u64 bar2_qoffset;
178 int ret;
179
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
181 pbar2_pa ? 1 : 0,
182 &bar2_qoffset, pbar2_qid);
183 if (ret)
184 return NULL;
185
186 if (pbar2_pa)
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
188
189 if (is_t4(rdev->lldi.adapter_type))
190 return NULL;
191
192 return rdev->bar2_kva + bar2_qoffset;
193 }
194
195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx,
198 struct c4iw_wr_wait *wr_waitp)
199 {
200 int user = (uctx != &rdev->uctx);
201 struct fw_ri_res_wr *res_wr;
202 struct fw_ri_res *res;
203 int wr_len;
204 struct sk_buff *skb;
205 int ret = 0;
206 int eqsize;
207
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
209 if (!wq->sq.qid)
210 return -ENOMEM;
211
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
213 if (!wq->rq.qid) {
214 ret = -ENOMEM;
215 goto free_sq_qid;
216 }
217
218 if (!user) {
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
220 GFP_KERNEL);
221 if (!wq->sq.sw_sq) {
222 ret = -ENOMEM;
223 goto free_rq_qid;
224 }
225
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
227 GFP_KERNEL);
228 if (!wq->rq.sw_rq) {
229 ret = -ENOMEM;
230 goto free_sw_sq;
231 }
232 }
233
234 /*
235 * RQT must be a power of 2 and at least 16 deep.
236 */
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
240 ret = -ENOMEM;
241 goto free_sw_rq;
242 }
243
244 ret = alloc_sq(rdev, &wq->sq, user);
245 if (ret)
246 goto free_hwaddr;
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
249
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
252 GFP_KERNEL);
253 if (!wq->rq.queue) {
254 ret = -ENOMEM;
255 goto free_sq;
256 }
257 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue),
260 wq->rq.queue,
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
264
265 wq->db = rdev->lldi.db_reg;
266
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
268 &wq->sq.bar2_qid,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
271 &wq->rq.bar2_qid,
272 user ? &wq->rq.bar2_pa : NULL);
273
274 /*
275 * User mode must have bar2 access.
276 */
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
280 goto free_dma;
281 }
282
283 wq->rdev = rdev;
284 wq->rq.msn = 1;
285
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
288
289 skb = alloc_skb(wr_len, GFP_KERNEL);
290 if (!skb) {
291 ret = -ENOMEM;
292 goto free_dma;
293 }
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
295
296 res_wr = __skb_put_zero(skb, wr_len);
297 res_wr->op_nres = cpu_to_be32(
298 FW_WR_OP_V(FW_RI_RES_WR) |
299 FW_RI_RES_WR_NRES_V(2) |
300 FW_WR_COMPL_F);
301 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
302 res_wr->cookie = (uintptr_t)wr_waitp;
303 res = res_wr->res;
304 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
305 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
306
307 /*
308 * eqsize is the number of 64B entries plus the status page size.
309 */
310 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
311 rdev->hw_queue.t4_eq_status_entries;
312
313 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
314 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
315 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
316 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
317 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
318 FW_RI_RES_WR_IQID_V(scq->cqid));
319 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
320 FW_RI_RES_WR_DCAEN_V(0) |
321 FW_RI_RES_WR_DCACPU_V(0) |
322 FW_RI_RES_WR_FBMIN_V(2) |
323 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
324 FW_RI_RES_WR_FBMAX_V(3)) |
325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
326 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
327 FW_RI_RES_WR_EQSIZE_V(eqsize));
328 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
329 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
330 res++;
331 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
332 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
333
334 /*
335 * eqsize is the number of 64B entries plus the status page size.
336 */
337 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
338 rdev->hw_queue.t4_eq_status_entries;
339 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
343 FW_RI_RES_WR_IQID_V(rcq->cqid));
344 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
345 FW_RI_RES_WR_DCAEN_V(0) |
346 FW_RI_RES_WR_DCACPU_V(0) |
347 FW_RI_RES_WR_FBMIN_V(2) |
348 FW_RI_RES_WR_FBMAX_V(3) |
349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
350 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
351 FW_RI_RES_WR_EQSIZE_V(eqsize));
352 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
353 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
354
355 c4iw_init_wr_wait(wr_waitp);
356 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__);
357 if (ret)
358 goto free_dma;
359
360 pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
361 wq->sq.qid, wq->rq.qid, wq->db,
362 wq->sq.bar2_va, wq->rq.bar2_va);
363
364 return 0;
365 free_dma:
366 dma_free_coherent(&(rdev->lldi.pdev->dev),
367 wq->rq.memsize, wq->rq.queue,
368 dma_unmap_addr(&wq->rq, mapping));
369 free_sq:
370 dealloc_sq(rdev, &wq->sq);
371 free_hwaddr:
372 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
373 free_sw_rq:
374 kfree(wq->rq.sw_rq);
375 free_sw_sq:
376 kfree(wq->sq.sw_sq);
377 free_rq_qid:
378 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
379 free_sq_qid:
380 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
381 return ret;
382 }
383
384 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
385 struct ib_send_wr *wr, int max, u32 *plenp)
386 {
387 u8 *dstp, *srcp;
388 u32 plen = 0;
389 int i;
390 int rem, len;
391
392 dstp = (u8 *)immdp->data;
393 for (i = 0; i < wr->num_sge; i++) {
394 if ((plen + wr->sg_list[i].length) > max)
395 return -EMSGSIZE;
396 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
397 plen += wr->sg_list[i].length;
398 rem = wr->sg_list[i].length;
399 while (rem) {
400 if (dstp == (u8 *)&sq->queue[sq->size])
401 dstp = (u8 *)sq->queue;
402 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
403 len = rem;
404 else
405 len = (u8 *)&sq->queue[sq->size] - dstp;
406 memcpy(dstp, srcp, len);
407 dstp += len;
408 srcp += len;
409 rem -= len;
410 }
411 }
412 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
413 if (len)
414 memset(dstp, 0, len);
415 immdp->op = FW_RI_DATA_IMMD;
416 immdp->r1 = 0;
417 immdp->r2 = 0;
418 immdp->immdlen = cpu_to_be32(plen);
419 *plenp = plen;
420 return 0;
421 }
422
423 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
424 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
425 int num_sge, u32 *plenp)
426
427 {
428 int i;
429 u32 plen = 0;
430 __be64 *flitp = (__be64 *)isglp->sge;
431
432 for (i = 0; i < num_sge; i++) {
433 if ((plen + sg_list[i].length) < plen)
434 return -EMSGSIZE;
435 plen += sg_list[i].length;
436 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
437 sg_list[i].length);
438 if (++flitp == queue_end)
439 flitp = queue_start;
440 *flitp = cpu_to_be64(sg_list[i].addr);
441 if (++flitp == queue_end)
442 flitp = queue_start;
443 }
444 *flitp = (__force __be64)0;
445 isglp->op = FW_RI_DATA_ISGL;
446 isglp->r1 = 0;
447 isglp->nsge = cpu_to_be16(num_sge);
448 isglp->r2 = 0;
449 if (plenp)
450 *plenp = plen;
451 return 0;
452 }
453
454 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
455 struct ib_send_wr *wr, u8 *len16)
456 {
457 u32 plen;
458 int size;
459 int ret;
460
461 if (wr->num_sge > T4_MAX_SEND_SGE)
462 return -EINVAL;
463 switch (wr->opcode) {
464 case IB_WR_SEND:
465 if (wr->send_flags & IB_SEND_SOLICITED)
466 wqe->send.sendop_pkd = cpu_to_be32(
467 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
468 else
469 wqe->send.sendop_pkd = cpu_to_be32(
470 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
471 wqe->send.stag_inv = 0;
472 break;
473 case IB_WR_SEND_WITH_INV:
474 if (wr->send_flags & IB_SEND_SOLICITED)
475 wqe->send.sendop_pkd = cpu_to_be32(
476 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
477 else
478 wqe->send.sendop_pkd = cpu_to_be32(
479 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
480 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
481 break;
482
483 default:
484 return -EINVAL;
485 }
486 wqe->send.r3 = 0;
487 wqe->send.r4 = 0;
488
489 plen = 0;
490 if (wr->num_sge) {
491 if (wr->send_flags & IB_SEND_INLINE) {
492 ret = build_immd(sq, wqe->send.u.immd_src, wr,
493 T4_MAX_SEND_INLINE, &plen);
494 if (ret)
495 return ret;
496 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
497 plen;
498 } else {
499 ret = build_isgl((__be64 *)sq->queue,
500 (__be64 *)&sq->queue[sq->size],
501 wqe->send.u.isgl_src,
502 wr->sg_list, wr->num_sge, &plen);
503 if (ret)
504 return ret;
505 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
506 wr->num_sge * sizeof(struct fw_ri_sge);
507 }
508 } else {
509 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
510 wqe->send.u.immd_src[0].r1 = 0;
511 wqe->send.u.immd_src[0].r2 = 0;
512 wqe->send.u.immd_src[0].immdlen = 0;
513 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
514 plen = 0;
515 }
516 *len16 = DIV_ROUND_UP(size, 16);
517 wqe->send.plen = cpu_to_be32(plen);
518 return 0;
519 }
520
521 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
522 struct ib_send_wr *wr, u8 *len16)
523 {
524 u32 plen;
525 int size;
526 int ret;
527
528 if (wr->num_sge > T4_MAX_SEND_SGE)
529 return -EINVAL;
530 wqe->write.r2 = 0;
531 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
532 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
533 if (wr->num_sge) {
534 if (wr->send_flags & IB_SEND_INLINE) {
535 ret = build_immd(sq, wqe->write.u.immd_src, wr,
536 T4_MAX_WRITE_INLINE, &plen);
537 if (ret)
538 return ret;
539 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
540 plen;
541 } else {
542 ret = build_isgl((__be64 *)sq->queue,
543 (__be64 *)&sq->queue[sq->size],
544 wqe->write.u.isgl_src,
545 wr->sg_list, wr->num_sge, &plen);
546 if (ret)
547 return ret;
548 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
549 wr->num_sge * sizeof(struct fw_ri_sge);
550 }
551 } else {
552 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
553 wqe->write.u.immd_src[0].r1 = 0;
554 wqe->write.u.immd_src[0].r2 = 0;
555 wqe->write.u.immd_src[0].immdlen = 0;
556 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
557 plen = 0;
558 }
559 *len16 = DIV_ROUND_UP(size, 16);
560 wqe->write.plen = cpu_to_be32(plen);
561 return 0;
562 }
563
564 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
565 {
566 if (wr->num_sge > 1)
567 return -EINVAL;
568 if (wr->num_sge && wr->sg_list[0].length) {
569 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
570 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
571 >> 32));
572 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
573 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
574 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
575 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
576 >> 32));
577 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
578 } else {
579 wqe->read.stag_src = cpu_to_be32(2);
580 wqe->read.to_src_hi = 0;
581 wqe->read.to_src_lo = 0;
582 wqe->read.stag_sink = cpu_to_be32(2);
583 wqe->read.plen = 0;
584 wqe->read.to_sink_hi = 0;
585 wqe->read.to_sink_lo = 0;
586 }
587 wqe->read.r2 = 0;
588 wqe->read.r5 = 0;
589 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
590 return 0;
591 }
592
593 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
594 struct ib_recv_wr *wr, u8 *len16)
595 {
596 int ret;
597
598 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
599 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
600 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
601 if (ret)
602 return ret;
603 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
604 wr->num_sge * sizeof(struct fw_ri_sge), 16);
605 return 0;
606 }
607
608 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
609 struct ib_reg_wr *wr, struct c4iw_mr *mhp,
610 u8 *len16)
611 {
612 __be64 *p = (__be64 *)fr->pbl;
613
614 fr->r2 = cpu_to_be32(0);
615 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
616
617 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
618 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
619 FW_RI_TPTE_STAGSTATE_V(1) |
620 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
621 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
622 fr->tpte.locread_to_qpid = cpu_to_be32(
623 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
624 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
625 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
626 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
627 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
628 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
629 fr->tpte.len_hi = cpu_to_be32(0);
630 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
631 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
632 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
633
634 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
635 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
636
637 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
638 }
639
640 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
641 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
642 bool dsgl_supported)
643 {
644 struct fw_ri_immd *imdp;
645 __be64 *p;
646 int i;
647 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
648 int rem;
649
650 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
651 return -EINVAL;
652
653 wqe->fr.qpbinde_to_dcacpu = 0;
654 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
655 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
656 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
657 wqe->fr.len_hi = 0;
658 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
659 wqe->fr.stag = cpu_to_be32(wr->key);
660 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
661 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
662 0xffffffff);
663
664 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
665 struct fw_ri_dsgl *sglp;
666
667 for (i = 0; i < mhp->mpl_len; i++)
668 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
669
670 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
671 sglp->op = FW_RI_DATA_DSGL;
672 sglp->r1 = 0;
673 sglp->nsge = cpu_to_be16(1);
674 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
675 sglp->len0 = cpu_to_be32(pbllen);
676
677 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
678 } else {
679 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
680 imdp->op = FW_RI_DATA_IMMD;
681 imdp->r1 = 0;
682 imdp->r2 = 0;
683 imdp->immdlen = cpu_to_be32(pbllen);
684 p = (__be64 *)(imdp + 1);
685 rem = pbllen;
686 for (i = 0; i < mhp->mpl_len; i++) {
687 *p = cpu_to_be64((u64)mhp->mpl[i]);
688 rem -= sizeof(*p);
689 if (++p == (__be64 *)&sq->queue[sq->size])
690 p = (__be64 *)sq->queue;
691 }
692 while (rem) {
693 *p = 0;
694 rem -= sizeof(*p);
695 if (++p == (__be64 *)&sq->queue[sq->size])
696 p = (__be64 *)sq->queue;
697 }
698 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
699 + pbllen, 16);
700 }
701 return 0;
702 }
703
704 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
705 {
706 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
707 wqe->inv.r2 = 0;
708 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
709 return 0;
710 }
711
712 static void free_qp_work(struct work_struct *work)
713 {
714 struct c4iw_ucontext *ucontext;
715 struct c4iw_qp *qhp;
716 struct c4iw_dev *rhp;
717
718 qhp = container_of(work, struct c4iw_qp, free_work);
719 ucontext = qhp->ucontext;
720 rhp = qhp->rhp;
721
722 pr_debug("qhp %p ucontext %p\n", qhp, ucontext);
723 destroy_qp(&rhp->rdev, &qhp->wq,
724 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
725
726 if (ucontext)
727 c4iw_put_ucontext(ucontext);
728 c4iw_put_wr_wait(qhp->wr_waitp);
729 kfree(qhp);
730 }
731
732 static void queue_qp_free(struct kref *kref)
733 {
734 struct c4iw_qp *qhp;
735
736 qhp = container_of(kref, struct c4iw_qp, kref);
737 pr_debug("qhp %p\n", qhp);
738 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
739 }
740
741 void c4iw_qp_add_ref(struct ib_qp *qp)
742 {
743 pr_debug("ib_qp %p\n", qp);
744 kref_get(&to_c4iw_qp(qp)->kref);
745 }
746
747 void c4iw_qp_rem_ref(struct ib_qp *qp)
748 {
749 pr_debug("ib_qp %p\n", qp);
750 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
751 }
752
753 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
754 {
755 if (list_empty(entry))
756 list_add_tail(entry, head);
757 }
758
759 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
760 {
761 unsigned long flags;
762
763 spin_lock_irqsave(&qhp->rhp->lock, flags);
764 spin_lock(&qhp->lock);
765 if (qhp->rhp->db_state == NORMAL)
766 t4_ring_sq_db(&qhp->wq, inc, NULL);
767 else {
768 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
769 qhp->wq.sq.wq_pidx_inc += inc;
770 }
771 spin_unlock(&qhp->lock);
772 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
773 return 0;
774 }
775
776 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
777 {
778 unsigned long flags;
779
780 spin_lock_irqsave(&qhp->rhp->lock, flags);
781 spin_lock(&qhp->lock);
782 if (qhp->rhp->db_state == NORMAL)
783 t4_ring_rq_db(&qhp->wq, inc, NULL);
784 else {
785 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
786 qhp->wq.rq.wq_pidx_inc += inc;
787 }
788 spin_unlock(&qhp->lock);
789 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
790 return 0;
791 }
792
793 static int ib_to_fw_opcode(int ib_opcode)
794 {
795 int opcode;
796
797 switch (ib_opcode) {
798 case IB_WR_SEND_WITH_INV:
799 opcode = FW_RI_SEND_WITH_INV;
800 break;
801 case IB_WR_SEND:
802 opcode = FW_RI_SEND;
803 break;
804 case IB_WR_RDMA_WRITE:
805 opcode = FW_RI_RDMA_WRITE;
806 break;
807 case IB_WR_RDMA_READ:
808 case IB_WR_RDMA_READ_WITH_INV:
809 opcode = FW_RI_READ_REQ;
810 break;
811 case IB_WR_REG_MR:
812 opcode = FW_RI_FAST_REGISTER;
813 break;
814 case IB_WR_LOCAL_INV:
815 opcode = FW_RI_LOCAL_INV;
816 break;
817 default:
818 opcode = -EINVAL;
819 }
820 return opcode;
821 }
822
823 static int complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
824 {
825 struct t4_cqe cqe = {};
826 struct c4iw_cq *schp;
827 unsigned long flag;
828 struct t4_cq *cq;
829 int opcode;
830
831 schp = to_c4iw_cq(qhp->ibqp.send_cq);
832 cq = &schp->cq;
833
834 opcode = ib_to_fw_opcode(wr->opcode);
835 if (opcode < 0)
836 return opcode;
837
838 cqe.u.drain_cookie = wr->wr_id;
839 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
840 CQE_OPCODE_V(opcode) |
841 CQE_TYPE_V(1) |
842 CQE_SWCQE_V(1) |
843 CQE_DRAIN_V(1) |
844 CQE_QPID_V(qhp->wq.sq.qid));
845
846 spin_lock_irqsave(&schp->lock, flag);
847 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
848 cq->sw_queue[cq->sw_pidx] = cqe;
849 t4_swcq_produce(cq);
850 spin_unlock_irqrestore(&schp->lock, flag);
851
852 if (t4_clear_cq_armed(&schp->cq)) {
853 spin_lock_irqsave(&schp->comp_handler_lock, flag);
854 (*schp->ibcq.comp_handler)(&schp->ibcq,
855 schp->ibcq.cq_context);
856 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
857 }
858 return 0;
859 }
860
861 static int complete_sq_drain_wrs(struct c4iw_qp *qhp, struct ib_send_wr *wr,
862 struct ib_send_wr **bad_wr)
863 {
864 int ret = 0;
865
866 while (wr) {
867 ret = complete_sq_drain_wr(qhp, wr);
868 if (ret) {
869 *bad_wr = wr;
870 break;
871 }
872 wr = wr->next;
873 }
874 return ret;
875 }
876
877 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
878 {
879 struct t4_cqe cqe = {};
880 struct c4iw_cq *rchp;
881 unsigned long flag;
882 struct t4_cq *cq;
883
884 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
885 cq = &rchp->cq;
886
887 cqe.u.drain_cookie = wr->wr_id;
888 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
889 CQE_OPCODE_V(FW_RI_SEND) |
890 CQE_TYPE_V(0) |
891 CQE_SWCQE_V(1) |
892 CQE_DRAIN_V(1) |
893 CQE_QPID_V(qhp->wq.sq.qid));
894
895 spin_lock_irqsave(&rchp->lock, flag);
896 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
897 cq->sw_queue[cq->sw_pidx] = cqe;
898 t4_swcq_produce(cq);
899 spin_unlock_irqrestore(&rchp->lock, flag);
900
901 if (t4_clear_cq_armed(&rchp->cq)) {
902 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
903 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
904 rchp->ibcq.cq_context);
905 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
906 }
907 }
908
909 static void complete_rq_drain_wrs(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
910 {
911 while (wr) {
912 complete_rq_drain_wr(qhp, wr);
913 wr = wr->next;
914 }
915 }
916
917 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
918 struct ib_send_wr **bad_wr)
919 {
920 int err = 0;
921 u8 len16 = 0;
922 enum fw_wr_opcodes fw_opcode = 0;
923 enum fw_ri_wr_flags fw_flags;
924 struct c4iw_qp *qhp;
925 union t4_wr *wqe = NULL;
926 u32 num_wrs;
927 struct t4_swsqe *swsqe;
928 unsigned long flag;
929 u16 idx = 0;
930
931 qhp = to_c4iw_qp(ibqp);
932 spin_lock_irqsave(&qhp->lock, flag);
933
934 /*
935 * If the qp has been flushed, then just insert a special
936 * drain cqe.
937 */
938 if (qhp->wq.flushed) {
939 spin_unlock_irqrestore(&qhp->lock, flag);
940 err = complete_sq_drain_wrs(qhp, wr, bad_wr);
941 return err;
942 }
943 num_wrs = t4_sq_avail(&qhp->wq);
944 if (num_wrs == 0) {
945 spin_unlock_irqrestore(&qhp->lock, flag);
946 *bad_wr = wr;
947 return -ENOMEM;
948 }
949 while (wr) {
950 if (num_wrs == 0) {
951 err = -ENOMEM;
952 *bad_wr = wr;
953 break;
954 }
955 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
956 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
957
958 fw_flags = 0;
959 if (wr->send_flags & IB_SEND_SOLICITED)
960 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
961 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
962 fw_flags |= FW_RI_COMPLETION_FLAG;
963 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
964 switch (wr->opcode) {
965 case IB_WR_SEND_WITH_INV:
966 case IB_WR_SEND:
967 if (wr->send_flags & IB_SEND_FENCE)
968 fw_flags |= FW_RI_READ_FENCE_FLAG;
969 fw_opcode = FW_RI_SEND_WR;
970 if (wr->opcode == IB_WR_SEND)
971 swsqe->opcode = FW_RI_SEND;
972 else
973 swsqe->opcode = FW_RI_SEND_WITH_INV;
974 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
975 break;
976 case IB_WR_RDMA_WRITE:
977 fw_opcode = FW_RI_RDMA_WRITE_WR;
978 swsqe->opcode = FW_RI_RDMA_WRITE;
979 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
980 break;
981 case IB_WR_RDMA_READ:
982 case IB_WR_RDMA_READ_WITH_INV:
983 fw_opcode = FW_RI_RDMA_READ_WR;
984 swsqe->opcode = FW_RI_READ_REQ;
985 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
986 c4iw_invalidate_mr(qhp->rhp,
987 wr->sg_list[0].lkey);
988 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
989 } else {
990 fw_flags = 0;
991 }
992 err = build_rdma_read(wqe, wr, &len16);
993 if (err)
994 break;
995 swsqe->read_len = wr->sg_list[0].length;
996 if (!qhp->wq.sq.oldest_read)
997 qhp->wq.sq.oldest_read = swsqe;
998 break;
999 case IB_WR_REG_MR: {
1000 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
1001
1002 swsqe->opcode = FW_RI_FAST_REGISTER;
1003 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
1004 !mhp->attr.state && mhp->mpl_len <= 2) {
1005 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
1006 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
1007 mhp, &len16);
1008 } else {
1009 fw_opcode = FW_RI_FR_NSMR_WR;
1010 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
1011 mhp, &len16,
1012 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
1013 if (err)
1014 break;
1015 }
1016 mhp->attr.state = 1;
1017 break;
1018 }
1019 case IB_WR_LOCAL_INV:
1020 if (wr->send_flags & IB_SEND_FENCE)
1021 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
1022 fw_opcode = FW_RI_INV_LSTAG_WR;
1023 swsqe->opcode = FW_RI_LOCAL_INV;
1024 err = build_inv_stag(wqe, wr, &len16);
1025 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
1026 break;
1027 default:
1028 pr_warn("%s post of type=%d TBD!\n", __func__,
1029 wr->opcode);
1030 err = -EINVAL;
1031 }
1032 if (err) {
1033 *bad_wr = wr;
1034 break;
1035 }
1036 swsqe->idx = qhp->wq.sq.pidx;
1037 swsqe->complete = 0;
1038 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
1039 qhp->sq_sig_all;
1040 swsqe->flushed = 0;
1041 swsqe->wr_id = wr->wr_id;
1042 if (c4iw_wr_log) {
1043 swsqe->sge_ts = cxgb4_read_sge_timestamp(
1044 qhp->rhp->rdev.lldi.ports[0]);
1045 swsqe->host_time = ktime_get();
1046 }
1047
1048 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
1049
1050 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
1051 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
1052 swsqe->opcode, swsqe->read_len);
1053 wr = wr->next;
1054 num_wrs--;
1055 t4_sq_produce(&qhp->wq, len16);
1056 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1057 }
1058 if (!qhp->rhp->rdev.status_page->db_off) {
1059 t4_ring_sq_db(&qhp->wq, idx, wqe);
1060 spin_unlock_irqrestore(&qhp->lock, flag);
1061 } else {
1062 spin_unlock_irqrestore(&qhp->lock, flag);
1063 ring_kernel_sq_db(qhp, idx);
1064 }
1065 return err;
1066 }
1067
1068 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1069 struct ib_recv_wr **bad_wr)
1070 {
1071 int err = 0;
1072 struct c4iw_qp *qhp;
1073 union t4_recv_wr *wqe = NULL;
1074 u32 num_wrs;
1075 u8 len16 = 0;
1076 unsigned long flag;
1077 u16 idx = 0;
1078
1079 qhp = to_c4iw_qp(ibqp);
1080 spin_lock_irqsave(&qhp->lock, flag);
1081
1082 /*
1083 * If the qp has been flushed, then just insert a special
1084 * drain cqe.
1085 */
1086 if (qhp->wq.flushed) {
1087 spin_unlock_irqrestore(&qhp->lock, flag);
1088 complete_rq_drain_wrs(qhp, wr);
1089 return err;
1090 }
1091 num_wrs = t4_rq_avail(&qhp->wq);
1092 if (num_wrs == 0) {
1093 spin_unlock_irqrestore(&qhp->lock, flag);
1094 *bad_wr = wr;
1095 return -ENOMEM;
1096 }
1097 while (wr) {
1098 if (wr->num_sge > T4_MAX_RECV_SGE) {
1099 err = -EINVAL;
1100 *bad_wr = wr;
1101 break;
1102 }
1103 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1104 qhp->wq.rq.wq_pidx *
1105 T4_EQ_ENTRY_SIZE);
1106 if (num_wrs)
1107 err = build_rdma_recv(qhp, wqe, wr, &len16);
1108 else
1109 err = -ENOMEM;
1110 if (err) {
1111 *bad_wr = wr;
1112 break;
1113 }
1114
1115 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1116 if (c4iw_wr_log) {
1117 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1118 cxgb4_read_sge_timestamp(
1119 qhp->rhp->rdev.lldi.ports[0]);
1120 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_time =
1121 ktime_get();
1122 }
1123
1124 wqe->recv.opcode = FW_RI_RECV_WR;
1125 wqe->recv.r1 = 0;
1126 wqe->recv.wrid = qhp->wq.rq.pidx;
1127 wqe->recv.r2[0] = 0;
1128 wqe->recv.r2[1] = 0;
1129 wqe->recv.r2[2] = 0;
1130 wqe->recv.len16 = len16;
1131 pr_debug("cookie 0x%llx pidx %u\n",
1132 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1133 t4_rq_produce(&qhp->wq, len16);
1134 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1135 wr = wr->next;
1136 num_wrs--;
1137 }
1138 if (!qhp->rhp->rdev.status_page->db_off) {
1139 t4_ring_rq_db(&qhp->wq, idx, wqe);
1140 spin_unlock_irqrestore(&qhp->lock, flag);
1141 } else {
1142 spin_unlock_irqrestore(&qhp->lock, flag);
1143 ring_kernel_rq_db(qhp, idx);
1144 }
1145 return err;
1146 }
1147
1148 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1149 u8 *ecode)
1150 {
1151 int status;
1152 int tagged;
1153 int opcode;
1154 int rqtype;
1155 int send_inv;
1156
1157 if (!err_cqe) {
1158 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1159 *ecode = 0;
1160 return;
1161 }
1162
1163 status = CQE_STATUS(err_cqe);
1164 opcode = CQE_OPCODE(err_cqe);
1165 rqtype = RQ_TYPE(err_cqe);
1166 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1167 (opcode == FW_RI_SEND_WITH_SE_INV);
1168 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1169 (rqtype && (opcode == FW_RI_READ_RESP));
1170
1171 switch (status) {
1172 case T4_ERR_STAG:
1173 if (send_inv) {
1174 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1175 *ecode = RDMAP_CANT_INV_STAG;
1176 } else {
1177 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1178 *ecode = RDMAP_INV_STAG;
1179 }
1180 break;
1181 case T4_ERR_PDID:
1182 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1183 if ((opcode == FW_RI_SEND_WITH_INV) ||
1184 (opcode == FW_RI_SEND_WITH_SE_INV))
1185 *ecode = RDMAP_CANT_INV_STAG;
1186 else
1187 *ecode = RDMAP_STAG_NOT_ASSOC;
1188 break;
1189 case T4_ERR_QPID:
1190 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1191 *ecode = RDMAP_STAG_NOT_ASSOC;
1192 break;
1193 case T4_ERR_ACCESS:
1194 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1195 *ecode = RDMAP_ACC_VIOL;
1196 break;
1197 case T4_ERR_WRAP:
1198 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1199 *ecode = RDMAP_TO_WRAP;
1200 break;
1201 case T4_ERR_BOUND:
1202 if (tagged) {
1203 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1204 *ecode = DDPT_BASE_BOUNDS;
1205 } else {
1206 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1207 *ecode = RDMAP_BASE_BOUNDS;
1208 }
1209 break;
1210 case T4_ERR_INVALIDATE_SHARED_MR:
1211 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1212 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1213 *ecode = RDMAP_CANT_INV_STAG;
1214 break;
1215 case T4_ERR_ECC:
1216 case T4_ERR_ECC_PSTAG:
1217 case T4_ERR_INTERNAL_ERR:
1218 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1219 *ecode = 0;
1220 break;
1221 case T4_ERR_OUT_OF_RQE:
1222 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1223 *ecode = DDPU_INV_MSN_NOBUF;
1224 break;
1225 case T4_ERR_PBL_ADDR_BOUND:
1226 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1227 *ecode = DDPT_BASE_BOUNDS;
1228 break;
1229 case T4_ERR_CRC:
1230 *layer_type = LAYER_MPA|DDP_LLP;
1231 *ecode = MPA_CRC_ERR;
1232 break;
1233 case T4_ERR_MARKER:
1234 *layer_type = LAYER_MPA|DDP_LLP;
1235 *ecode = MPA_MARKER_ERR;
1236 break;
1237 case T4_ERR_PDU_LEN_ERR:
1238 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1239 *ecode = DDPU_MSG_TOOBIG;
1240 break;
1241 case T4_ERR_DDP_VERSION:
1242 if (tagged) {
1243 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1244 *ecode = DDPT_INV_VERS;
1245 } else {
1246 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1247 *ecode = DDPU_INV_VERS;
1248 }
1249 break;
1250 case T4_ERR_RDMA_VERSION:
1251 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1252 *ecode = RDMAP_INV_VERS;
1253 break;
1254 case T4_ERR_OPCODE:
1255 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1256 *ecode = RDMAP_INV_OPCODE;
1257 break;
1258 case T4_ERR_DDP_QUEUE_NUM:
1259 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1260 *ecode = DDPU_INV_QN;
1261 break;
1262 case T4_ERR_MSN:
1263 case T4_ERR_MSN_GAP:
1264 case T4_ERR_MSN_RANGE:
1265 case T4_ERR_IRD_OVERFLOW:
1266 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1267 *ecode = DDPU_INV_MSN_RANGE;
1268 break;
1269 case T4_ERR_TBIT:
1270 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1271 *ecode = 0;
1272 break;
1273 case T4_ERR_MO:
1274 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1275 *ecode = DDPU_INV_MO;
1276 break;
1277 default:
1278 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1279 *ecode = 0;
1280 break;
1281 }
1282 }
1283
1284 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1285 gfp_t gfp)
1286 {
1287 struct fw_ri_wr *wqe;
1288 struct sk_buff *skb;
1289 struct terminate_message *term;
1290
1291 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid,
1292 qhp->ep->hwtid);
1293
1294 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1295 if (WARN_ON(!skb))
1296 return;
1297
1298 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1299
1300 wqe = __skb_put(skb, sizeof(*wqe));
1301 memset(wqe, 0, sizeof *wqe);
1302 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1303 wqe->flowid_len16 = cpu_to_be32(
1304 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1305 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1306
1307 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1308 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1309 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1310 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1311 term->layer_etype = qhp->attr.layer_etype;
1312 term->ecode = qhp->attr.ecode;
1313 } else
1314 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1315 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1316 }
1317
1318 /*
1319 * Assumes qhp lock is held.
1320 */
1321 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1322 struct c4iw_cq *schp)
1323 {
1324 int count;
1325 int rq_flushed, sq_flushed;
1326 unsigned long flag;
1327
1328 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp);
1329
1330 /* locking hierarchy: cqs lock first, then qp lock. */
1331 spin_lock_irqsave(&rchp->lock, flag);
1332 if (schp != rchp)
1333 spin_lock(&schp->lock);
1334 spin_lock(&qhp->lock);
1335
1336 if (qhp->wq.flushed) {
1337 spin_unlock(&qhp->lock);
1338 if (schp != rchp)
1339 spin_unlock(&schp->lock);
1340 spin_unlock_irqrestore(&rchp->lock, flag);
1341 return;
1342 }
1343 qhp->wq.flushed = 1;
1344 t4_set_wq_in_error(&qhp->wq);
1345
1346 c4iw_flush_hw_cq(rchp);
1347 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1348 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1349
1350 if (schp != rchp)
1351 c4iw_flush_hw_cq(schp);
1352 sq_flushed = c4iw_flush_sq(qhp);
1353
1354 spin_unlock(&qhp->lock);
1355 if (schp != rchp)
1356 spin_unlock(&schp->lock);
1357 spin_unlock_irqrestore(&rchp->lock, flag);
1358
1359 if (schp == rchp) {
1360 if ((rq_flushed || sq_flushed) &&
1361 t4_clear_cq_armed(&rchp->cq)) {
1362 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1363 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1364 rchp->ibcq.cq_context);
1365 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1366 }
1367 } else {
1368 if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1369 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1370 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1371 rchp->ibcq.cq_context);
1372 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1373 }
1374 if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1375 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1376 (*schp->ibcq.comp_handler)(&schp->ibcq,
1377 schp->ibcq.cq_context);
1378 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1379 }
1380 }
1381 }
1382
1383 static void flush_qp(struct c4iw_qp *qhp)
1384 {
1385 struct c4iw_cq *rchp, *schp;
1386 unsigned long flag;
1387
1388 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1389 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1390
1391 if (qhp->ibqp.uobject) {
1392 t4_set_wq_in_error(&qhp->wq);
1393 t4_set_cq_in_error(&rchp->cq);
1394 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1395 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1396 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1397 if (schp != rchp) {
1398 t4_set_cq_in_error(&schp->cq);
1399 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1400 (*schp->ibcq.comp_handler)(&schp->ibcq,
1401 schp->ibcq.cq_context);
1402 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1403 }
1404 return;
1405 }
1406 __flush_qp(qhp, rchp, schp);
1407 }
1408
1409 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1410 struct c4iw_ep *ep)
1411 {
1412 struct fw_ri_wr *wqe;
1413 int ret;
1414 struct sk_buff *skb;
1415
1416 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid);
1417
1418 skb = skb_dequeue(&ep->com.ep_skb_list);
1419 if (WARN_ON(!skb))
1420 return -ENOMEM;
1421
1422 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1423
1424 wqe = __skb_put(skb, sizeof(*wqe));
1425 memset(wqe, 0, sizeof *wqe);
1426 wqe->op_compl = cpu_to_be32(
1427 FW_WR_OP_V(FW_RI_INIT_WR) |
1428 FW_WR_COMPL_F);
1429 wqe->flowid_len16 = cpu_to_be32(
1430 FW_WR_FLOWID_V(ep->hwtid) |
1431 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1432 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1433
1434 wqe->u.fini.type = FW_RI_TYPE_FINI;
1435
1436 ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp,
1437 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1438
1439 pr_debug("ret %d\n", ret);
1440 return ret;
1441 }
1442
1443 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1444 {
1445 pr_debug("p2p_type = %d\n", p2p_type);
1446 memset(&init->u, 0, sizeof init->u);
1447 switch (p2p_type) {
1448 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1449 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1450 init->u.write.stag_sink = cpu_to_be32(1);
1451 init->u.write.to_sink = cpu_to_be64(1);
1452 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1453 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1454 sizeof(struct fw_ri_immd),
1455 16);
1456 break;
1457 case FW_RI_INIT_P2PTYPE_READ_REQ:
1458 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1459 init->u.read.stag_src = cpu_to_be32(1);
1460 init->u.read.to_src_lo = cpu_to_be32(1);
1461 init->u.read.stag_sink = cpu_to_be32(1);
1462 init->u.read.to_sink_lo = cpu_to_be32(1);
1463 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1464 break;
1465 }
1466 }
1467
1468 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1469 {
1470 struct fw_ri_wr *wqe;
1471 int ret;
1472 struct sk_buff *skb;
1473
1474 pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp,
1475 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1476
1477 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1478 if (!skb) {
1479 ret = -ENOMEM;
1480 goto out;
1481 }
1482 ret = alloc_ird(rhp, qhp->attr.max_ird);
1483 if (ret) {
1484 qhp->attr.max_ird = 0;
1485 kfree_skb(skb);
1486 goto out;
1487 }
1488 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1489
1490 wqe = __skb_put(skb, sizeof(*wqe));
1491 memset(wqe, 0, sizeof *wqe);
1492 wqe->op_compl = cpu_to_be32(
1493 FW_WR_OP_V(FW_RI_INIT_WR) |
1494 FW_WR_COMPL_F);
1495 wqe->flowid_len16 = cpu_to_be32(
1496 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1497 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1498
1499 wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp;
1500
1501 wqe->u.init.type = FW_RI_TYPE_INIT;
1502 wqe->u.init.mpareqbit_p2ptype =
1503 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1504 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1505 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1506 if (qhp->attr.mpa_attr.recv_marker_enabled)
1507 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1508 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1509 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1510 if (qhp->attr.mpa_attr.crc_enabled)
1511 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1512
1513 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1514 FW_RI_QP_RDMA_WRITE_ENABLE |
1515 FW_RI_QP_BIND_ENABLE;
1516 if (!qhp->ibqp.uobject)
1517 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1518 FW_RI_QP_STAG0_ENABLE;
1519 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1520 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1521 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1522 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1523 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1524 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1525 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1526 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1527 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1528 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1529 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1530 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1531 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1532 rhp->rdev.lldi.vr->rq.start);
1533 if (qhp->attr.mpa_attr.initiator)
1534 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1535
1536 ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp,
1537 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1538 if (!ret)
1539 goto out;
1540
1541 free_ird(rhp, qhp->attr.max_ird);
1542 out:
1543 pr_debug("ret %d\n", ret);
1544 return ret;
1545 }
1546
1547 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1548 enum c4iw_qp_attr_mask mask,
1549 struct c4iw_qp_attributes *attrs,
1550 int internal)
1551 {
1552 int ret = 0;
1553 struct c4iw_qp_attributes newattr = qhp->attr;
1554 int disconnect = 0;
1555 int terminate = 0;
1556 int abort = 0;
1557 int free = 0;
1558 struct c4iw_ep *ep = NULL;
1559
1560 pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1561 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1562 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1563
1564 mutex_lock(&qhp->mutex);
1565
1566 /* Process attr changes if in IDLE */
1567 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1568 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1569 ret = -EIO;
1570 goto out;
1571 }
1572 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1573 newattr.enable_rdma_read = attrs->enable_rdma_read;
1574 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1575 newattr.enable_rdma_write = attrs->enable_rdma_write;
1576 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1577 newattr.enable_bind = attrs->enable_bind;
1578 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1579 if (attrs->max_ord > c4iw_max_read_depth) {
1580 ret = -EINVAL;
1581 goto out;
1582 }
1583 newattr.max_ord = attrs->max_ord;
1584 }
1585 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1586 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1587 ret = -EINVAL;
1588 goto out;
1589 }
1590 newattr.max_ird = attrs->max_ird;
1591 }
1592 qhp->attr = newattr;
1593 }
1594
1595 if (mask & C4IW_QP_ATTR_SQ_DB) {
1596 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1597 goto out;
1598 }
1599 if (mask & C4IW_QP_ATTR_RQ_DB) {
1600 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1601 goto out;
1602 }
1603
1604 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1605 goto out;
1606 if (qhp->attr.state == attrs->next_state)
1607 goto out;
1608
1609 switch (qhp->attr.state) {
1610 case C4IW_QP_STATE_IDLE:
1611 switch (attrs->next_state) {
1612 case C4IW_QP_STATE_RTS:
1613 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1614 ret = -EINVAL;
1615 goto out;
1616 }
1617 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1618 ret = -EINVAL;
1619 goto out;
1620 }
1621 qhp->attr.mpa_attr = attrs->mpa_attr;
1622 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1623 qhp->ep = qhp->attr.llp_stream_handle;
1624 set_state(qhp, C4IW_QP_STATE_RTS);
1625
1626 /*
1627 * Ref the endpoint here and deref when we
1628 * disassociate the endpoint from the QP. This
1629 * happens in CLOSING->IDLE transition or *->ERROR
1630 * transition.
1631 */
1632 c4iw_get_ep(&qhp->ep->com);
1633 ret = rdma_init(rhp, qhp);
1634 if (ret)
1635 goto err;
1636 break;
1637 case C4IW_QP_STATE_ERROR:
1638 set_state(qhp, C4IW_QP_STATE_ERROR);
1639 flush_qp(qhp);
1640 break;
1641 default:
1642 ret = -EINVAL;
1643 goto out;
1644 }
1645 break;
1646 case C4IW_QP_STATE_RTS:
1647 switch (attrs->next_state) {
1648 case C4IW_QP_STATE_CLOSING:
1649 t4_set_wq_in_error(&qhp->wq);
1650 set_state(qhp, C4IW_QP_STATE_CLOSING);
1651 ep = qhp->ep;
1652 if (!internal) {
1653 abort = 0;
1654 disconnect = 1;
1655 c4iw_get_ep(&qhp->ep->com);
1656 }
1657 ret = rdma_fini(rhp, qhp, ep);
1658 if (ret)
1659 goto err;
1660 break;
1661 case C4IW_QP_STATE_TERMINATE:
1662 t4_set_wq_in_error(&qhp->wq);
1663 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1664 qhp->attr.layer_etype = attrs->layer_etype;
1665 qhp->attr.ecode = attrs->ecode;
1666 ep = qhp->ep;
1667 if (!internal) {
1668 c4iw_get_ep(&qhp->ep->com);
1669 terminate = 1;
1670 disconnect = 1;
1671 } else {
1672 terminate = qhp->attr.send_term;
1673 ret = rdma_fini(rhp, qhp, ep);
1674 if (ret)
1675 goto err;
1676 }
1677 break;
1678 case C4IW_QP_STATE_ERROR:
1679 t4_set_wq_in_error(&qhp->wq);
1680 set_state(qhp, C4IW_QP_STATE_ERROR);
1681 if (!internal) {
1682 abort = 1;
1683 disconnect = 1;
1684 ep = qhp->ep;
1685 c4iw_get_ep(&qhp->ep->com);
1686 }
1687 goto err;
1688 break;
1689 default:
1690 ret = -EINVAL;
1691 goto out;
1692 }
1693 break;
1694 case C4IW_QP_STATE_CLOSING:
1695
1696 /*
1697 * Allow kernel users to move to ERROR for qp draining.
1698 */
1699 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1700 C4IW_QP_STATE_ERROR)) {
1701 ret = -EINVAL;
1702 goto out;
1703 }
1704 switch (attrs->next_state) {
1705 case C4IW_QP_STATE_IDLE:
1706 flush_qp(qhp);
1707 set_state(qhp, C4IW_QP_STATE_IDLE);
1708 qhp->attr.llp_stream_handle = NULL;
1709 c4iw_put_ep(&qhp->ep->com);
1710 qhp->ep = NULL;
1711 wake_up(&qhp->wait);
1712 break;
1713 case C4IW_QP_STATE_ERROR:
1714 goto err;
1715 default:
1716 ret = -EINVAL;
1717 goto err;
1718 }
1719 break;
1720 case C4IW_QP_STATE_ERROR:
1721 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1722 ret = -EINVAL;
1723 goto out;
1724 }
1725 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1726 ret = -EINVAL;
1727 goto out;
1728 }
1729 set_state(qhp, C4IW_QP_STATE_IDLE);
1730 break;
1731 case C4IW_QP_STATE_TERMINATE:
1732 if (!internal) {
1733 ret = -EINVAL;
1734 goto out;
1735 }
1736 goto err;
1737 break;
1738 default:
1739 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1740 ret = -EINVAL;
1741 goto err;
1742 break;
1743 }
1744 goto out;
1745 err:
1746 pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep,
1747 qhp->wq.sq.qid);
1748
1749 /* disassociate the LLP connection */
1750 qhp->attr.llp_stream_handle = NULL;
1751 if (!ep)
1752 ep = qhp->ep;
1753 qhp->ep = NULL;
1754 set_state(qhp, C4IW_QP_STATE_ERROR);
1755 free = 1;
1756 abort = 1;
1757 flush_qp(qhp);
1758 wake_up(&qhp->wait);
1759 out:
1760 mutex_unlock(&qhp->mutex);
1761
1762 if (terminate)
1763 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1764
1765 /*
1766 * If disconnect is 1, then we need to initiate a disconnect
1767 * on the EP. This can be a normal close (RTS->CLOSING) or
1768 * an abnormal close (RTS/CLOSING->ERROR).
1769 */
1770 if (disconnect) {
1771 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1772 GFP_KERNEL);
1773 c4iw_put_ep(&ep->com);
1774 }
1775
1776 /*
1777 * If free is 1, then we've disassociated the EP from the QP
1778 * and we need to dereference the EP.
1779 */
1780 if (free)
1781 c4iw_put_ep(&ep->com);
1782 pr_debug("exit state %d\n", qhp->attr.state);
1783 return ret;
1784 }
1785
1786 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1787 {
1788 struct c4iw_dev *rhp;
1789 struct c4iw_qp *qhp;
1790 struct c4iw_qp_attributes attrs;
1791
1792 qhp = to_c4iw_qp(ib_qp);
1793 rhp = qhp->rhp;
1794
1795 attrs.next_state = C4IW_QP_STATE_ERROR;
1796 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1797 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1798 else
1799 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1800 wait_event(qhp->wait, !qhp->ep);
1801
1802 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1803
1804 spin_lock_irq(&rhp->lock);
1805 if (!list_empty(&qhp->db_fc_entry))
1806 list_del_init(&qhp->db_fc_entry);
1807 spin_unlock_irq(&rhp->lock);
1808 free_ird(rhp, qhp->attr.max_ird);
1809
1810 c4iw_qp_rem_ref(ib_qp);
1811
1812 pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid);
1813 return 0;
1814 }
1815
1816 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1817 struct ib_udata *udata)
1818 {
1819 struct c4iw_dev *rhp;
1820 struct c4iw_qp *qhp;
1821 struct c4iw_pd *php;
1822 struct c4iw_cq *schp;
1823 struct c4iw_cq *rchp;
1824 struct c4iw_create_qp_resp uresp;
1825 unsigned int sqsize, rqsize;
1826 struct c4iw_ucontext *ucontext;
1827 int ret;
1828 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1829 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1830
1831 pr_debug("ib_pd %p\n", pd);
1832
1833 if (attrs->qp_type != IB_QPT_RC)
1834 return ERR_PTR(-EINVAL);
1835
1836 php = to_c4iw_pd(pd);
1837 rhp = php->rhp;
1838 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1839 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1840 if (!schp || !rchp)
1841 return ERR_PTR(-EINVAL);
1842
1843 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1844 return ERR_PTR(-EINVAL);
1845
1846 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1847 return ERR_PTR(-E2BIG);
1848 rqsize = attrs->cap.max_recv_wr + 1;
1849 if (rqsize < 8)
1850 rqsize = 8;
1851
1852 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1853 return ERR_PTR(-E2BIG);
1854 sqsize = attrs->cap.max_send_wr + 1;
1855 if (sqsize < 8)
1856 sqsize = 8;
1857
1858 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1859
1860 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1861 if (!qhp)
1862 return ERR_PTR(-ENOMEM);
1863
1864 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
1865 if (!qhp->wr_waitp) {
1866 ret = -ENOMEM;
1867 goto err_free_qhp;
1868 }
1869
1870 qhp->wq.sq.size = sqsize;
1871 qhp->wq.sq.memsize =
1872 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1873 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1874 qhp->wq.sq.flush_cidx = -1;
1875 qhp->wq.rq.size = rqsize;
1876 qhp->wq.rq.memsize =
1877 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1878 sizeof(*qhp->wq.rq.queue);
1879
1880 if (ucontext) {
1881 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1882 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1883 }
1884
1885 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1886 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
1887 qhp->wr_waitp);
1888 if (ret)
1889 goto err_free_wr_wait;
1890
1891 attrs->cap.max_recv_wr = rqsize - 1;
1892 attrs->cap.max_send_wr = sqsize - 1;
1893 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1894
1895 qhp->rhp = rhp;
1896 qhp->attr.pd = php->pdid;
1897 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1898 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1899 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1900 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1901 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1902 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1903 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1904 qhp->attr.state = C4IW_QP_STATE_IDLE;
1905 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1906 qhp->attr.enable_rdma_read = 1;
1907 qhp->attr.enable_rdma_write = 1;
1908 qhp->attr.enable_bind = 1;
1909 qhp->attr.max_ord = 0;
1910 qhp->attr.max_ird = 0;
1911 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1912 spin_lock_init(&qhp->lock);
1913 mutex_init(&qhp->mutex);
1914 init_waitqueue_head(&qhp->wait);
1915 kref_init(&qhp->kref);
1916 INIT_WORK(&qhp->free_work, free_qp_work);
1917
1918 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1919 if (ret)
1920 goto err_destroy_qp;
1921
1922 if (udata && ucontext) {
1923 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1924 if (!sq_key_mm) {
1925 ret = -ENOMEM;
1926 goto err_remove_handle;
1927 }
1928 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1929 if (!rq_key_mm) {
1930 ret = -ENOMEM;
1931 goto err_free_sq_key;
1932 }
1933 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1934 if (!sq_db_key_mm) {
1935 ret = -ENOMEM;
1936 goto err_free_rq_key;
1937 }
1938 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1939 if (!rq_db_key_mm) {
1940 ret = -ENOMEM;
1941 goto err_free_sq_db_key;
1942 }
1943 if (t4_sq_onchip(&qhp->wq.sq)) {
1944 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1945 GFP_KERNEL);
1946 if (!ma_sync_key_mm) {
1947 ret = -ENOMEM;
1948 goto err_free_rq_db_key;
1949 }
1950 uresp.flags = C4IW_QPF_ONCHIP;
1951 } else
1952 uresp.flags = 0;
1953 uresp.qid_mask = rhp->rdev.qpmask;
1954 uresp.sqid = qhp->wq.sq.qid;
1955 uresp.sq_size = qhp->wq.sq.size;
1956 uresp.sq_memsize = qhp->wq.sq.memsize;
1957 uresp.rqid = qhp->wq.rq.qid;
1958 uresp.rq_size = qhp->wq.rq.size;
1959 uresp.rq_memsize = qhp->wq.rq.memsize;
1960 spin_lock(&ucontext->mmap_lock);
1961 if (ma_sync_key_mm) {
1962 uresp.ma_sync_key = ucontext->key;
1963 ucontext->key += PAGE_SIZE;
1964 } else {
1965 uresp.ma_sync_key = 0;
1966 }
1967 uresp.sq_key = ucontext->key;
1968 ucontext->key += PAGE_SIZE;
1969 uresp.rq_key = ucontext->key;
1970 ucontext->key += PAGE_SIZE;
1971 uresp.sq_db_gts_key = ucontext->key;
1972 ucontext->key += PAGE_SIZE;
1973 uresp.rq_db_gts_key = ucontext->key;
1974 ucontext->key += PAGE_SIZE;
1975 spin_unlock(&ucontext->mmap_lock);
1976 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1977 if (ret)
1978 goto err_free_ma_sync_key;
1979 sq_key_mm->key = uresp.sq_key;
1980 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1981 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1982 insert_mmap(ucontext, sq_key_mm);
1983 rq_key_mm->key = uresp.rq_key;
1984 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1985 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1986 insert_mmap(ucontext, rq_key_mm);
1987 sq_db_key_mm->key = uresp.sq_db_gts_key;
1988 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1989 sq_db_key_mm->len = PAGE_SIZE;
1990 insert_mmap(ucontext, sq_db_key_mm);
1991 rq_db_key_mm->key = uresp.rq_db_gts_key;
1992 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1993 rq_db_key_mm->len = PAGE_SIZE;
1994 insert_mmap(ucontext, rq_db_key_mm);
1995 if (ma_sync_key_mm) {
1996 ma_sync_key_mm->key = uresp.ma_sync_key;
1997 ma_sync_key_mm->addr =
1998 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1999 PCIE_MA_SYNC_A) & PAGE_MASK;
2000 ma_sync_key_mm->len = PAGE_SIZE;
2001 insert_mmap(ucontext, ma_sync_key_mm);
2002 }
2003
2004 c4iw_get_ucontext(ucontext);
2005 qhp->ucontext = ucontext;
2006 }
2007 qhp->ibqp.qp_num = qhp->wq.sq.qid;
2008 INIT_LIST_HEAD(&qhp->db_fc_entry);
2009 pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
2010 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
2011 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
2012 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
2013 return &qhp->ibqp;
2014 err_free_ma_sync_key:
2015 kfree(ma_sync_key_mm);
2016 err_free_rq_db_key:
2017 kfree(rq_db_key_mm);
2018 err_free_sq_db_key:
2019 kfree(sq_db_key_mm);
2020 err_free_rq_key:
2021 kfree(rq_key_mm);
2022 err_free_sq_key:
2023 kfree(sq_key_mm);
2024 err_remove_handle:
2025 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
2026 err_destroy_qp:
2027 destroy_qp(&rhp->rdev, &qhp->wq,
2028 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
2029 err_free_wr_wait:
2030 c4iw_put_wr_wait(qhp->wr_waitp);
2031 err_free_qhp:
2032 kfree(qhp);
2033 return ERR_PTR(ret);
2034 }
2035
2036 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2037 int attr_mask, struct ib_udata *udata)
2038 {
2039 struct c4iw_dev *rhp;
2040 struct c4iw_qp *qhp;
2041 enum c4iw_qp_attr_mask mask = 0;
2042 struct c4iw_qp_attributes attrs;
2043
2044 pr_debug("ib_qp %p\n", ibqp);
2045
2046 /* iwarp does not support the RTR state */
2047 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
2048 attr_mask &= ~IB_QP_STATE;
2049
2050 /* Make sure we still have something left to do */
2051 if (!attr_mask)
2052 return 0;
2053
2054 memset(&attrs, 0, sizeof attrs);
2055 qhp = to_c4iw_qp(ibqp);
2056 rhp = qhp->rhp;
2057
2058 attrs.next_state = c4iw_convert_state(attr->qp_state);
2059 attrs.enable_rdma_read = (attr->qp_access_flags &
2060 IB_ACCESS_REMOTE_READ) ? 1 : 0;
2061 attrs.enable_rdma_write = (attr->qp_access_flags &
2062 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2063 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2064
2065
2066 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2067 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2068 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2069 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2070 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2071
2072 /*
2073 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2074 * ringing the queue db when we're in DB_FULL mode.
2075 * Only allow this on T4 devices.
2076 */
2077 attrs.sq_db_inc = attr->sq_psn;
2078 attrs.rq_db_inc = attr->rq_psn;
2079 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2080 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2081 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2082 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2083 return -EINVAL;
2084
2085 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2086 }
2087
2088 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2089 {
2090 pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn);
2091 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2092 }
2093
2094 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2095 int attr_mask, struct ib_qp_init_attr *init_attr)
2096 {
2097 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2098
2099 memset(attr, 0, sizeof *attr);
2100 memset(init_attr, 0, sizeof *init_attr);
2101 attr->qp_state = to_ib_qp_state(qhp->attr.state);
2102 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2103 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2104 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2105 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
2106 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2107 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2108 return 0;
2109 }
CRIS linux kernel tree