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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / mlx5 / cq.c
blob5b974fb97611bc57b6dd2110e1df487e9a001d42
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
37 #include "mlx5_ib.h"
38
39 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
40 {
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
42
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
44 }
45
46 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
47 {
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
52
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
55 type, mcq->cqn);
56 return;
57 }
58
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
64 }
65 }
66
67 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
68 {
69 return mlx5_buf_offset(&buf->buf, n * size);
70 }
71
72 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
73 {
74 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
75 }
76
77 static u8 sw_ownership_bit(int n, int nent)
78 {
79 return (n & nent) ? 1 : 0;
80 }
81
82 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
83 {
84 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
85 struct mlx5_cqe64 *cqe64;
86
87 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
88
89 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
90 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
91 return cqe;
92 } else {
93 return NULL;
94 }
95 }
96
97 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
98 {
99 return get_sw_cqe(cq, cq->mcq.cons_index);
100 }
101
102 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
103 {
104 switch (wq->wr_data[idx]) {
105 case MLX5_IB_WR_UMR:
106 return 0;
107
108 case IB_WR_LOCAL_INV:
109 return IB_WC_LOCAL_INV;
110
111 case IB_WR_REG_MR:
112 return IB_WC_REG_MR;
113
114 default:
115 pr_warn("unknown completion status\n");
116 return 0;
117 }
118 }
119
120 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
121 struct mlx5_ib_wq *wq, int idx)
122 {
123 wc->wc_flags = 0;
124 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
125 case MLX5_OPCODE_RDMA_WRITE_IMM:
126 wc->wc_flags |= IB_WC_WITH_IMM;
127 /* fall through */
128 case MLX5_OPCODE_RDMA_WRITE:
129 wc->opcode = IB_WC_RDMA_WRITE;
130 break;
131 case MLX5_OPCODE_SEND_IMM:
132 wc->wc_flags |= IB_WC_WITH_IMM;
133 /* fall through */
134 case MLX5_OPCODE_SEND:
135 case MLX5_OPCODE_SEND_INVAL:
136 wc->opcode = IB_WC_SEND;
137 break;
138 case MLX5_OPCODE_RDMA_READ:
139 wc->opcode = IB_WC_RDMA_READ;
140 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
141 break;
142 case MLX5_OPCODE_ATOMIC_CS:
143 wc->opcode = IB_WC_COMP_SWAP;
144 wc->byte_len = 8;
145 break;
146 case MLX5_OPCODE_ATOMIC_FA:
147 wc->opcode = IB_WC_FETCH_ADD;
148 wc->byte_len = 8;
149 break;
150 case MLX5_OPCODE_ATOMIC_MASKED_CS:
151 wc->opcode = IB_WC_MASKED_COMP_SWAP;
152 wc->byte_len = 8;
153 break;
154 case MLX5_OPCODE_ATOMIC_MASKED_FA:
155 wc->opcode = IB_WC_MASKED_FETCH_ADD;
156 wc->byte_len = 8;
157 break;
158 case MLX5_OPCODE_UMR:
159 wc->opcode = get_umr_comp(wq, idx);
160 break;
161 }
162 }
163
164 enum {
165 MLX5_GRH_IN_BUFFER = 1,
166 MLX5_GRH_IN_CQE = 2,
167 };
168
169 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
170 struct mlx5_ib_qp *qp)
171 {
172 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
173 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
174 struct mlx5_ib_srq *srq;
175 struct mlx5_ib_wq *wq;
176 u16 wqe_ctr;
177 u8 roce_packet_type;
178 bool vlan_present;
179 u8 g;
180
181 if (qp->ibqp.srq || qp->ibqp.xrcd) {
182 struct mlx5_core_srq *msrq = NULL;
183
184 if (qp->ibqp.xrcd) {
185 msrq = mlx5_core_get_srq(dev->mdev,
186 be32_to_cpu(cqe->srqn));
187 srq = to_mibsrq(msrq);
188 } else {
189 srq = to_msrq(qp->ibqp.srq);
190 }
191 if (srq) {
192 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
193 wc->wr_id = srq->wrid[wqe_ctr];
194 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
195 if (msrq && atomic_dec_and_test(&msrq->refcount))
196 complete(&msrq->free);
197 }
198 } else {
199 wq = &qp->rq;
200 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
201 ++wq->tail;
202 }
203 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
204
205 switch (cqe->op_own >> 4) {
206 case MLX5_CQE_RESP_WR_IMM:
207 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
208 wc->wc_flags = IB_WC_WITH_IMM;
209 wc->ex.imm_data = cqe->imm_inval_pkey;
210 break;
211 case MLX5_CQE_RESP_SEND:
212 wc->opcode = IB_WC_RECV;
213 wc->wc_flags = IB_WC_IP_CSUM_OK;
214 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
215 (cqe->hds_ip_ext & CQE_L4_OK))))
216 wc->wc_flags = 0;
217 break;
218 case MLX5_CQE_RESP_SEND_IMM:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_IMM;
221 wc->ex.imm_data = cqe->imm_inval_pkey;
222 break;
223 case MLX5_CQE_RESP_SEND_INV:
224 wc->opcode = IB_WC_RECV;
225 wc->wc_flags = IB_WC_WITH_INVALIDATE;
226 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
227 break;
228 }
229 wc->slid = be16_to_cpu(cqe->slid);
230 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
231 wc->dlid_path_bits = cqe->ml_path;
232 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
233 wc->wc_flags |= g ? IB_WC_GRH : 0;
234 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
235 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
236
237 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
238 &wc->pkey_index);
239 } else {
240 wc->pkey_index = 0;
241 }
242
243 if (ll != IB_LINK_LAYER_ETHERNET) {
244 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
245 return;
246 }
247
248 vlan_present = cqe->l4_l3_hdr_type & 0x1;
249 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
250 if (vlan_present) {
251 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
252 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
253 wc->wc_flags |= IB_WC_WITH_VLAN;
254 } else {
255 wc->sl = 0;
256 }
257
258 switch (roce_packet_type) {
259 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
260 wc->network_hdr_type = RDMA_NETWORK_IB;
261 break;
262 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
263 wc->network_hdr_type = RDMA_NETWORK_IPV6;
264 break;
265 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
266 wc->network_hdr_type = RDMA_NETWORK_IPV4;
267 break;
268 }
269 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
270 }
271
272 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
273 {
274 __be32 *p = (__be32 *)cqe;
275 int i;
276
277 mlx5_ib_warn(dev, "dump error cqe\n");
278 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
279 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
280 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
281 be32_to_cpu(p[3]));
282 }
283
284 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
285 struct mlx5_err_cqe *cqe,
286 struct ib_wc *wc)
287 {
288 int dump = 1;
289
290 switch (cqe->syndrome) {
291 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
292 wc->status = IB_WC_LOC_LEN_ERR;
293 break;
294 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
295 wc->status = IB_WC_LOC_QP_OP_ERR;
296 break;
297 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
298 wc->status = IB_WC_LOC_PROT_ERR;
299 break;
300 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
301 dump = 0;
302 wc->status = IB_WC_WR_FLUSH_ERR;
303 break;
304 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
305 wc->status = IB_WC_MW_BIND_ERR;
306 break;
307 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
308 wc->status = IB_WC_BAD_RESP_ERR;
309 break;
310 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
311 wc->status = IB_WC_LOC_ACCESS_ERR;
312 break;
313 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
314 wc->status = IB_WC_REM_INV_REQ_ERR;
315 break;
316 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
317 wc->status = IB_WC_REM_ACCESS_ERR;
318 break;
319 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
320 wc->status = IB_WC_REM_OP_ERR;
321 break;
322 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
323 wc->status = IB_WC_RETRY_EXC_ERR;
324 dump = 0;
325 break;
326 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
327 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
328 dump = 0;
329 break;
330 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
331 wc->status = IB_WC_REM_ABORT_ERR;
332 break;
333 default:
334 wc->status = IB_WC_GENERAL_ERR;
335 break;
336 }
337
338 wc->vendor_err = cqe->vendor_err_synd;
339 if (dump)
340 dump_cqe(dev, cqe);
341 }
342
343 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
344 {
345 /* TBD: waiting decision
346 */
347 return 0;
348 }
349
350 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
351 {
352 struct mlx5_wqe_data_seg *dpseg;
353 void *addr;
354
355 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
356 sizeof(struct mlx5_wqe_raddr_seg) +
357 sizeof(struct mlx5_wqe_atomic_seg);
358 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
359 return addr;
360 }
361
362 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
363 uint16_t idx)
364 {
365 void *addr;
366 int byte_count;
367 int i;
368
369 if (!is_atomic_response(qp, idx))
370 return;
371
372 byte_count = be32_to_cpu(cqe64->byte_cnt);
373 addr = mlx5_get_atomic_laddr(qp, idx);
374
375 if (byte_count == 4) {
376 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
377 } else {
378 for (i = 0; i < byte_count; i += 8) {
379 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
380 addr += 8;
381 }
382 }
383
384 return;
385 }
386
387 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
388 u16 tail, u16 head)
389 {
390 u16 idx;
391
392 do {
393 idx = tail & (qp->sq.wqe_cnt - 1);
394 handle_atomic(qp, cqe64, idx);
395 if (idx == head)
396 break;
397
398 tail = qp->sq.w_list[idx].next;
399 } while (1);
400 tail = qp->sq.w_list[idx].next;
401 qp->sq.last_poll = tail;
402 }
403
404 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
405 {
406 mlx5_buf_free(dev->mdev, &buf->buf);
407 }
408
409 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
410 struct ib_sig_err *item)
411 {
412 u16 syndrome = be16_to_cpu(cqe->syndrome);
413
414 #define GUARD_ERR (1 << 13)
415 #define APPTAG_ERR (1 << 12)
416 #define REFTAG_ERR (1 << 11)
417
418 if (syndrome & GUARD_ERR) {
419 item->err_type = IB_SIG_BAD_GUARD;
420 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
421 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
422 } else
423 if (syndrome & REFTAG_ERR) {
424 item->err_type = IB_SIG_BAD_REFTAG;
425 item->expected = be32_to_cpu(cqe->expected_reftag);
426 item->actual = be32_to_cpu(cqe->actual_reftag);
427 } else
428 if (syndrome & APPTAG_ERR) {
429 item->err_type = IB_SIG_BAD_APPTAG;
430 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
431 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
432 } else {
433 pr_err("Got signature completion error with bad syndrome %04x\n",
434 syndrome);
435 }
436
437 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
438 item->key = be32_to_cpu(cqe->mkey);
439 }
440
441 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
442 struct ib_wc *wc, int *npolled)
443 {
444 struct mlx5_ib_wq *wq;
445 unsigned int cur;
446 unsigned int idx;
447 int np;
448 int i;
449
450 wq = &qp->sq;
451 cur = wq->head - wq->tail;
452 np = *npolled;
453
454 if (cur == 0)
455 return;
456
457 for (i = 0; i < cur && np < num_entries; i++) {
458 idx = wq->last_poll & (wq->wqe_cnt - 1);
459 wc->wr_id = wq->wrid[idx];
460 wc->status = IB_WC_WR_FLUSH_ERR;
461 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
462 wq->tail++;
463 np++;
464 wc->qp = &qp->ibqp;
465 wc++;
466 wq->last_poll = wq->w_list[idx].next;
467 }
468 *npolled = np;
469 }
470
471 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
472 struct ib_wc *wc, int *npolled)
473 {
474 struct mlx5_ib_wq *wq;
475 unsigned int cur;
476 int np;
477 int i;
478
479 wq = &qp->rq;
480 cur = wq->head - wq->tail;
481 np = *npolled;
482
483 if (cur == 0)
484 return;
485
486 for (i = 0; i < cur && np < num_entries; i++) {
487 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
488 wc->status = IB_WC_WR_FLUSH_ERR;
489 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
490 wq->tail++;
491 np++;
492 wc->qp = &qp->ibqp;
493 wc++;
494 }
495 *npolled = np;
496 }
497
498 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
499 struct ib_wc *wc, int *npolled)
500 {
501 struct mlx5_ib_qp *qp;
502
503 *npolled = 0;
504 /* Find uncompleted WQEs belonging to that cq and return mmics ones */
505 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
506 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
507 if (*npolled >= num_entries)
508 return;
509 }
510
511 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
512 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
513 if (*npolled >= num_entries)
514 return;
515 }
516 }
517
518 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
519 struct mlx5_ib_qp **cur_qp,
520 struct ib_wc *wc)
521 {
522 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
523 struct mlx5_err_cqe *err_cqe;
524 struct mlx5_cqe64 *cqe64;
525 struct mlx5_core_qp *mqp;
526 struct mlx5_ib_wq *wq;
527 struct mlx5_sig_err_cqe *sig_err_cqe;
528 struct mlx5_core_mkey *mmkey;
529 struct mlx5_ib_mr *mr;
530 uint8_t opcode;
531 uint32_t qpn;
532 u16 wqe_ctr;
533 void *cqe;
534 int idx;
535
536 repoll:
537 cqe = next_cqe_sw(cq);
538 if (!cqe)
539 return -EAGAIN;
540
541 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
542
543 ++cq->mcq.cons_index;
544
545 /* Make sure we read CQ entry contents after we've checked the
546 * ownership bit.
547 */
548 rmb();
549
550 opcode = cqe64->op_own >> 4;
551 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
552 if (likely(cq->resize_buf)) {
553 free_cq_buf(dev, &cq->buf);
554 cq->buf = *cq->resize_buf;
555 kfree(cq->resize_buf);
556 cq->resize_buf = NULL;
557 goto repoll;
558 } else {
559 mlx5_ib_warn(dev, "unexpected resize cqe\n");
560 }
561 }
562
563 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
564 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
565 /* We do not have to take the QP table lock here,
566 * because CQs will be locked while QPs are removed
567 * from the table.
568 */
569 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
570 *cur_qp = to_mibqp(mqp);
571 }
572
573 wc->qp = &(*cur_qp)->ibqp;
574 switch (opcode) {
575 case MLX5_CQE_REQ:
576 wq = &(*cur_qp)->sq;
577 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
578 idx = wqe_ctr & (wq->wqe_cnt - 1);
579 handle_good_req(wc, cqe64, wq, idx);
580 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
581 wc->wr_id = wq->wrid[idx];
582 wq->tail = wq->wqe_head[idx] + 1;
583 wc->status = IB_WC_SUCCESS;
584 break;
585 case MLX5_CQE_RESP_WR_IMM:
586 case MLX5_CQE_RESP_SEND:
587 case MLX5_CQE_RESP_SEND_IMM:
588 case MLX5_CQE_RESP_SEND_INV:
589 handle_responder(wc, cqe64, *cur_qp);
590 wc->status = IB_WC_SUCCESS;
591 break;
592 case MLX5_CQE_RESIZE_CQ:
593 break;
594 case MLX5_CQE_REQ_ERR:
595 case MLX5_CQE_RESP_ERR:
596 err_cqe = (struct mlx5_err_cqe *)cqe64;
597 mlx5_handle_error_cqe(dev, err_cqe, wc);
598 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
599 opcode == MLX5_CQE_REQ_ERR ?
600 "Requestor" : "Responder", cq->mcq.cqn);
601 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
602 err_cqe->syndrome, err_cqe->vendor_err_synd);
603 if (opcode == MLX5_CQE_REQ_ERR) {
604 wq = &(*cur_qp)->sq;
605 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
606 idx = wqe_ctr & (wq->wqe_cnt - 1);
607 wc->wr_id = wq->wrid[idx];
608 wq->tail = wq->wqe_head[idx] + 1;
609 } else {
610 struct mlx5_ib_srq *srq;
611
612 if ((*cur_qp)->ibqp.srq) {
613 srq = to_msrq((*cur_qp)->ibqp.srq);
614 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
615 wc->wr_id = srq->wrid[wqe_ctr];
616 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
617 } else {
618 wq = &(*cur_qp)->rq;
619 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
620 ++wq->tail;
621 }
622 }
623 break;
624 case MLX5_CQE_SIG_ERR:
625 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
626
627 read_lock(&dev->mdev->priv.mkey_table.lock);
628 mmkey = __mlx5_mr_lookup(dev->mdev,
629 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
630 mr = to_mibmr(mmkey);
631 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
632 mr->sig->sig_err_exists = true;
633 mr->sig->sigerr_count++;
634
635 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
636 cq->mcq.cqn, mr->sig->err_item.key,
637 mr->sig->err_item.err_type,
638 mr->sig->err_item.sig_err_offset,
639 mr->sig->err_item.expected,
640 mr->sig->err_item.actual);
641
642 read_unlock(&dev->mdev->priv.mkey_table.lock);
643 goto repoll;
644 }
645
646 return 0;
647 }
648
649 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
650 struct ib_wc *wc)
651 {
652 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
653 struct mlx5_ib_wc *soft_wc, *next;
654 int npolled = 0;
655
656 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
657 if (npolled >= num_entries)
658 break;
659
660 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
661 cq->mcq.cqn);
662
663 wc[npolled++] = soft_wc->wc;
664 list_del(&soft_wc->list);
665 kfree(soft_wc);
666 }
667
668 return npolled;
669 }
670
671 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
672 {
673 struct mlx5_ib_cq *cq = to_mcq(ibcq);
674 struct mlx5_ib_qp *cur_qp = NULL;
675 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
676 struct mlx5_core_dev *mdev = dev->mdev;
677 unsigned long flags;
678 int soft_polled = 0;
679 int npolled;
680
681 spin_lock_irqsave(&cq->lock, flags);
682 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
683 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
684 goto out;
685 }
686
687 if (unlikely(!list_empty(&cq->wc_list)))
688 soft_polled = poll_soft_wc(cq, num_entries, wc);
689
690 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
691 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
692 break;
693 }
694
695 if (npolled)
696 mlx5_cq_set_ci(&cq->mcq);
697 out:
698 spin_unlock_irqrestore(&cq->lock, flags);
699
700 return soft_polled + npolled;
701 }
702
703 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
704 {
705 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
706 struct mlx5_ib_cq *cq = to_mcq(ibcq);
707 void __iomem *uar_page = mdev->priv.uar->map;
708 unsigned long irq_flags;
709 int ret = 0;
710
711 spin_lock_irqsave(&cq->lock, irq_flags);
712 if (cq->notify_flags != IB_CQ_NEXT_COMP)
713 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
714
715 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
716 ret = 1;
717 spin_unlock_irqrestore(&cq->lock, irq_flags);
718
719 mlx5_cq_arm(&cq->mcq,
720 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
721 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
722 uar_page, to_mcq(ibcq)->mcq.cons_index);
723
724 return ret;
725 }
726
727 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
728 int nent, int cqe_size)
729 {
730 int err;
731
732 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
733 if (err)
734 return err;
735
736 buf->cqe_size = cqe_size;
737 buf->nent = nent;
738
739 return 0;
740 }
741
742 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
743 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
744 int entries, u32 **cqb,
745 int *cqe_size, int *index, int *inlen)
746 {
747 struct mlx5_ib_create_cq ucmd = {};
748 size_t ucmdlen;
749 int page_shift;
750 __be64 *pas;
751 int npages;
752 int ncont;
753 void *cqc;
754 int err;
755
756 ucmdlen = udata->inlen < sizeof(ucmd) ?
757 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
758
759 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
760 return -EFAULT;
761
762 if (ucmdlen == sizeof(ucmd) &&
763 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
764 return -EINVAL;
765
766 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
767 return -EINVAL;
768
769 *cqe_size = ucmd.cqe_size;
770
771 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
772 entries * ucmd.cqe_size,
773 IB_ACCESS_LOCAL_WRITE, 1);
774 if (IS_ERR(cq->buf.umem)) {
775 err = PTR_ERR(cq->buf.umem);
776 return err;
777 }
778
779 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
780 &cq->db);
781 if (err)
782 goto err_umem;
783
784 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
785 &ncont, NULL);
786 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
787 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
788
789 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
790 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
791 *cqb = kvzalloc(*inlen, GFP_KERNEL);
792 if (!*cqb) {
793 err = -ENOMEM;
794 goto err_db;
795 }
796
797 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
798 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
799
800 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
801 MLX5_SET(cqc, cqc, log_page_size,
802 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
803
804 *index = to_mucontext(context)->bfregi.sys_pages[0];
805
806 if (ucmd.cqe_comp_en == 1) {
807 if (!((*cqe_size == 128 &&
808 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
809 (*cqe_size == 64 &&
810 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
811 err = -EOPNOTSUPP;
812 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
813 *cqe_size);
814 goto err_cqb;
815 }
816
817 if (unlikely(!ucmd.cqe_comp_res_format ||
818 !(ucmd.cqe_comp_res_format <
819 MLX5_IB_CQE_RES_RESERVED) ||
820 (ucmd.cqe_comp_res_format &
821 (ucmd.cqe_comp_res_format - 1)))) {
822 err = -EOPNOTSUPP;
823 mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n",
824 ucmd.cqe_comp_res_format);
825 goto err_cqb;
826 }
827
828 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
829 MLX5_SET(cqc, cqc, mini_cqe_res_format,
830 ilog2(ucmd.cqe_comp_res_format));
831 }
832
833 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
834 if (*cqe_size != 128 ||
835 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
836 err = -EOPNOTSUPP;
837 mlx5_ib_warn(dev,
838 "CQE padding is not supported for CQE size of %dB!\n",
839 *cqe_size);
840 goto err_cqb;
841 }
842
843 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
844 }
845
846 return 0;
847
848 err_cqb:
849 kfree(*cqb);
850
851 err_db:
852 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
853
854 err_umem:
855 ib_umem_release(cq->buf.umem);
856 return err;
857 }
858
859 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
860 {
861 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
862 ib_umem_release(cq->buf.umem);
863 }
864
865 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
866 {
867 int i;
868 void *cqe;
869 struct mlx5_cqe64 *cqe64;
870
871 for (i = 0; i < buf->nent; i++) {
872 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
873 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
874 cqe64->op_own = MLX5_CQE_INVALID << 4;
875 }
876 }
877
878 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
879 int entries, int cqe_size,
880 u32 **cqb, int *index, int *inlen)
881 {
882 __be64 *pas;
883 void *cqc;
884 int err;
885
886 err = mlx5_db_alloc(dev->mdev, &cq->db);
887 if (err)
888 return err;
889
890 cq->mcq.set_ci_db = cq->db.db;
891 cq->mcq.arm_db = cq->db.db + 1;
892 cq->mcq.cqe_sz = cqe_size;
893
894 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
895 if (err)
896 goto err_db;
897
898 init_cq_buf(cq, &cq->buf);
899
900 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
901 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages;
902 *cqb = kvzalloc(*inlen, GFP_KERNEL);
903 if (!*cqb) {
904 err = -ENOMEM;
905 goto err_buf;
906 }
907
908 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
909 mlx5_fill_page_array(&cq->buf.buf, pas);
910
911 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
912 MLX5_SET(cqc, cqc, log_page_size,
913 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
914
915 *index = dev->mdev->priv.uar->index;
916
917 return 0;
918
919 err_buf:
920 free_cq_buf(dev, &cq->buf);
921
922 err_db:
923 mlx5_db_free(dev->mdev, &cq->db);
924 return err;
925 }
926
927 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
928 {
929 free_cq_buf(dev, &cq->buf);
930 mlx5_db_free(dev->mdev, &cq->db);
931 }
932
933 static void notify_soft_wc_handler(struct work_struct *work)
934 {
935 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
936 notify_work);
937
938 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
939 }
940
941 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
942 const struct ib_cq_init_attr *attr,
943 struct ib_ucontext *context,
944 struct ib_udata *udata)
945 {
946 int entries = attr->cqe;
947 int vector = attr->comp_vector;
948 struct mlx5_ib_dev *dev = to_mdev(ibdev);
949 struct mlx5_ib_cq *cq;
950 int uninitialized_var(index);
951 int uninitialized_var(inlen);
952 u32 *cqb = NULL;
953 void *cqc;
954 int cqe_size;
955 unsigned int irqn;
956 int eqn;
957 int err;
958
959 if (entries < 0 ||
960 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
961 return ERR_PTR(-EINVAL);
962
963 if (check_cq_create_flags(attr->flags))
964 return ERR_PTR(-EOPNOTSUPP);
965
966 entries = roundup_pow_of_two(entries + 1);
967 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
968 return ERR_PTR(-EINVAL);
969
970 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
971 if (!cq)
972 return ERR_PTR(-ENOMEM);
973
974 cq->ibcq.cqe = entries - 1;
975 mutex_init(&cq->resize_mutex);
976 spin_lock_init(&cq->lock);
977 cq->resize_buf = NULL;
978 cq->resize_umem = NULL;
979 cq->create_flags = attr->flags;
980 INIT_LIST_HEAD(&cq->list_send_qp);
981 INIT_LIST_HEAD(&cq->list_recv_qp);
982
983 if (context) {
984 err = create_cq_user(dev, udata, context, cq, entries,
985 &cqb, &cqe_size, &index, &inlen);
986 if (err)
987 goto err_create;
988 } else {
989 cqe_size = cache_line_size() == 128 ? 128 : 64;
990 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
991 &index, &inlen);
992 if (err)
993 goto err_create;
994
995 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
996 }
997
998 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
999 if (err)
1000 goto err_cqb;
1001
1002 cq->cqe_size = cqe_size;
1003
1004 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
1005 MLX5_SET(cqc, cqc, cqe_sz,
1006 cqe_sz_to_mlx_sz(cqe_size,
1007 cq->private_flags &
1008 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1009 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1010 MLX5_SET(cqc, cqc, uar_page, index);
1011 MLX5_SET(cqc, cqc, c_eqn, eqn);
1012 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1013 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
1014 MLX5_SET(cqc, cqc, oi, 1);
1015
1016 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
1017 if (err)
1018 goto err_cqb;
1019
1020 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1021 cq->mcq.irqn = irqn;
1022 if (context)
1023 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1024 else
1025 cq->mcq.comp = mlx5_ib_cq_comp;
1026 cq->mcq.event = mlx5_ib_cq_event;
1027
1028 INIT_LIST_HEAD(&cq->wc_list);
1029
1030 if (context)
1031 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1032 err = -EFAULT;
1033 goto err_cmd;
1034 }
1035
1036
1037 kvfree(cqb);
1038 return &cq->ibcq;
1039
1040 err_cmd:
1041 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1042
1043 err_cqb:
1044 kvfree(cqb);
1045 if (context)
1046 destroy_cq_user(cq, context);
1047 else
1048 destroy_cq_kernel(dev, cq);
1049
1050 err_create:
1051 kfree(cq);
1052
1053 return ERR_PTR(err);
1054 }
1055
1056
1057 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1058 {
1059 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1060 struct mlx5_ib_cq *mcq = to_mcq(cq);
1061 struct ib_ucontext *context = NULL;
1062
1063 if (cq->uobject)
1064 context = cq->uobject->context;
1065
1066 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1067 if (context)
1068 destroy_cq_user(mcq, context);
1069 else
1070 destroy_cq_kernel(dev, mcq);
1071
1072 kfree(mcq);
1073
1074 return 0;
1075 }
1076
1077 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1078 {
1079 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1080 }
1081
1082 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1083 {
1084 struct mlx5_cqe64 *cqe64, *dest64;
1085 void *cqe, *dest;
1086 u32 prod_index;
1087 int nfreed = 0;
1088 u8 owner_bit;
1089
1090 if (!cq)
1091 return;
1092
1093 /* First we need to find the current producer index, so we
1094 * know where to start cleaning from. It doesn't matter if HW
1095 * adds new entries after this loop -- the QP we're worried
1096 * about is already in RESET, so the new entries won't come
1097 * from our QP and therefore don't need to be checked.
1098 */
1099 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1100 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1101 break;
1102
1103 /* Now sweep backwards through the CQ, removing CQ entries
1104 * that match our QP by copying older entries on top of them.
1105 */
1106 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1107 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1108 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1109 if (is_equal_rsn(cqe64, rsn)) {
1110 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1111 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1112 ++nfreed;
1113 } else if (nfreed) {
1114 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1115 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1116 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1117 memcpy(dest, cqe, cq->mcq.cqe_sz);
1118 dest64->op_own = owner_bit |
1119 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1120 }
1121 }
1122
1123 if (nfreed) {
1124 cq->mcq.cons_index += nfreed;
1125 /* Make sure update of buffer contents is done before
1126 * updating consumer index.
1127 */
1128 wmb();
1129 mlx5_cq_set_ci(&cq->mcq);
1130 }
1131 }
1132
1133 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1134 {
1135 if (!cq)
1136 return;
1137
1138 spin_lock_irq(&cq->lock);
1139 __mlx5_ib_cq_clean(cq, qpn, srq);
1140 spin_unlock_irq(&cq->lock);
1141 }
1142
1143 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1144 {
1145 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1146 struct mlx5_ib_cq *mcq = to_mcq(cq);
1147 int err;
1148
1149 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1150 return -ENOSYS;
1151
1152 if (cq_period > MLX5_MAX_CQ_PERIOD)
1153 return -EINVAL;
1154
1155 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1156 cq_period, cq_count);
1157 if (err)
1158 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1159
1160 return err;
1161 }
1162
1163 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1164 int entries, struct ib_udata *udata, int *npas,
1165 int *page_shift, int *cqe_size)
1166 {
1167 struct mlx5_ib_resize_cq ucmd;
1168 struct ib_umem *umem;
1169 int err;
1170 int npages;
1171 struct ib_ucontext *context = cq->buf.umem->context;
1172
1173 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1174 if (err)
1175 return err;
1176
1177 if (ucmd.reserved0 || ucmd.reserved1)
1178 return -EINVAL;
1179
1180 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1181 IB_ACCESS_LOCAL_WRITE, 1);
1182 if (IS_ERR(umem)) {
1183 err = PTR_ERR(umem);
1184 return err;
1185 }
1186
1187 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1188 npas, NULL);
1189
1190 cq->resize_umem = umem;
1191 *cqe_size = ucmd.cqe_size;
1192
1193 return 0;
1194 }
1195
1196 static void un_resize_user(struct mlx5_ib_cq *cq)
1197 {
1198 ib_umem_release(cq->resize_umem);
1199 }
1200
1201 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1202 int entries, int cqe_size)
1203 {
1204 int err;
1205
1206 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1207 if (!cq->resize_buf)
1208 return -ENOMEM;
1209
1210 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1211 if (err)
1212 goto ex;
1213
1214 init_cq_buf(cq, cq->resize_buf);
1215
1216 return 0;
1217
1218 ex:
1219 kfree(cq->resize_buf);
1220 return err;
1221 }
1222
1223 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1224 {
1225 free_cq_buf(dev, cq->resize_buf);
1226 cq->resize_buf = NULL;
1227 }
1228
1229 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1230 {
1231 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1232 struct mlx5_cqe64 *scqe64;
1233 struct mlx5_cqe64 *dcqe64;
1234 void *start_cqe;
1235 void *scqe;
1236 void *dcqe;
1237 int ssize;
1238 int dsize;
1239 int i;
1240 u8 sw_own;
1241
1242 ssize = cq->buf.cqe_size;
1243 dsize = cq->resize_buf->cqe_size;
1244 if (ssize != dsize) {
1245 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1246 return -EINVAL;
1247 }
1248
1249 i = cq->mcq.cons_index;
1250 scqe = get_sw_cqe(cq, i);
1251 scqe64 = ssize == 64 ? scqe : scqe + 64;
1252 start_cqe = scqe;
1253 if (!scqe) {
1254 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1255 return -EINVAL;
1256 }
1257
1258 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1259 dcqe = get_cqe_from_buf(cq->resize_buf,
1260 (i + 1) & (cq->resize_buf->nent),
1261 dsize);
1262 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1263 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1264 memcpy(dcqe, scqe, dsize);
1265 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1266
1267 ++i;
1268 scqe = get_sw_cqe(cq, i);
1269 scqe64 = ssize == 64 ? scqe : scqe + 64;
1270 if (!scqe) {
1271 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1272 return -EINVAL;
1273 }
1274
1275 if (scqe == start_cqe) {
1276 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1277 cq->mcq.cqn);
1278 return -ENOMEM;
1279 }
1280 }
1281 ++cq->mcq.cons_index;
1282 return 0;
1283 }
1284
1285 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1286 {
1287 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1288 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1289 void *cqc;
1290 u32 *in;
1291 int err;
1292 int npas;
1293 __be64 *pas;
1294 int page_shift;
1295 int inlen;
1296 int uninitialized_var(cqe_size);
1297 unsigned long flags;
1298
1299 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1300 pr_info("Firmware does not support resize CQ\n");
1301 return -ENOSYS;
1302 }
1303
1304 if (entries < 1 ||
1305 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1306 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1307 entries,
1308 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1309 return -EINVAL;
1310 }
1311
1312 entries = roundup_pow_of_two(entries + 1);
1313 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1314 return -EINVAL;
1315
1316 if (entries == ibcq->cqe + 1)
1317 return 0;
1318
1319 mutex_lock(&cq->resize_mutex);
1320 if (udata) {
1321 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1322 &cqe_size);
1323 } else {
1324 cqe_size = 64;
1325 err = resize_kernel(dev, cq, entries, cqe_size);
1326 if (!err) {
1327 npas = cq->resize_buf->buf.npages;
1328 page_shift = cq->resize_buf->buf.page_shift;
1329 }
1330 }
1331
1332 if (err)
1333 goto ex;
1334
1335 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1336 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1337
1338 in = kvzalloc(inlen, GFP_KERNEL);
1339 if (!in) {
1340 err = -ENOMEM;
1341 goto ex_resize;
1342 }
1343
1344 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1345 if (udata)
1346 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1347 pas, 0);
1348 else
1349 mlx5_fill_page_array(&cq->resize_buf->buf, pas);
1350
1351 MLX5_SET(modify_cq_in, in,
1352 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1353 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1354 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1355 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1356
1357 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1358
1359 MLX5_SET(cqc, cqc, log_page_size,
1360 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1361 MLX5_SET(cqc, cqc, cqe_sz,
1362 cqe_sz_to_mlx_sz(cqe_size,
1363 cq->private_flags &
1364 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1365 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1366
1367 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1368 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1369
1370 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1371 if (err)
1372 goto ex_alloc;
1373
1374 if (udata) {
1375 cq->ibcq.cqe = entries - 1;
1376 ib_umem_release(cq->buf.umem);
1377 cq->buf.umem = cq->resize_umem;
1378 cq->resize_umem = NULL;
1379 } else {
1380 struct mlx5_ib_cq_buf tbuf;
1381 int resized = 0;
1382
1383 spin_lock_irqsave(&cq->lock, flags);
1384 if (cq->resize_buf) {
1385 err = copy_resize_cqes(cq);
1386 if (!err) {
1387 tbuf = cq->buf;
1388 cq->buf = *cq->resize_buf;
1389 kfree(cq->resize_buf);
1390 cq->resize_buf = NULL;
1391 resized = 1;
1392 }
1393 }
1394 cq->ibcq.cqe = entries - 1;
1395 spin_unlock_irqrestore(&cq->lock, flags);
1396 if (resized)
1397 free_cq_buf(dev, &tbuf);
1398 }
1399 mutex_unlock(&cq->resize_mutex);
1400
1401 kvfree(in);
1402 return 0;
1403
1404 ex_alloc:
1405 kvfree(in);
1406
1407 ex_resize:
1408 if (udata)
1409 un_resize_user(cq);
1410 else
1411 un_resize_kernel(dev, cq);
1412 ex:
1413 mutex_unlock(&cq->resize_mutex);
1414 return err;
1415 }
1416
1417 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1418 {
1419 struct mlx5_ib_cq *cq;
1420
1421 if (!ibcq)
1422 return 128;
1423
1424 cq = to_mcq(ibcq);
1425 return cq->cqe_size;
1426 }
1427
1428 /* Called from atomic context */
1429 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1430 {
1431 struct mlx5_ib_wc *soft_wc;
1432 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1433 unsigned long flags;
1434
1435 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1436 if (!soft_wc)
1437 return -ENOMEM;
1438
1439 soft_wc->wc = *wc;
1440 spin_lock_irqsave(&cq->lock, flags);
1441 list_add_tail(&soft_wc->list, &cq->wc_list);
1442 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1443 wc->status != IB_WC_SUCCESS) {
1444 cq->notify_flags = 0;
1445 schedule_work(&cq->notify_work);
1446 }
1447 spin_unlock_irqrestore(&cq->lock, flags);
1448
1449 return 0;
1450 }
CRIS linux kernel tree