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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / infiniband / hw / nes / nes_hw.c
blob18a7de1c3923e8ac1a515517494b5e4411f60c46
1 /*
2 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
39 #include <linux/slab.h>
40
41 #include "nes.h"
42
43 static int wide_ppm_offset;
44 module_param(wide_ppm_offset, int, 0644);
45 MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
46
47 static u32 crit_err_count;
48 u32 int_mod_timer_init;
49 u32 int_mod_cq_depth_256;
50 u32 int_mod_cq_depth_128;
51 u32 int_mod_cq_depth_32;
52 u32 int_mod_cq_depth_24;
53 u32 int_mod_cq_depth_16;
54 u32 int_mod_cq_depth_4;
55 u32 int_mod_cq_depth_1;
56 static const u8 nes_max_critical_error_count = 100;
57 #include "nes_cm.h"
58
59 static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq);
60 static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count);
61 static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
62 struct nes_adapter *nesadapter, u8 OneG_Mode);
63 static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
64 static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq);
65 static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq);
66 static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
67 struct nes_hw_aeqe *aeqe);
68 static void process_critical_error(struct nes_device *nesdev);
69 static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number);
70 static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode);
71 static void nes_terminate_start_timer(struct nes_qp *nesqp);
72
73 #ifdef CONFIG_INFINIBAND_NES_DEBUG
74 static unsigned char *nes_iwarp_state_str[] = {
75 "Non-Existent",
76 "Idle",
77 "RTS",
78 "Closing",
79 "RSVD1",
80 "Terminate",
81 "Error",
82 "RSVD2",
83 };
84
85 static unsigned char *nes_tcp_state_str[] = {
86 "Non-Existent",
87 "Closed",
88 "Listen",
89 "SYN Sent",
90 "SYN Rcvd",
91 "Established",
92 "Close Wait",
93 "FIN Wait 1",
94 "Closing",
95 "Last Ack",
96 "FIN Wait 2",
97 "Time Wait",
98 "RSVD1",
99 "RSVD2",
100 "RSVD3",
101 "RSVD4",
102 };
103 #endif
104
105 static inline void print_ip(struct nes_cm_node *cm_node)
106 {
107 unsigned char *rem_addr;
108 if (cm_node) {
109 rem_addr = (unsigned char *)&cm_node->rem_addr;
110 printk(KERN_ERR PFX "Remote IP addr: %pI4\n", rem_addr);
111 }
112 }
113
114 /**
115 * nes_nic_init_timer_defaults
116 */
117 void nes_nic_init_timer_defaults(struct nes_device *nesdev, u8 jumbomode)
118 {
119 unsigned long flags;
120 struct nes_adapter *nesadapter = nesdev->nesadapter;
121 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
122
123 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
124
125 shared_timer->timer_in_use_min = NES_NIC_FAST_TIMER_LOW;
126 shared_timer->timer_in_use_max = NES_NIC_FAST_TIMER_HIGH;
127 if (jumbomode) {
128 shared_timer->threshold_low = DEFAULT_JUMBO_NES_QL_LOW;
129 shared_timer->threshold_target = DEFAULT_JUMBO_NES_QL_TARGET;
130 shared_timer->threshold_high = DEFAULT_JUMBO_NES_QL_HIGH;
131 } else {
132 shared_timer->threshold_low = DEFAULT_NES_QL_LOW;
133 shared_timer->threshold_target = DEFAULT_NES_QL_TARGET;
134 shared_timer->threshold_high = DEFAULT_NES_QL_HIGH;
135 }
136
137 /* todo use netdev->mtu to set thresholds */
138 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
139 }
140
141
142 /**
143 * nes_nic_init_timer
144 */
145 static void nes_nic_init_timer(struct nes_device *nesdev)
146 {
147 unsigned long flags;
148 struct nes_adapter *nesadapter = nesdev->nesadapter;
149 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
150
151 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
152
153 if (shared_timer->timer_in_use_old == 0) {
154 nesdev->deepcq_count = 0;
155 shared_timer->timer_direction_upward = 0;
156 shared_timer->timer_direction_downward = 0;
157 shared_timer->timer_in_use = NES_NIC_FAST_TIMER;
158 shared_timer->timer_in_use_old = 0;
159
160 }
161 if (shared_timer->timer_in_use != shared_timer->timer_in_use_old) {
162 shared_timer->timer_in_use_old = shared_timer->timer_in_use;
163 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
164 0x80000000 | ((u32)(shared_timer->timer_in_use*8)));
165 }
166 /* todo use netdev->mtu to set thresholds */
167 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
168 }
169
170
171 /**
172 * nes_nic_tune_timer
173 */
174 static void nes_nic_tune_timer(struct nes_device *nesdev)
175 {
176 unsigned long flags;
177 struct nes_adapter *nesadapter = nesdev->nesadapter;
178 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
179 u16 cq_count = nesdev->currcq_count;
180
181 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
182
183 if (shared_timer->cq_count_old <= cq_count)
184 shared_timer->cq_direction_downward = 0;
185 else
186 shared_timer->cq_direction_downward++;
187 shared_timer->cq_count_old = cq_count;
188 if (shared_timer->cq_direction_downward > NES_NIC_CQ_DOWNWARD_TREND) {
189 if (cq_count <= shared_timer->threshold_low &&
190 shared_timer->threshold_low > 4) {
191 shared_timer->threshold_low = shared_timer->threshold_low/2;
192 shared_timer->cq_direction_downward=0;
193 nesdev->currcq_count = 0;
194 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
195 return;
196 }
197 }
198
199 if (cq_count > 1) {
200 nesdev->deepcq_count += cq_count;
201 if (cq_count <= shared_timer->threshold_low) { /* increase timer gently */
202 shared_timer->timer_direction_upward++;
203 shared_timer->timer_direction_downward = 0;
204 } else if (cq_count <= shared_timer->threshold_target) { /* balanced */
205 shared_timer->timer_direction_upward = 0;
206 shared_timer->timer_direction_downward = 0;
207 } else if (cq_count <= shared_timer->threshold_high) { /* decrease timer gently */
208 shared_timer->timer_direction_downward++;
209 shared_timer->timer_direction_upward = 0;
210 } else if (cq_count <= (shared_timer->threshold_high) * 2) {
211 shared_timer->timer_in_use -= 2;
212 shared_timer->timer_direction_upward = 0;
213 shared_timer->timer_direction_downward++;
214 } else {
215 shared_timer->timer_in_use -= 4;
216 shared_timer->timer_direction_upward = 0;
217 shared_timer->timer_direction_downward++;
218 }
219
220 if (shared_timer->timer_direction_upward > 3 ) { /* using history */
221 shared_timer->timer_in_use += 3;
222 shared_timer->timer_direction_upward = 0;
223 shared_timer->timer_direction_downward = 0;
224 }
225 if (shared_timer->timer_direction_downward > 5) { /* using history */
226 shared_timer->timer_in_use -= 4 ;
227 shared_timer->timer_direction_downward = 0;
228 shared_timer->timer_direction_upward = 0;
229 }
230 }
231
232 /* boundary checking */
233 if (shared_timer->timer_in_use > shared_timer->threshold_high)
234 shared_timer->timer_in_use = shared_timer->threshold_high;
235 else if (shared_timer->timer_in_use < shared_timer->threshold_low)
236 shared_timer->timer_in_use = shared_timer->threshold_low;
237
238 nesdev->currcq_count = 0;
239
240 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
241 }
242
243
244 /**
245 * nes_init_adapter - initialize adapter
246 */
247 struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
248 struct nes_adapter *nesadapter = NULL;
249 unsigned long num_pds;
250 u32 u32temp;
251 u32 port_count;
252 u16 max_rq_wrs;
253 u16 max_sq_wrs;
254 u32 max_mr;
255 u32 max_256pbl;
256 u32 max_4kpbl;
257 u32 max_qp;
258 u32 max_irrq;
259 u32 max_cq;
260 u32 hte_index_mask;
261 u32 adapter_size;
262 u32 arp_table_size;
263 u16 vendor_id;
264 u16 device_id;
265 u8 OneG_Mode;
266 u8 func_index;
267
268 /* search the list of existing adapters */
269 list_for_each_entry(nesadapter, &nes_adapter_list, list) {
270 nes_debug(NES_DBG_INIT, "Searching Adapter list for PCI devfn = 0x%X,"
271 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
272 nesdev->pcidev->devfn,
273 PCI_SLOT(nesadapter->devfn),
274 nesadapter->bus_number,
275 PCI_SLOT(nesdev->pcidev->devfn),
276 nesdev->pcidev->bus->number );
277 if ((PCI_SLOT(nesadapter->devfn) == PCI_SLOT(nesdev->pcidev->devfn)) &&
278 (nesadapter->bus_number == nesdev->pcidev->bus->number)) {
279 nesadapter->ref_count++;
280 return nesadapter;
281 }
282 }
283
284 /* no adapter found */
285 num_pds = pci_resource_len(nesdev->pcidev, BAR_1) >> PAGE_SHIFT;
286 if ((hw_rev != NE020_REV) && (hw_rev != NE020_REV1)) {
287 nes_debug(NES_DBG_INIT, "NE020 driver detected unknown hardware revision 0x%x\n",
288 hw_rev);
289 return NULL;
290 }
291
292 nes_debug(NES_DBG_INIT, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
293 nes_read_indexed(nesdev, NES_IDX_QP_CONTROL + PCI_FUNC(nesdev->pcidev->devfn) * 8),
294 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS),
295 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 4),
296 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 8));
297
298 nes_debug(NES_DBG_INIT, "Reset and init NE020\n");
299
300
301 if ((port_count = nes_reset_adapter_ne020(nesdev, &OneG_Mode)) == 0)
302 return NULL;
303
304 max_qp = nes_read_indexed(nesdev, NES_IDX_QP_CTX_SIZE);
305 nes_debug(NES_DBG_INIT, "QP_CTX_SIZE=%u\n", max_qp);
306
307 u32temp = nes_read_indexed(nesdev, NES_IDX_QUAD_HASH_TABLE_SIZE);
308 if (max_qp > ((u32)1 << (u32temp & 0x001f))) {
309 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
310 max_qp, u32temp);
311 max_qp = (u32)1 << (u32temp & 0x001f);
312 }
313
314 hte_index_mask = ((u32)1 << ((u32temp & 0x001f)+1))-1;
315 nes_debug(NES_DBG_INIT, "Max QP = %u, hte_index_mask = 0x%08X.\n",
316 max_qp, hte_index_mask);
317
318 u32temp = nes_read_indexed(nesdev, NES_IDX_IRRQ_COUNT);
319
320 max_irrq = 1 << (u32temp & 0x001f);
321
322 if (max_qp > max_irrq) {
323 max_qp = max_irrq;
324 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to Available Q1s.\n",
325 max_qp);
326 }
327
328 /* there should be no reason to allocate more pds than qps */
329 if (num_pds > max_qp)
330 num_pds = max_qp;
331
332 u32temp = nes_read_indexed(nesdev, NES_IDX_MRT_SIZE);
333 max_mr = (u32)8192 << (u32temp & 0x7);
334
335 u32temp = nes_read_indexed(nesdev, NES_IDX_PBL_REGION_SIZE);
336 max_256pbl = (u32)1 << (u32temp & 0x0000001f);
337 max_4kpbl = (u32)1 << ((u32temp >> 16) & 0x0000001f);
338 max_cq = nes_read_indexed(nesdev, NES_IDX_CQ_CTX_SIZE);
339
340 u32temp = nes_read_indexed(nesdev, NES_IDX_ARP_CACHE_SIZE);
341 arp_table_size = 1 << u32temp;
342
343 adapter_size = (sizeof(struct nes_adapter) +
344 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
345 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
346 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
347 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
348 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
349 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
350 adapter_size += sizeof(struct nes_qp **) * max_qp;
351
352 /* allocate a new adapter struct */
353 nesadapter = kzalloc(adapter_size, GFP_KERNEL);
354 if (!nesadapter)
355 return NULL;
356
357 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
358 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
359
360 if (nes_read_eeprom_values(nesdev, nesadapter)) {
361 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
362 kfree(nesadapter);
363 return NULL;
364 }
365
366 nesadapter->vendor_id = (((u32) nesadapter->mac_addr_high) << 8) |
367 (nesadapter->mac_addr_low >> 24);
368
369 pci_bus_read_config_word(nesdev->pcidev->bus, nesdev->pcidev->devfn,
370 PCI_DEVICE_ID, &device_id);
371 nesadapter->vendor_part_id = device_id;
372
373 if (nes_init_serdes(nesdev, hw_rev, port_count, nesadapter,
374 OneG_Mode)) {
375 kfree(nesadapter);
376 return NULL;
377 }
378 nes_init_csr_ne020(nesdev, hw_rev, port_count);
379
380 memset(nesadapter->pft_mcast_map, 255,
381 sizeof nesadapter->pft_mcast_map);
382
383 /* populate the new nesadapter */
384 nesadapter->nesdev = nesdev;
385 nesadapter->devfn = nesdev->pcidev->devfn;
386 nesadapter->bus_number = nesdev->pcidev->bus->number;
387 nesadapter->ref_count = 1;
388 nesadapter->timer_int_req = 0xffff0000;
389 nesadapter->OneG_Mode = OneG_Mode;
390 nesadapter->doorbell_start = nesdev->doorbell_region;
391
392 /* nesadapter->tick_delta = clk_divisor; */
393 nesadapter->hw_rev = hw_rev;
394 nesadapter->port_count = port_count;
395
396 nesadapter->max_qp = max_qp;
397 nesadapter->hte_index_mask = hte_index_mask;
398 nesadapter->max_irrq = max_irrq;
399 nesadapter->max_mr = max_mr;
400 nesadapter->max_256pbl = max_256pbl - 1;
401 nesadapter->max_4kpbl = max_4kpbl - 1;
402 nesadapter->max_cq = max_cq;
403 nesadapter->free_256pbl = max_256pbl - 1;
404 nesadapter->free_4kpbl = max_4kpbl - 1;
405 nesadapter->max_pd = num_pds;
406 nesadapter->arp_table_size = arp_table_size;
407
408 nesadapter->et_pkt_rate_low = NES_TIMER_ENABLE_LIMIT;
409 if (nes_drv_opt & NES_DRV_OPT_DISABLE_INT_MOD) {
410 nesadapter->et_use_adaptive_rx_coalesce = 0;
411 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
412 nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
413 } else {
414 nesadapter->et_use_adaptive_rx_coalesce = 1;
415 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
416 nesadapter->et_rx_coalesce_usecs_irq = 0;
417 printk(PFX "%s: Using Adaptive Interrupt Moderation\n", __func__);
418 }
419 /* Setup and enable the periodic timer */
420 if (nesadapter->et_rx_coalesce_usecs_irq)
421 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
422 ((u32)(nesadapter->et_rx_coalesce_usecs_irq * 8)));
423 else
424 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
425
426 nesadapter->base_pd = 1;
427
428 nesadapter->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
429 IB_DEVICE_MEM_WINDOW |
430 IB_DEVICE_MEM_MGT_EXTENSIONS;
431
432 nesadapter->allocated_qps = (unsigned long *)&(((unsigned char *)nesadapter)
433 [(sizeof(struct nes_adapter)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
434 nesadapter->allocated_cqs = &nesadapter->allocated_qps[BITS_TO_LONGS(max_qp)];
435 nesadapter->allocated_mrs = &nesadapter->allocated_cqs[BITS_TO_LONGS(max_cq)];
436 nesadapter->allocated_pds = &nesadapter->allocated_mrs[BITS_TO_LONGS(max_mr)];
437 nesadapter->allocated_arps = &nesadapter->allocated_pds[BITS_TO_LONGS(num_pds)];
438 nesadapter->qp_table = (struct nes_qp **)(&nesadapter->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
439
440
441 /* mark the usual suspect QPs, MR and CQs as in use */
442 for (u32temp = 0; u32temp < NES_FIRST_QPN; u32temp++) {
443 set_bit(u32temp, nesadapter->allocated_qps);
444 set_bit(u32temp, nesadapter->allocated_cqs);
445 }
446 set_bit(0, nesadapter->allocated_mrs);
447
448 for (u32temp = 0; u32temp < 20; u32temp++)
449 set_bit(u32temp, nesadapter->allocated_pds);
450 u32temp = nes_read_indexed(nesdev, NES_IDX_QP_MAX_CFG_SIZES);
451
452 max_rq_wrs = ((u32temp >> 8) & 3);
453 switch (max_rq_wrs) {
454 case 0:
455 max_rq_wrs = 4;
456 break;
457 case 1:
458 max_rq_wrs = 16;
459 break;
460 case 2:
461 max_rq_wrs = 32;
462 break;
463 case 3:
464 max_rq_wrs = 512;
465 break;
466 }
467
468 max_sq_wrs = (u32temp & 3);
469 switch (max_sq_wrs) {
470 case 0:
471 max_sq_wrs = 4;
472 break;
473 case 1:
474 max_sq_wrs = 16;
475 break;
476 case 2:
477 max_sq_wrs = 32;
478 break;
479 case 3:
480 max_sq_wrs = 512;
481 break;
482 }
483 nesadapter->max_qp_wr = min(max_rq_wrs, max_sq_wrs);
484 nesadapter->max_irrq_wr = (u32temp >> 16) & 3;
485
486 nesadapter->max_sge = 4;
487 nesadapter->max_cqe = 32766;
488
489 if (nes_read_eeprom_values(nesdev, nesadapter)) {
490 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
491 kfree(nesadapter);
492 return NULL;
493 }
494
495 u32temp = nes_read_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG);
496 nes_write_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG,
497 (u32temp & 0xff000000) | (nesadapter->tcp_timer_core_clk_divisor & 0x00ffffff));
498
499 /* setup port configuration */
500 if (nesadapter->port_count == 1) {
501 nesadapter->log_port = 0x00000000;
502 if (nes_drv_opt & NES_DRV_OPT_DUAL_LOGICAL_PORT)
503 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000002);
504 else
505 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
506 } else {
507 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
508 nesadapter->log_port = 0x000000D8;
509 } else {
510 if (nesadapter->port_count == 2)
511 nesadapter->log_port = 0x00000044;
512 else
513 nesadapter->log_port = 0x000000e4;
514 }
515 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
516 }
517
518 nes_write_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT,
519 nesadapter->log_port);
520 nes_debug(NES_DBG_INIT, "Probe time, LOG2PHY=%u\n",
521 nes_read_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT));
522
523 spin_lock_init(&nesadapter->resource_lock);
524 spin_lock_init(&nesadapter->phy_lock);
525 spin_lock_init(&nesadapter->pbl_lock);
526 spin_lock_init(&nesadapter->periodic_timer_lock);
527
528 INIT_LIST_HEAD(&nesadapter->nesvnic_list[0]);
529 INIT_LIST_HEAD(&nesadapter->nesvnic_list[1]);
530 INIT_LIST_HEAD(&nesadapter->nesvnic_list[2]);
531 INIT_LIST_HEAD(&nesadapter->nesvnic_list[3]);
532
533 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
534 u32 pcs_control_status0, pcs_control_status1;
535 u32 reset_value;
536 u32 i = 0;
537 u32 int_cnt = 0;
538 u32 ext_cnt = 0;
539 unsigned long flags;
540 u32 j = 0;
541
542 pcs_control_status0 = nes_read_indexed(nesdev,
543 NES_IDX_PHY_PCS_CONTROL_STATUS0);
544 pcs_control_status1 = nes_read_indexed(nesdev,
545 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
546
547 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
548 pcs_control_status0 = nes_read_indexed(nesdev,
549 NES_IDX_PHY_PCS_CONTROL_STATUS0);
550 pcs_control_status1 = nes_read_indexed(nesdev,
551 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
552 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
553 || (0x0F000100 == (pcs_control_status1 & 0x0F000100)))
554 int_cnt++;
555 usleep_range(1000, 2000);
556 }
557 if (int_cnt > 1) {
558 spin_lock_irqsave(&nesadapter->phy_lock, flags);
559 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
560 mh_detected++;
561 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
562 reset_value |= 0x0000003d;
563 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
564
565 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
566 & 0x00000040) != 0x00000040) && (j++ < 5000));
567 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
568
569 pcs_control_status0 = nes_read_indexed(nesdev,
570 NES_IDX_PHY_PCS_CONTROL_STATUS0);
571 pcs_control_status1 = nes_read_indexed(nesdev,
572 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
573
574 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
575 pcs_control_status0 = nes_read_indexed(nesdev,
576 NES_IDX_PHY_PCS_CONTROL_STATUS0);
577 pcs_control_status1 = nes_read_indexed(nesdev,
578 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
579 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
580 || (0x0F000100 == (pcs_control_status1 & 0x0F000100))) {
581 if (++ext_cnt > int_cnt) {
582 spin_lock_irqsave(&nesadapter->phy_lock, flags);
583 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
584 0x0000F088);
585 mh_detected++;
586 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
587 reset_value |= 0x0000003d;
588 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
589
590 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
591 & 0x00000040) != 0x00000040) && (j++ < 5000));
592 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
593 break;
594 }
595 }
596 usleep_range(1000, 2000);
597 }
598 }
599 }
600
601 if (nesadapter->hw_rev == NE020_REV) {
602 timer_setup(&nesadapter->mh_timer, nes_mh_fix, 0);
603 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */
604 add_timer(&nesadapter->mh_timer);
605 } else {
606 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000);
607 }
608
609 timer_setup(&nesadapter->lc_timer, nes_clc, 0);
610 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
611 add_timer(&nesadapter->lc_timer);
612
613 list_add_tail(&nesadapter->list, &nes_adapter_list);
614
615 for (func_index = 0; func_index < 8; func_index++) {
616 pci_bus_read_config_word(nesdev->pcidev->bus,
617 PCI_DEVFN(PCI_SLOT(nesdev->pcidev->devfn),
618 func_index), 0, &vendor_id);
619 if (vendor_id == 0xffff)
620 break;
621 }
622 nes_debug(NES_DBG_INIT, "%s %d functions found for %s.\n", __func__,
623 func_index, pci_name(nesdev->pcidev));
624 nesadapter->adapter_fcn_count = func_index;
625
626 return nesadapter;
627 }
628
629
630 /**
631 * nes_reset_adapter_ne020
632 */
633 static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode)
634 {
635 u32 port_count;
636 u32 u32temp;
637 u32 i;
638
639 u32temp = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
640 port_count = ((u32temp & 0x00000300) >> 8) + 1;
641 /* TODO: assuming that both SERDES are set the same for now */
642 *OneG_Mode = (u32temp & 0x00003c00) ? 0 : 1;
643 nes_debug(NES_DBG_INIT, "Initial Software Reset = 0x%08X, port_count=%u\n",
644 u32temp, port_count);
645 if (*OneG_Mode)
646 nes_debug(NES_DBG_INIT, "Running in 1G mode.\n");
647 u32temp &= 0xff00ffc0;
648 switch (port_count) {
649 case 1:
650 u32temp |= 0x00ee0000;
651 break;
652 case 2:
653 u32temp |= 0x00cc0000;
654 break;
655 case 4:
656 u32temp |= 0x00000000;
657 break;
658 default:
659 return 0;
660 break;
661 }
662
663 /* check and do full reset if needed */
664 if (nes_read_indexed(nesdev, NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8))) {
665 nes_debug(NES_DBG_INIT, "Issuing Full Soft reset = 0x%08X\n", u32temp | 0xd);
666 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
667
668 i = 0;
669 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
670 mdelay(1);
671 if (i > 10000) {
672 nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n");
673 return 0;
674 }
675
676 i = 0;
677 while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000)
678 mdelay(1);
679 if (i > 10000) {
680 printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n",
681 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS));
682 return 0;
683 }
684 }
685
686 /* port reset */
687 switch (port_count) {
688 case 1:
689 u32temp |= 0x00ee0010;
690 break;
691 case 2:
692 u32temp |= 0x00cc0030;
693 break;
694 case 4:
695 u32temp |= 0x00000030;
696 break;
697 }
698
699 nes_debug(NES_DBG_INIT, "Issuing Port Soft reset = 0x%08X\n", u32temp | 0xd);
700 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
701
702 i = 0;
703 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
704 mdelay(1);
705 if (i > 10000) {
706 nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n");
707 return 0;
708 }
709
710 /* serdes 0 */
711 i = 0;
712 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
713 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
714 mdelay(1);
715 if (i > 5000) {
716 nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp);
717 return 0;
718 }
719
720 /* serdes 1 */
721 if (port_count > 1) {
722 i = 0;
723 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
724 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
725 mdelay(1);
726 if (i > 5000) {
727 nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp);
728 return 0;
729 }
730 }
731
732 return port_count;
733 }
734
735
736 /**
737 * nes_init_serdes
738 */
739 static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
740 struct nes_adapter *nesadapter, u8 OneG_Mode)
741 {
742 int i;
743 u32 u32temp;
744 u32 sds;
745
746 if (hw_rev != NE020_REV) {
747 /* init serdes 0 */
748 switch (nesadapter->phy_type[0]) {
749 case NES_PHY_TYPE_CX4:
750 if (wide_ppm_offset)
751 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
752 else
753 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
754 break;
755 case NES_PHY_TYPE_KR:
756 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
757 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
758 break;
759 case NES_PHY_TYPE_PUMA_1G:
760 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
761 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
762 sds |= 0x00000100;
763 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
764 break;
765 default:
766 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
767 break;
768 }
769
770 if (!OneG_Mode)
771 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
772
773 if (port_count < 2)
774 return 0;
775
776 /* init serdes 1 */
777 if (!(OneG_Mode && (nesadapter->phy_type[1] != NES_PHY_TYPE_PUMA_1G)))
778 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
779
780 switch (nesadapter->phy_type[1]) {
781 case NES_PHY_TYPE_ARGUS:
782 case NES_PHY_TYPE_SFP_D:
783 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
784 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
785 break;
786 case NES_PHY_TYPE_CX4:
787 if (wide_ppm_offset)
788 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
789 break;
790 case NES_PHY_TYPE_KR:
791 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
792 break;
793 case NES_PHY_TYPE_PUMA_1G:
794 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
795 sds |= 0x000000100;
796 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
797 }
798 if (!OneG_Mode) {
799 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
800 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
801 sds &= 0xFFFFFFBF;
802 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
803 }
804 } else {
805 /* init serdes 0 */
806 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
807 i = 0;
808 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
809 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
810 mdelay(1);
811 if (i > 5000) {
812 nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp);
813 return 1;
814 }
815 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
816 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
817 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
818 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
819 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
820 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
821 if (OneG_Mode)
822 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
823 else
824 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
825
826 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
827 if (port_count > 1) {
828 /* init serdes 1 */
829 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x00000048);
830 i = 0;
831 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
832 & 0x0000000f)) != 0x0000000f) && (i++ < 5000))
833 mdelay(1);
834 if (i > 5000) {
835 printk("%s: Init: serdes 1 not ready, status=%x\n", __func__, u32temp);
836 /* return 1; */
837 }
838 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x000bdef7);
839 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE1, 0x9ce73000);
840 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE1, 0x0ff00000);
841 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET1, 0x00000000);
842 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS1, 0x00000000);
843 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1, 0x00000000);
844 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1, 0xf0002222);
845 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000ff);
846 }
847 }
848 return 0;
849 }
850
851
852 /**
853 * nes_init_csr_ne020
854 * Initialize registers for ne020 hardware
855 */
856 static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
857 {
858 u32 u32temp;
859
860 nes_debug(NES_DBG_INIT, "port_count=%d\n", port_count);
861
862 nes_write_indexed(nesdev, 0x000001E4, 0x00000007);
863 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
864 nes_write_indexed(nesdev, 0x000001E8, 0x00020874);
865 nes_write_indexed(nesdev, 0x000001D8, 0x00048002);
866 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
867 nes_write_indexed(nesdev, 0x000001FC, 0x00050005);
868 nes_write_indexed(nesdev, 0x00000600, 0x55555555);
869 nes_write_indexed(nesdev, 0x00000604, 0x55555555);
870
871 /* TODO: move these MAC register settings to NIC bringup */
872 nes_write_indexed(nesdev, 0x00002000, 0x00000001);
873 nes_write_indexed(nesdev, 0x00002004, 0x00000001);
874 nes_write_indexed(nesdev, 0x00002008, 0x0000FFFF);
875 nes_write_indexed(nesdev, 0x0000200C, 0x00000001);
876 nes_write_indexed(nesdev, 0x00002010, 0x000003c1);
877 nes_write_indexed(nesdev, 0x0000201C, 0x75345678);
878 if (port_count > 1) {
879 nes_write_indexed(nesdev, 0x00002200, 0x00000001);
880 nes_write_indexed(nesdev, 0x00002204, 0x00000001);
881 nes_write_indexed(nesdev, 0x00002208, 0x0000FFFF);
882 nes_write_indexed(nesdev, 0x0000220C, 0x00000001);
883 nes_write_indexed(nesdev, 0x00002210, 0x000003c1);
884 nes_write_indexed(nesdev, 0x0000221C, 0x75345678);
885 nes_write_indexed(nesdev, 0x00000908, 0x20000001);
886 }
887 if (port_count > 2) {
888 nes_write_indexed(nesdev, 0x00002400, 0x00000001);
889 nes_write_indexed(nesdev, 0x00002404, 0x00000001);
890 nes_write_indexed(nesdev, 0x00002408, 0x0000FFFF);
891 nes_write_indexed(nesdev, 0x0000240C, 0x00000001);
892 nes_write_indexed(nesdev, 0x00002410, 0x000003c1);
893 nes_write_indexed(nesdev, 0x0000241C, 0x75345678);
894 nes_write_indexed(nesdev, 0x00000910, 0x20000001);
895
896 nes_write_indexed(nesdev, 0x00002600, 0x00000001);
897 nes_write_indexed(nesdev, 0x00002604, 0x00000001);
898 nes_write_indexed(nesdev, 0x00002608, 0x0000FFFF);
899 nes_write_indexed(nesdev, 0x0000260C, 0x00000001);
900 nes_write_indexed(nesdev, 0x00002610, 0x000003c1);
901 nes_write_indexed(nesdev, 0x0000261C, 0x75345678);
902 nes_write_indexed(nesdev, 0x00000918, 0x20000001);
903 }
904
905 nes_write_indexed(nesdev, 0x00005000, 0x00018000);
906 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
907 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG1, (wqm_quanta << 1) |
908 0x00000001);
909 nes_write_indexed(nesdev, 0x00005008, 0x1F1F1F1F);
910 nes_write_indexed(nesdev, 0x00005010, 0x1F1F1F1F);
911 nes_write_indexed(nesdev, 0x00005018, 0x1F1F1F1F);
912 nes_write_indexed(nesdev, 0x00005020, 0x1F1F1F1F);
913 nes_write_indexed(nesdev, 0x00006090, 0xFFFFFFFF);
914
915 /* TODO: move this to code, get from EEPROM */
916 nes_write_indexed(nesdev, 0x00000900, 0x20000001);
917 nes_write_indexed(nesdev, 0x000060C0, 0x0000028e);
918 nes_write_indexed(nesdev, 0x000060C8, 0x00000020);
919
920 nes_write_indexed(nesdev, 0x000001EC, 0x7b2625a0);
921 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
922
923 if (hw_rev != NE020_REV) {
924 u32temp = nes_read_indexed(nesdev, 0x000008e8);
925 u32temp |= 0x80000000;
926 nes_write_indexed(nesdev, 0x000008e8, u32temp);
927 u32temp = nes_read_indexed(nesdev, 0x000021f8);
928 u32temp &= 0x7fffffff;
929 u32temp |= 0x7fff0010;
930 nes_write_indexed(nesdev, 0x000021f8, u32temp);
931 if (port_count > 1) {
932 u32temp = nes_read_indexed(nesdev, 0x000023f8);
933 u32temp &= 0x7fffffff;
934 u32temp |= 0x7fff0010;
935 nes_write_indexed(nesdev, 0x000023f8, u32temp);
936 }
937 }
938 }
939
940
941 /**
942 * nes_destroy_adapter - destroy the adapter structure
943 */
944 void nes_destroy_adapter(struct nes_adapter *nesadapter)
945 {
946 struct nes_adapter *tmp_adapter;
947
948 list_for_each_entry(tmp_adapter, &nes_adapter_list, list) {
949 nes_debug(NES_DBG_SHUTDOWN, "Nes Adapter list entry = 0x%p.\n",
950 tmp_adapter);
951 }
952
953 nesadapter->ref_count--;
954 if (!nesadapter->ref_count) {
955 if (nesadapter->hw_rev == NE020_REV) {
956 del_timer(&nesadapter->mh_timer);
957 }
958 del_timer(&nesadapter->lc_timer);
959
960 list_del(&nesadapter->list);
961 kfree(nesadapter);
962 }
963 }
964
965
966 /**
967 * nes_init_cqp
968 */
969 int nes_init_cqp(struct nes_device *nesdev)
970 {
971 struct nes_adapter *nesadapter = nesdev->nesadapter;
972 struct nes_hw_cqp_qp_context *cqp_qp_context;
973 struct nes_hw_cqp_wqe *cqp_wqe;
974 struct nes_hw_ceq *ceq;
975 struct nes_hw_ceq *nic_ceq;
976 struct nes_hw_aeq *aeq;
977 void *vmem;
978 dma_addr_t pmem;
979 u32 count=0;
980 u32 cqp_head;
981 u64 u64temp;
982 u32 u32temp;
983
984 /* allocate CQP memory */
985 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
986 /* SQ is 512 byte aligned, others are 256 byte aligned */
987 nesdev->cqp_mem_size = 512 +
988 (sizeof(struct nes_hw_cqp_wqe) * NES_CQP_SQ_SIZE) +
989 (sizeof(struct nes_hw_cqe) * NES_CCQ_SIZE) +
990 max(((u32)sizeof(struct nes_hw_ceqe) * NES_CCEQ_SIZE), (u32)256) +
991 max(((u32)sizeof(struct nes_hw_ceqe) * NES_NIC_CEQ_SIZE), (u32)256) +
992 (sizeof(struct nes_hw_aeqe) * nesadapter->max_qp) +
993 sizeof(struct nes_hw_cqp_qp_context);
994
995 nesdev->cqp_vbase = pci_zalloc_consistent(nesdev->pcidev,
996 nesdev->cqp_mem_size,
997 &nesdev->cqp_pbase);
998 if (!nesdev->cqp_vbase) {
999 nes_debug(NES_DBG_INIT, "Unable to allocate memory for host descriptor rings\n");
1000 return -ENOMEM;
1001 }
1002
1003 /* Allocate a twice the number of CQP requests as the SQ size */
1004 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
1005 2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
1006 if (!nesdev->nes_cqp_requests) {
1007 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1008 nesdev->cqp.sq_pbase);
1009 return -ENOMEM;
1010 }
1011
1012 nes_debug(NES_DBG_INIT, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
1013 nesdev->cqp_vbase, (unsigned long)nesdev->cqp_pbase, nesdev->cqp_mem_size);
1014
1015 spin_lock_init(&nesdev->cqp.lock);
1016 init_waitqueue_head(&nesdev->cqp.waitq);
1017
1018 /* Setup Various Structures */
1019 vmem = (void *)(((unsigned long)nesdev->cqp_vbase + (512 - 1)) &
1020 ~(unsigned long)(512 - 1));
1021 pmem = (dma_addr_t)(((unsigned long long)nesdev->cqp_pbase + (512 - 1)) &
1022 ~(unsigned long long)(512 - 1));
1023
1024 nesdev->cqp.sq_vbase = vmem;
1025 nesdev->cqp.sq_pbase = pmem;
1026 nesdev->cqp.sq_size = NES_CQP_SQ_SIZE;
1027 nesdev->cqp.sq_head = 0;
1028 nesdev->cqp.sq_tail = 0;
1029 nesdev->cqp.qp_id = PCI_FUNC(nesdev->pcidev->devfn);
1030
1031 vmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1032 pmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1033
1034 nesdev->ccq.cq_vbase = vmem;
1035 nesdev->ccq.cq_pbase = pmem;
1036 nesdev->ccq.cq_size = NES_CCQ_SIZE;
1037 nesdev->ccq.cq_head = 0;
1038 nesdev->ccq.ce_handler = nes_cqp_ce_handler;
1039 nesdev->ccq.cq_number = PCI_FUNC(nesdev->pcidev->devfn);
1040
1041 vmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1042 pmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1043
1044 nesdev->ceq_index = PCI_FUNC(nesdev->pcidev->devfn);
1045 ceq = &nesadapter->ceq[nesdev->ceq_index];
1046 ceq->ceq_vbase = vmem;
1047 ceq->ceq_pbase = pmem;
1048 ceq->ceq_size = NES_CCEQ_SIZE;
1049 ceq->ceq_head = 0;
1050
1051 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1052 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1053
1054 nesdev->nic_ceq_index = PCI_FUNC(nesdev->pcidev->devfn) + 8;
1055 nic_ceq = &nesadapter->ceq[nesdev->nic_ceq_index];
1056 nic_ceq->ceq_vbase = vmem;
1057 nic_ceq->ceq_pbase = pmem;
1058 nic_ceq->ceq_size = NES_NIC_CEQ_SIZE;
1059 nic_ceq->ceq_head = 0;
1060
1061 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1062 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1063
1064 aeq = &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)];
1065 aeq->aeq_vbase = vmem;
1066 aeq->aeq_pbase = pmem;
1067 aeq->aeq_size = nesadapter->max_qp;
1068 aeq->aeq_head = 0;
1069
1070 /* Setup QP Context */
1071 vmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1072 pmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1073
1074 cqp_qp_context = vmem;
1075 cqp_qp_context->context_words[0] =
1076 cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
1077 cqp_qp_context->context_words[1] = 0;
1078 cqp_qp_context->context_words[2] = cpu_to_le32((u32)nesdev->cqp.sq_pbase);
1079 cqp_qp_context->context_words[3] = cpu_to_le32(((u64)nesdev->cqp.sq_pbase) >> 32);
1080
1081
1082 /* Write the address to Create CQP */
1083 if ((sizeof(dma_addr_t) > 4)) {
1084 nes_write_indexed(nesdev,
1085 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1086 ((u64)pmem) >> 32);
1087 } else {
1088 nes_write_indexed(nesdev,
1089 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8), 0);
1090 }
1091 nes_write_indexed(nesdev,
1092 NES_IDX_CREATE_CQP_LOW + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1093 (u32)pmem);
1094
1095 INIT_LIST_HEAD(&nesdev->cqp_avail_reqs);
1096 INIT_LIST_HEAD(&nesdev->cqp_pending_reqs);
1097
1098 for (count = 0; count < 2*NES_CQP_SQ_SIZE; count++) {
1099 init_waitqueue_head(&nesdev->nes_cqp_requests[count].waitq);
1100 list_add_tail(&nesdev->nes_cqp_requests[count].list, &nesdev->cqp_avail_reqs);
1101 }
1102
1103 /* Write Create CCQ WQE */
1104 cqp_head = nesdev->cqp.sq_head++;
1105 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1106 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1107 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1108 (NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1109 NES_CQP_CQ_CHK_OVERFLOW | ((u32)nesdev->ccq.cq_size << 16)));
1110 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1111 (nesdev->ccq.cq_number |
1112 ((u32)nesdev->ceq_index << 16)));
1113 u64temp = (u64)nesdev->ccq.cq_pbase;
1114 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1115 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1116 u64temp = (unsigned long)&nesdev->ccq;
1117 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] =
1118 cpu_to_le32((u32)(u64temp >> 1));
1119 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1120 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1121 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1122
1123 /* Write Create CEQ WQE */
1124 cqp_head = nesdev->cqp.sq_head++;
1125 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1126 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1127 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1128 (NES_CQP_CREATE_CEQ + ((u32)nesdev->ceq_index << 8)));
1129 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, ceq->ceq_size);
1130 u64temp = (u64)ceq->ceq_pbase;
1131 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1132
1133 /* Write Create AEQ WQE */
1134 cqp_head = nesdev->cqp.sq_head++;
1135 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1136 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1137 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1138 (NES_CQP_CREATE_AEQ + ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8)));
1139 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX, aeq->aeq_size);
1140 u64temp = (u64)aeq->aeq_pbase;
1141 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1142
1143 /* Write Create NIC CEQ WQE */
1144 cqp_head = nesdev->cqp.sq_head++;
1145 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1146 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1147 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1148 (NES_CQP_CREATE_CEQ + ((u32)nesdev->nic_ceq_index << 8)));
1149 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, nic_ceq->ceq_size);
1150 u64temp = (u64)nic_ceq->ceq_pbase;
1151 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1152
1153 /* Poll until CCQP done */
1154 count = 0;
1155 do {
1156 if (count++ > 1000) {
1157 printk(KERN_ERR PFX "Error creating CQP\n");
1158 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1159 nesdev->cqp_vbase, nesdev->cqp_pbase);
1160 return -1;
1161 }
1162 udelay(10);
1163 } while (!(nes_read_indexed(nesdev,
1164 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn) * 8)) & (1 << 8)));
1165
1166 nes_debug(NES_DBG_INIT, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev,
1167 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1168
1169 u32temp = 0x04800000;
1170 nes_write32(nesdev->regs+NES_WQE_ALLOC, u32temp | nesdev->cqp.qp_id);
1171
1172 /* wait for the CCQ, CEQ, and AEQ to get created */
1173 count = 0;
1174 do {
1175 if (count++ > 1000) {
1176 printk(KERN_ERR PFX "Error creating CCQ, CEQ, and AEQ\n");
1177 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1178 nesdev->cqp_vbase, nesdev->cqp_pbase);
1179 return -1;
1180 }
1181 udelay(10);
1182 } while (((nes_read_indexed(nesdev,
1183 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
1184
1185 /* dump the QP status value */
1186 nes_debug(NES_DBG_INIT, "QP Status = 0x%08X\n", nes_read_indexed(nesdev,
1187 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1188
1189 nesdev->cqp.sq_tail++;
1190
1191 return 0;
1192 }
1193
1194
1195 /**
1196 * nes_destroy_cqp
1197 */
1198 int nes_destroy_cqp(struct nes_device *nesdev)
1199 {
1200 struct nes_hw_cqp_wqe *cqp_wqe;
1201 u32 count = 0;
1202 u32 cqp_head;
1203 unsigned long flags;
1204
1205 do {
1206 if (count++ > 1000)
1207 break;
1208 udelay(10);
1209 } while (!(nesdev->cqp.sq_head == nesdev->cqp.sq_tail));
1210
1211 /* Reset CCQ */
1212 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_RESET |
1213 nesdev->ccq.cq_number);
1214
1215 /* Disable device interrupts */
1216 nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
1217
1218 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1219
1220 /* Destroy the AEQ */
1221 cqp_head = nesdev->cqp.sq_head++;
1222 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1223 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1224 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_AEQ |
1225 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
1226 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
1227
1228 /* Destroy the NIC CEQ */
1229 cqp_head = nesdev->cqp.sq_head++;
1230 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1231 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1232 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1233 ((u32)nesdev->nic_ceq_index << 8));
1234
1235 /* Destroy the CEQ */
1236 cqp_head = nesdev->cqp.sq_head++;
1237 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1238 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1239 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1240 (nesdev->ceq_index << 8));
1241
1242 /* Destroy the CCQ */
1243 cqp_head = nesdev->cqp.sq_head++;
1244 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1245 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1246 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
1247 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
1248 ((u32)nesdev->ceq_index << 16));
1249
1250 /* Destroy CQP */
1251 cqp_head = nesdev->cqp.sq_head++;
1252 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1253 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1254 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP |
1255 NES_CQP_QP_TYPE_CQP);
1256 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
1257
1258 barrier();
1259 /* Ring doorbell (5 WQEs) */
1260 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x05800000 | nesdev->cqp.qp_id);
1261
1262 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1263
1264 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1265 count = 0;
1266 do {
1267 if (count++ > 1000) {
1268 printk(KERN_ERR PFX "Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1269 PCI_FUNC(nesdev->pcidev->devfn));
1270 break;
1271 }
1272 udelay(10);
1273 } while (((nes_read_indexed(nesdev,
1274 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15 << 8)) != 0));
1275
1276 /* dump the QP status value */
1277 nes_debug(NES_DBG_SHUTDOWN, "Function%d: QP Status = 0x%08X\n",
1278 PCI_FUNC(nesdev->pcidev->devfn),
1279 nes_read_indexed(nesdev,
1280 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1281
1282 kfree(nesdev->nes_cqp_requests);
1283
1284 /* Free the control structures */
1285 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1286 nesdev->cqp.sq_pbase);
1287
1288 return 0;
1289 }
1290
1291
1292 /**
1293 * nes_init_1g_phy
1294 */
1295 static int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
1296 {
1297 u32 counter = 0;
1298 u16 phy_data;
1299 int ret = 0;
1300
1301 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1302 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
1303
1304 /* Reset the PHY */
1305 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1306 udelay(100);
1307 counter = 0;
1308 do {
1309 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1310 if (counter++ > 100) {
1311 ret = -1;
1312 break;
1313 }
1314 } while (phy_data & 0x8000);
1315
1316 /* Setting no phy loopback */
1317 phy_data &= 0xbfff;
1318 phy_data |= 0x1140;
1319 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1320 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1321 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1322 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1323
1324 /* Setting the interrupt mask */
1325 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1326 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1327 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1328
1329 /* turning on flow control */
1330 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1331 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1332 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1333
1334 /* Clear Half duplex */
1335 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1336 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1337 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1338
1339 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1340 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1341
1342 return ret;
1343 }
1344
1345
1346 /**
1347 * nes_init_2025_phy
1348 */
1349 static int nes_init_2025_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
1350 {
1351 u32 temp_phy_data = 0;
1352 u32 temp_phy_data2 = 0;
1353 u32 counter = 0;
1354 u32 sds;
1355 u32 mac_index = nesdev->mac_index;
1356 int ret = 0;
1357 unsigned int first_attempt = 1;
1358
1359 /* Check firmware heartbeat */
1360 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1361 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1362 udelay(1500);
1363 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1364 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1365
1366 if (temp_phy_data != temp_phy_data2) {
1367 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1368 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1369 if ((temp_phy_data & 0xff) > 0x20)
1370 return 0;
1371 printk(PFX "Reinitialize external PHY\n");
1372 }
1373
1374 /* no heartbeat, configure the PHY */
1375 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1376 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1377 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1378 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1379
1380 switch (phy_type) {
1381 case NES_PHY_TYPE_ARGUS:
1382 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1383 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1384 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1385 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1386 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1387 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1388 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1389
1390 /* setup LEDs */
1391 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1392 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1393 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1394 break;
1395
1396 case NES_PHY_TYPE_SFP_D:
1397 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1398 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1399 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1400 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1401 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1402 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1403 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1404
1405 /* setup LEDs */
1406 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1407 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1408 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1409 break;
1410
1411 case NES_PHY_TYPE_KR:
1412 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1413 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1414 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1415 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0010);
1416 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1417 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0080);
1418 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1419
1420 /* setup LEDs */
1421 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x000B);
1422 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x0003);
1423 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0004);
1424
1425 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0022, 0x406D);
1426 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0023, 0x0020);
1427 break;
1428 }
1429
1430 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
1431
1432 /* Bring PHY out of reset */
1433 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
1434
1435 /* Check for heartbeat */
1436 counter = 0;
1437 mdelay(690);
1438 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1439 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1440 do {
1441 if (counter++ > 150) {
1442 printk(PFX "No PHY heartbeat\n");
1443 break;
1444 }
1445 mdelay(1);
1446 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1447 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1448 } while ((temp_phy_data2 == temp_phy_data));
1449
1450 /* wait for tracking */
1451 counter = 0;
1452 do {
1453 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1454 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1455 if (counter++ > 300) {
1456 if (((temp_phy_data & 0xff) == 0x0) && first_attempt) {
1457 first_attempt = 0;
1458 counter = 0;
1459 /* reset AMCC PHY and try again */
1460 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0);
1461 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040);
1462 continue;
1463 } else {
1464 ret = 1;
1465 break;
1466 }
1467 }
1468 mdelay(10);
1469 } while ((temp_phy_data & 0xff) < 0x30);
1470
1471 /* setup signal integrity */
1472 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1473 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1474 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1475 if (phy_type == NES_PHY_TYPE_KR) {
1476 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x000C);
1477 } else {
1478 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1479 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
1480 }
1481
1482 /* reset serdes */
1483 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200);
1484 sds |= 0x1;
1485 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1486 sds &= 0xfffffffe;
1487 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1488
1489 counter = 0;
1490 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1491 && (counter++ < 5000))
1492 ;
1493
1494 return ret;
1495 }
1496
1497
1498 /**
1499 * nes_init_phy
1500 */
1501 int nes_init_phy(struct nes_device *nesdev)
1502 {
1503 struct nes_adapter *nesadapter = nesdev->nesadapter;
1504 u32 mac_index = nesdev->mac_index;
1505 u32 tx_config = 0;
1506 unsigned long flags;
1507 u8 phy_type = nesadapter->phy_type[mac_index];
1508 u8 phy_index = nesadapter->phy_index[mac_index];
1509 int ret = 0;
1510
1511 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1512 if (phy_type == NES_PHY_TYPE_1G) {
1513 /* setup 1G MDIO operation */
1514 tx_config &= 0xFFFFFFE3;
1515 tx_config |= 0x04;
1516 } else {
1517 /* setup 10G MDIO operation */
1518 tx_config &= 0xFFFFFFE3;
1519 tx_config |= 0x1D;
1520 }
1521 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1522
1523 spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
1524
1525 switch (phy_type) {
1526 case NES_PHY_TYPE_1G:
1527 ret = nes_init_1g_phy(nesdev, phy_type, phy_index);
1528 break;
1529 case NES_PHY_TYPE_ARGUS:
1530 case NES_PHY_TYPE_SFP_D:
1531 case NES_PHY_TYPE_KR:
1532 ret = nes_init_2025_phy(nesdev, phy_type, phy_index);
1533 break;
1534 }
1535
1536 spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
1537
1538 return ret;
1539 }
1540
1541
1542 /**
1543 * nes_replenish_nic_rq
1544 */
1545 static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
1546 {
1547 unsigned long flags;
1548 dma_addr_t bus_address;
1549 struct sk_buff *skb;
1550 struct nes_hw_nic_rq_wqe *nic_rqe;
1551 struct nes_hw_nic *nesnic;
1552 struct nes_device *nesdev;
1553 struct nes_rskb_cb *cb;
1554 u32 rx_wqes_posted = 0;
1555
1556 nesnic = &nesvnic->nic;
1557 nesdev = nesvnic->nesdev;
1558 spin_lock_irqsave(&nesnic->rq_lock, flags);
1559 if (nesnic->replenishing_rq !=0) {
1560 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1561 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1562 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1563 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1564 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1565 add_timer(&nesvnic->rq_wqes_timer);
1566 } else
1567 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1568 return;
1569 }
1570 nesnic->replenishing_rq = 1;
1571 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1572 do {
1573 skb = dev_alloc_skb(nesvnic->max_frame_size);
1574 if (skb) {
1575 skb->dev = nesvnic->netdev;
1576
1577 bus_address = pci_map_single(nesdev->pcidev,
1578 skb->data, nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1579 cb = (struct nes_rskb_cb *)&skb->cb[0];
1580 cb->busaddr = bus_address;
1581 cb->maplen = nesvnic->max_frame_size;
1582
1583 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_head];
1584 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] =
1585 cpu_to_le32(nesvnic->max_frame_size);
1586 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1587 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] =
1588 cpu_to_le32((u32)bus_address);
1589 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] =
1590 cpu_to_le32((u32)((u64)bus_address >> 32));
1591 nesnic->rx_skb[nesnic->rq_head] = skb;
1592 nesnic->rq_head++;
1593 nesnic->rq_head &= nesnic->rq_size - 1;
1594 atomic_dec(&nesvnic->rx_skbs_needed);
1595 barrier();
1596 if (++rx_wqes_posted == 255) {
1597 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1598 rx_wqes_posted = 0;
1599 }
1600 } else {
1601 spin_lock_irqsave(&nesnic->rq_lock, flags);
1602 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1603 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1604 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1605 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1606 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1607 add_timer(&nesvnic->rq_wqes_timer);
1608 } else
1609 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1610 break;
1611 }
1612 } while (atomic_read(&nesvnic->rx_skbs_needed));
1613 barrier();
1614 if (rx_wqes_posted)
1615 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1616 nesnic->replenishing_rq = 0;
1617 }
1618
1619
1620 /**
1621 * nes_rq_wqes_timeout
1622 */
1623 static void nes_rq_wqes_timeout(struct timer_list *t)
1624 {
1625 struct nes_vnic *nesvnic = from_timer(nesvnic, t, rq_wqes_timer);
1626 printk("%s: Timer fired.\n", __func__);
1627 atomic_set(&nesvnic->rx_skb_timer_running, 0);
1628 if (atomic_read(&nesvnic->rx_skbs_needed))
1629 nes_replenish_nic_rq(nesvnic);
1630 }
1631
1632
1633 /**
1634 * nes_init_nic_qp
1635 */
1636 int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1637 {
1638 struct nes_hw_cqp_wqe *cqp_wqe;
1639 struct nes_hw_nic_sq_wqe *nic_sqe;
1640 struct nes_hw_nic_qp_context *nic_context;
1641 struct sk_buff *skb;
1642 struct nes_hw_nic_rq_wqe *nic_rqe;
1643 struct nes_vnic *nesvnic = netdev_priv(netdev);
1644 unsigned long flags;
1645 void *vmem;
1646 dma_addr_t pmem;
1647 u64 u64temp;
1648 int ret;
1649 u32 cqp_head;
1650 u32 counter;
1651 u32 wqe_count;
1652 struct nes_rskb_cb *cb;
1653 u8 jumbomode=0;
1654
1655 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1656 nesvnic->nic_mem_size = 256 +
1657 (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag)) +
1658 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe)) +
1659 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe)) +
1660 (NES_NIC_WQ_SIZE * 2 * sizeof(struct nes_hw_nic_cqe)) +
1661 sizeof(struct nes_hw_nic_qp_context);
1662
1663 nesvnic->nic_vbase = pci_zalloc_consistent(nesdev->pcidev,
1664 nesvnic->nic_mem_size,
1665 &nesvnic->nic_pbase);
1666 if (!nesvnic->nic_vbase) {
1667 nes_debug(NES_DBG_INIT, "Unable to allocate memory for NIC host descriptor rings\n");
1668 return -ENOMEM;
1669 }
1670 nes_debug(NES_DBG_INIT, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1671 nesvnic->nic_vbase, (unsigned long)nesvnic->nic_pbase, nesvnic->nic_mem_size);
1672
1673 vmem = (void *)(((unsigned long)nesvnic->nic_vbase + (256 - 1)) &
1674 ~(unsigned long)(256 - 1));
1675 pmem = (dma_addr_t)(((unsigned long long)nesvnic->nic_pbase + (256 - 1)) &
1676 ~(unsigned long long)(256 - 1));
1677
1678 /* Setup the first Fragment buffers */
1679 nesvnic->nic.first_frag_vbase = vmem;
1680
1681 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1682 nesvnic->nic.frag_paddr[counter] = pmem;
1683 pmem += sizeof(struct nes_first_frag);
1684 }
1685
1686 /* setup the SQ */
1687 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag));
1688
1689 nesvnic->nic.sq_vbase = (void *)vmem;
1690 nesvnic->nic.sq_pbase = pmem;
1691 nesvnic->nic.sq_head = 0;
1692 nesvnic->nic.sq_tail = 0;
1693 nesvnic->nic.sq_size = NES_NIC_WQ_SIZE;
1694 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1695 nic_sqe = &nesvnic->nic.sq_vbase[counter];
1696 nic_sqe->wqe_words[NES_NIC_SQ_WQE_MISC_IDX] =
1697 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM |
1698 NES_NIC_SQ_WQE_COMPLETION);
1699 nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX] =
1700 cpu_to_le32((u32)NES_FIRST_FRAG_SIZE << 16);
1701 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX] =
1702 cpu_to_le32((u32)nesvnic->nic.frag_paddr[counter]);
1703 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX] =
1704 cpu_to_le32((u32)((u64)nesvnic->nic.frag_paddr[counter] >> 32));
1705 }
1706
1707 nesvnic->get_cqp_request = nes_get_cqp_request;
1708 nesvnic->post_cqp_request = nes_post_cqp_request;
1709 nesvnic->mcrq_mcast_filter = NULL;
1710
1711 spin_lock_init(&nesvnic->nic.rq_lock);
1712
1713 /* setup the RQ */
1714 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1715 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1716
1717
1718 nesvnic->nic.rq_vbase = vmem;
1719 nesvnic->nic.rq_pbase = pmem;
1720 nesvnic->nic.rq_head = 0;
1721 nesvnic->nic.rq_tail = 0;
1722 nesvnic->nic.rq_size = NES_NIC_WQ_SIZE;
1723
1724 /* setup the CQ */
1725 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1726 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1727
1728 if (nesdev->nesadapter->netdev_count > 2)
1729 nesvnic->mcrq_qp_id = nesvnic->nic_index + 32;
1730 else
1731 nesvnic->mcrq_qp_id = nesvnic->nic.qp_id + 4;
1732
1733 nesvnic->nic_cq.cq_vbase = vmem;
1734 nesvnic->nic_cq.cq_pbase = pmem;
1735 nesvnic->nic_cq.cq_head = 0;
1736 nesvnic->nic_cq.cq_size = NES_NIC_WQ_SIZE * 2;
1737
1738 nesvnic->nic_cq.ce_handler = nes_nic_napi_ce_handler;
1739
1740 /* Send CreateCQ request to CQP */
1741 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1742 cqp_head = nesdev->cqp.sq_head;
1743
1744 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1745 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1746
1747 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
1748 NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1749 ((u32)nesvnic->nic_cq.cq_size << 16));
1750 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
1751 nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16));
1752 u64temp = (u64)nesvnic->nic_cq.cq_pbase;
1753 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1754 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1755 u64temp = (unsigned long)&nesvnic->nic_cq;
1756 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
1757 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1758 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1759 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1760 if (++cqp_head >= nesdev->cqp.sq_size)
1761 cqp_head = 0;
1762 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1763 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1764
1765 /* Send CreateQP request to CQP */
1766 nic_context = (void *)(&nesvnic->nic_cq.cq_vbase[nesvnic->nic_cq.cq_size]);
1767 nic_context->context_words[NES_NIC_CTX_MISC_IDX] =
1768 cpu_to_le32((u32)NES_NIC_CTX_SIZE |
1769 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 12));
1770 nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1771 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
1772 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
1773 if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0) {
1774 nic_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
1775 }
1776
1777 u64temp = (u64)nesvnic->nic.sq_pbase;
1778 nic_context->context_words[NES_NIC_CTX_SQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1779 nic_context->context_words[NES_NIC_CTX_SQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1780 u64temp = (u64)nesvnic->nic.rq_pbase;
1781 nic_context->context_words[NES_NIC_CTX_RQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
1782 nic_context->context_words[NES_NIC_CTX_RQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1783
1784 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_QP |
1785 NES_CQP_QP_TYPE_NIC);
1786 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic.qp_id);
1787 u64temp = (u64)nesvnic->nic_cq.cq_pbase +
1788 (nesvnic->nic_cq.cq_size * sizeof(struct nes_hw_nic_cqe));
1789 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
1790
1791 if (++cqp_head >= nesdev->cqp.sq_size)
1792 cqp_head = 0;
1793 nesdev->cqp.sq_head = cqp_head;
1794
1795 barrier();
1796
1797 /* Ring doorbell (2 WQEs) */
1798 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1799
1800 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1801 nes_debug(NES_DBG_INIT, "Waiting for create NIC QP%u to complete.\n",
1802 nesvnic->nic.qp_id);
1803
1804 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
1805 NES_EVENT_TIMEOUT);
1806 nes_debug(NES_DBG_INIT, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1807 nesvnic->nic.qp_id, ret);
1808 if (!ret) {
1809 nes_debug(NES_DBG_INIT, "NIC QP%u create timeout expired\n", nesvnic->nic.qp_id);
1810 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
1811 nesvnic->nic_pbase);
1812 return -EIO;
1813 }
1814
1815 /* Populate the RQ */
1816 for (counter = 0; counter < (NES_NIC_WQ_SIZE - 1); counter++) {
1817 skb = dev_alloc_skb(nesvnic->max_frame_size);
1818 if (!skb) {
1819 nes_debug(NES_DBG_INIT, "%s: out of memory for receive skb\n", netdev->name);
1820
1821 nes_destroy_nic_qp(nesvnic);
1822 return -ENOMEM;
1823 }
1824
1825 skb->dev = netdev;
1826
1827 pmem = pci_map_single(nesdev->pcidev, skb->data,
1828 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1829 cb = (struct nes_rskb_cb *)&skb->cb[0];
1830 cb->busaddr = pmem;
1831 cb->maplen = nesvnic->max_frame_size;
1832
1833 nic_rqe = &nesvnic->nic.rq_vbase[counter];
1834 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] = cpu_to_le32(nesvnic->max_frame_size);
1835 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1836 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] = cpu_to_le32((u32)pmem);
1837 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] = cpu_to_le32((u32)((u64)pmem >> 32));
1838 nesvnic->nic.rx_skb[counter] = skb;
1839 }
1840
1841 wqe_count = NES_NIC_WQ_SIZE - 1;
1842 nesvnic->nic.rq_head = wqe_count;
1843 barrier();
1844 do {
1845 counter = min(wqe_count, ((u32)255));
1846 wqe_count -= counter;
1847 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id);
1848 } while (wqe_count);
1849 timer_setup(&nesvnic->rq_wqes_timer, nes_rq_wqes_timeout, 0);
1850 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
1851 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
1852 {
1853 nes_nic_init_timer(nesdev);
1854 if (netdev->mtu > 1500)
1855 jumbomode = 1;
1856 nes_nic_init_timer_defaults(nesdev, jumbomode);
1857 }
1858 if ((nesdev->nesadapter->allow_unaligned_fpdus) &&
1859 (nes_init_mgt_qp(nesdev, netdev, nesvnic))) {
1860 nes_debug(NES_DBG_INIT, "%s: Out of memory for pau nic\n",
1861 netdev->name);
1862 nes_destroy_nic_qp(nesvnic);
1863 return -ENOMEM;
1864 }
1865
1866 return 0;
1867 }
1868
1869
1870 /**
1871 * nes_destroy_nic_qp
1872 */
1873 void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
1874 {
1875 u64 u64temp;
1876 dma_addr_t bus_address;
1877 struct nes_device *nesdev = nesvnic->nesdev;
1878 struct nes_hw_cqp_wqe *cqp_wqe;
1879 struct nes_hw_nic_sq_wqe *nic_sqe;
1880 __le16 *wqe_fragment_length;
1881 u16 wqe_fragment_index;
1882 u32 cqp_head;
1883 u32 wqm_cfg0;
1884 unsigned long flags;
1885 struct sk_buff *rx_skb;
1886 struct nes_rskb_cb *cb;
1887 int ret;
1888
1889 if (nesdev->nesadapter->allow_unaligned_fpdus)
1890 nes_destroy_mgt(nesvnic);
1891
1892 /* clear wqe stall before destroying NIC QP */
1893 wqm_cfg0 = nes_read_indexed(nesdev, NES_IDX_WQM_CONFIG0);
1894 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0 & 0xFFFF7FFF);
1895
1896 /* Free remaining NIC receive buffers */
1897 while (nesvnic->nic.rq_head != nesvnic->nic.rq_tail) {
1898 rx_skb = nesvnic->nic.rx_skb[nesvnic->nic.rq_tail];
1899 cb = (struct nes_rskb_cb *)&rx_skb->cb[0];
1900 pci_unmap_single(nesdev->pcidev, cb->busaddr, cb->maplen,
1901 PCI_DMA_FROMDEVICE);
1902
1903 dev_kfree_skb(nesvnic->nic.rx_skb[nesvnic->nic.rq_tail++]);
1904 nesvnic->nic.rq_tail &= (nesvnic->nic.rq_size - 1);
1905 }
1906
1907 /* Free remaining NIC transmit buffers */
1908 while (nesvnic->nic.sq_head != nesvnic->nic.sq_tail) {
1909 nic_sqe = &nesvnic->nic.sq_vbase[nesvnic->nic.sq_tail];
1910 wqe_fragment_index = 1;
1911 wqe_fragment_length = (__le16 *)
1912 &nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
1913 /* bump past the vlan tag */
1914 wqe_fragment_length++;
1915 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
1916 u64temp = (u64)le32_to_cpu(
1917 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1918 wqe_fragment_index*2]);
1919 u64temp += ((u64)le32_to_cpu(
1920 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
1921 + wqe_fragment_index*2]))<<32;
1922 bus_address = (dma_addr_t)u64temp;
1923 if (test_and_clear_bit(nesvnic->nic.sq_tail,
1924 nesvnic->nic.first_frag_overflow)) {
1925 pci_unmap_single(nesdev->pcidev,
1926 bus_address,
1927 le16_to_cpu(wqe_fragment_length[
1928 wqe_fragment_index++]),
1929 PCI_DMA_TODEVICE);
1930 }
1931 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
1932 if (wqe_fragment_length[wqe_fragment_index]) {
1933 u64temp = le32_to_cpu(
1934 nic_sqe->wqe_words[
1935 NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1936 wqe_fragment_index*2]);
1937 u64temp += ((u64)le32_to_cpu(
1938 nic_sqe->wqe_words[
1939 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+
1940 wqe_fragment_index*2]))<<32;
1941 bus_address = (dma_addr_t)u64temp;
1942 pci_unmap_page(nesdev->pcidev,
1943 bus_address,
1944 le16_to_cpu(
1945 wqe_fragment_length[
1946 wqe_fragment_index]),
1947 PCI_DMA_TODEVICE);
1948 } else
1949 break;
1950 }
1951 }
1952 if (nesvnic->nic.tx_skb[nesvnic->nic.sq_tail])
1953 dev_kfree_skb(
1954 nesvnic->nic.tx_skb[nesvnic->nic.sq_tail]);
1955
1956 nesvnic->nic.sq_tail = (nesvnic->nic.sq_tail + 1)
1957 & (nesvnic->nic.sq_size - 1);
1958 }
1959
1960 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1961
1962 /* Destroy NIC QP */
1963 cqp_head = nesdev->cqp.sq_head;
1964 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1965 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1966
1967 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1968 (NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC));
1969 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1970 nesvnic->nic.qp_id);
1971
1972 if (++cqp_head >= nesdev->cqp.sq_size)
1973 cqp_head = 0;
1974
1975 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1976
1977 /* Destroy NIC CQ */
1978 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1979 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1980 (NES_CQP_DESTROY_CQ | ((u32)nesvnic->nic_cq.cq_size << 16)));
1981 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1982 (nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16)));
1983
1984 if (++cqp_head >= nesdev->cqp.sq_size)
1985 cqp_head = 0;
1986
1987 nesdev->cqp.sq_head = cqp_head;
1988 barrier();
1989
1990 /* Ring doorbell (2 WQEs) */
1991 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1992
1993 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1994 nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
1995 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
1996 cqp_head, nesdev->cqp.sq_head,
1997 nesdev->cqp.sq_tail, nesdev->cqp.sq_size);
1998
1999 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
2000 NES_EVENT_TIMEOUT);
2001
2002 nes_debug(NES_DBG_SHUTDOWN, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
2003 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
2004 ret, cqp_head, nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
2005 if (!ret) {
2006 nes_debug(NES_DBG_SHUTDOWN, "NIC QP%u destroy timeout expired\n",
2007 nesvnic->nic.qp_id);
2008 }
2009
2010 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
2011 nesvnic->nic_pbase);
2012
2013 /* restore old wqm_cfg0 value */
2014 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0);
2015 }
2016
2017 /**
2018 * nes_napi_isr
2019 */
2020 int nes_napi_isr(struct nes_device *nesdev)
2021 {
2022 struct nes_adapter *nesadapter = nesdev->nesadapter;
2023 u32 int_stat;
2024
2025 if (nesdev->napi_isr_ran) {
2026 /* interrupt status has already been read in ISR */
2027 int_stat = nesdev->int_stat;
2028 } else {
2029 int_stat = nes_read32(nesdev->regs + NES_INT_STAT);
2030 nesdev->int_stat = int_stat;
2031 nesdev->napi_isr_ran = 1;
2032 }
2033
2034 int_stat &= nesdev->int_req;
2035 /* iff NIC, process here, else wait for DPC */
2036 if ((int_stat) && ((int_stat & 0x0000ff00) == int_stat)) {
2037 nesdev->napi_isr_ran = 0;
2038 nes_write32(nesdev->regs + NES_INT_STAT,
2039 (int_stat &
2040 ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 | NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
2041
2042 /* Process the CEQs */
2043 nes_process_ceq(nesdev, &nesdev->nesadapter->ceq[nesdev->nic_ceq_index]);
2044
2045 if (unlikely((((nesadapter->et_rx_coalesce_usecs_irq) &&
2046 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2047 ((nesadapter->et_use_adaptive_rx_coalesce) &&
2048 (nesdev->deepcq_count > nesadapter->et_pkt_rate_low))))) {
2049 if ((nesdev->int_req & NES_INT_TIMER) == 0) {
2050 /* Enable Periodic timer interrupts */
2051 nesdev->int_req |= NES_INT_TIMER;
2052 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
2053 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
2054 nes_write32(nesdev->regs+NES_TIMER_STAT,
2055 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2056 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2057 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2058 }
2059
2060 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2061 {
2062 nes_nic_init_timer(nesdev);
2063 }
2064 /* Enable interrupts, except CEQs */
2065 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2066 } else {
2067 /* Enable interrupts, make sure timer is off */
2068 nesdev->int_req &= ~NES_INT_TIMER;
2069 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2070 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2071 }
2072 nesdev->deepcq_count = 0;
2073 return 1;
2074 } else {
2075 return 0;
2076 }
2077 }
2078
2079 static void process_critical_error(struct nes_device *nesdev)
2080 {
2081 u32 debug_error;
2082 u32 nes_idx_debug_error_masks0 = 0;
2083 u16 error_module = 0;
2084
2085 debug_error = nes_read_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS);
2086 printk(KERN_ERR PFX "Critical Error reported by device!!! 0x%02X\n",
2087 (u16)debug_error);
2088 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS,
2089 0x01010000 | (debug_error & 0x0000ffff));
2090 if (crit_err_count++ > 10)
2091 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS1, 1 << 0x17);
2092 error_module = (u16) (debug_error & 0x1F00) >> 8;
2093 if (++nesdev->nesadapter->crit_error_count[error_module-1] >=
2094 nes_max_critical_error_count) {
2095 printk(KERN_ERR PFX "Masking off critical error for module "
2096 "0x%02X\n", (u16)error_module);
2097 nes_idx_debug_error_masks0 = nes_read_indexed(nesdev,
2098 NES_IDX_DEBUG_ERROR_MASKS0);
2099 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS0,
2100 nes_idx_debug_error_masks0 | (1 << error_module));
2101 }
2102 }
2103 /**
2104 * nes_dpc
2105 */
2106 void nes_dpc(unsigned long param)
2107 {
2108 struct nes_device *nesdev = (struct nes_device *)param;
2109 struct nes_adapter *nesadapter = nesdev->nesadapter;
2110 u32 counter;
2111 u32 loop_counter = 0;
2112 u32 int_status_bit;
2113 u32 int_stat;
2114 u32 timer_stat;
2115 u32 temp_int_stat;
2116 u32 intf_int_stat;
2117 u32 processed_intf_int = 0;
2118 u16 processed_timer_int = 0;
2119 u16 completion_ints = 0;
2120 u16 timer_ints = 0;
2121
2122 /* nes_debug(NES_DBG_ISR, "\n"); */
2123
2124 do {
2125 timer_stat = 0;
2126 if (nesdev->napi_isr_ran) {
2127 nesdev->napi_isr_ran = 0;
2128 int_stat = nesdev->int_stat;
2129 } else
2130 int_stat = nes_read32(nesdev->regs+NES_INT_STAT);
2131 if (processed_intf_int != 0)
2132 int_stat &= nesdev->int_req & ~NES_INT_INTF;
2133 else
2134 int_stat &= nesdev->int_req;
2135 if (processed_timer_int == 0) {
2136 processed_timer_int = 1;
2137 if (int_stat & NES_INT_TIMER) {
2138 timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
2139 if ((timer_stat & nesdev->timer_int_req) == 0) {
2140 int_stat &= ~NES_INT_TIMER;
2141 }
2142 }
2143 } else {
2144 int_stat &= ~NES_INT_TIMER;
2145 }
2146
2147 if (int_stat) {
2148 if (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2149 NES_INT_MAC1|NES_INT_MAC2 | NES_INT_MAC3)) {
2150 /* Ack the interrupts */
2151 nes_write32(nesdev->regs+NES_INT_STAT,
2152 (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2153 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
2154 }
2155
2156 temp_int_stat = int_stat;
2157 for (counter = 0, int_status_bit = 1; counter < 16; counter++) {
2158 if (int_stat & int_status_bit) {
2159 nes_process_ceq(nesdev, &nesadapter->ceq[counter]);
2160 temp_int_stat &= ~int_status_bit;
2161 completion_ints = 1;
2162 }
2163 if (!(temp_int_stat & 0x0000ffff))
2164 break;
2165 int_status_bit <<= 1;
2166 }
2167
2168 /* Process the AEQ for this pci function */
2169 int_status_bit = 1 << (16 + PCI_FUNC(nesdev->pcidev->devfn));
2170 if (int_stat & int_status_bit) {
2171 nes_process_aeq(nesdev, &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)]);
2172 }
2173
2174 /* Process the MAC interrupt for this pci function */
2175 int_status_bit = 1 << (24 + nesdev->mac_index);
2176 if (int_stat & int_status_bit) {
2177 nes_process_mac_intr(nesdev, nesdev->mac_index);
2178 }
2179
2180 if (int_stat & NES_INT_TIMER) {
2181 if (timer_stat & nesdev->timer_int_req) {
2182 nes_write32(nesdev->regs + NES_TIMER_STAT,
2183 (timer_stat & nesdev->timer_int_req) |
2184 ~(nesdev->nesadapter->timer_int_req));
2185 timer_ints = 1;
2186 }
2187 }
2188
2189 if (int_stat & NES_INT_INTF) {
2190 processed_intf_int = 1;
2191 intf_int_stat = nes_read32(nesdev->regs+NES_INTF_INT_STAT);
2192 intf_int_stat &= nesdev->intf_int_req;
2193 if (NES_INTF_INT_CRITERR & intf_int_stat) {
2194 process_critical_error(nesdev);
2195 }
2196 if (NES_INTF_INT_PCIERR & intf_int_stat) {
2197 printk(KERN_ERR PFX "PCI Error reported by device!!!\n");
2198 BUG();
2199 }
2200 if (NES_INTF_INT_AEQ_OFLOW & intf_int_stat) {
2201 printk(KERN_ERR PFX "AEQ Overflow reported by device!!!\n");
2202 BUG();
2203 }
2204 nes_write32(nesdev->regs+NES_INTF_INT_STAT, intf_int_stat);
2205 }
2206
2207 if (int_stat & NES_INT_TSW) {
2208 }
2209 }
2210 /* Don't use the interface interrupt bit stay in loop */
2211 int_stat &= ~NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 |
2212 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3;
2213 } while ((int_stat != 0) && (loop_counter++ < MAX_DPC_ITERATIONS));
2214
2215 if (timer_ints == 1) {
2216 if ((nesadapter->et_rx_coalesce_usecs_irq) || (nesadapter->et_use_adaptive_rx_coalesce)) {
2217 if (completion_ints == 0) {
2218 nesdev->timer_only_int_count++;
2219 if (nesdev->timer_only_int_count>=nesadapter->timer_int_limit) {
2220 nesdev->timer_only_int_count = 0;
2221 nesdev->int_req &= ~NES_INT_TIMER;
2222 nes_write32(nesdev->regs + NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2223 nes_write32(nesdev->regs + NES_INT_MASK, ~nesdev->int_req);
2224 } else {
2225 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2226 }
2227 } else {
2228 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2229 {
2230 nes_nic_init_timer(nesdev);
2231 }
2232 nesdev->timer_only_int_count = 0;
2233 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2234 }
2235 } else {
2236 nesdev->timer_only_int_count = 0;
2237 nesdev->int_req &= ~NES_INT_TIMER;
2238 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2239 nes_write32(nesdev->regs+NES_TIMER_STAT,
2240 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2241 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2242 }
2243 } else {
2244 if ( (completion_ints == 1) &&
2245 (((nesadapter->et_rx_coalesce_usecs_irq) &&
2246 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2247 ((nesdev->deepcq_count > nesadapter->et_pkt_rate_low) &&
2248 (nesadapter->et_use_adaptive_rx_coalesce) )) ) {
2249 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
2250 nesdev->timer_only_int_count = 0;
2251 nesdev->int_req |= NES_INT_TIMER;
2252 nes_write32(nesdev->regs+NES_TIMER_STAT,
2253 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2254 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2255 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2256 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2257 } else {
2258 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2259 }
2260 }
2261 nesdev->deepcq_count = 0;
2262 }
2263
2264
2265 /**
2266 * nes_process_ceq
2267 */
2268 static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq)
2269 {
2270 u64 u64temp;
2271 struct nes_hw_cq *cq;
2272 u32 head;
2273 u32 ceq_size;
2274
2275 /* nes_debug(NES_DBG_CQ, "\n"); */
2276 head = ceq->ceq_head;
2277 ceq_size = ceq->ceq_size;
2278
2279 do {
2280 if (le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]) &
2281 NES_CEQE_VALID) {
2282 u64temp = (((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]))) << 32) |
2283 ((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_LOW_IDX])));
2284 u64temp <<= 1;
2285 cq = *((struct nes_hw_cq **)&u64temp);
2286 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
2287 barrier();
2288 ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX] = 0;
2289
2290 /* call the event handler */
2291 cq->ce_handler(nesdev, cq);
2292
2293 if (++head >= ceq_size)
2294 head = 0;
2295 } else {
2296 break;
2297 }
2298
2299 } while (1);
2300
2301 ceq->ceq_head = head;
2302 }
2303
2304
2305 /**
2306 * nes_process_aeq
2307 */
2308 static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq)
2309 {
2310 /* u64 u64temp; */
2311 u32 head;
2312 u32 aeq_size;
2313 u32 aeqe_misc;
2314 u32 aeqe_cq_id;
2315 struct nes_hw_aeqe volatile *aeqe;
2316
2317 head = aeq->aeq_head;
2318 aeq_size = aeq->aeq_size;
2319
2320 do {
2321 aeqe = &aeq->aeq_vbase[head];
2322 if ((le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]) & NES_AEQE_VALID) == 0)
2323 break;
2324 aeqe_misc = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
2325 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
2326 if (aeqe_misc & (NES_AEQE_QP|NES_AEQE_CQ)) {
2327 if (aeqe_cq_id >= NES_FIRST_QPN) {
2328 /* dealing with an accelerated QP related AE */
2329 /*
2330 * u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX]))) << 32) |
2331 * ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
2332 */
2333 nes_process_iwarp_aeqe(nesdev, (struct nes_hw_aeqe *)aeqe);
2334 } else {
2335 /* TODO: dealing with a CQP related AE */
2336 nes_debug(NES_DBG_AEQ, "Processing CQP related AE, misc = 0x%04X\n",
2337 (u16)(aeqe_misc >> 16));
2338 }
2339 }
2340
2341 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = 0;
2342
2343 if (++head >= aeq_size)
2344 head = 0;
2345
2346 nes_write32(nesdev->regs + NES_AEQ_ALLOC, 1 << 16);
2347 }
2348 while (1);
2349 aeq->aeq_head = head;
2350 }
2351
2352 static void nes_reset_link(struct nes_device *nesdev, u32 mac_index)
2353 {
2354 struct nes_adapter *nesadapter = nesdev->nesadapter;
2355 u32 reset_value;
2356 u32 i=0;
2357 u32 u32temp;
2358
2359 if (nesadapter->hw_rev == NE020_REV) {
2360 return;
2361 }
2362 mh_detected++;
2363
2364 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
2365
2366 if ((mac_index == 0) || ((mac_index == 1) && (nesadapter->OneG_Mode)))
2367 reset_value |= 0x0000001d;
2368 else
2369 reset_value |= 0x0000002d;
2370
2371 if (4 <= (nesadapter->link_interrupt_count[mac_index] / ((u16)NES_MAX_LINK_INTERRUPTS))) {
2372 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
2373 nesadapter->link_interrupt_count[0] = 0;
2374 nesadapter->link_interrupt_count[1] = 0;
2375 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2376 if (0x00000040 & u32temp)
2377 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2378 else
2379 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2380
2381 reset_value |= 0x0000003d;
2382 }
2383 nesadapter->link_interrupt_count[mac_index] = 0;
2384 }
2385
2386 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2387
2388 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
2389 & 0x00000040) != 0x00000040) && (i++ < 5000));
2390
2391 if (0x0000003d == (reset_value & 0x0000003d)) {
2392 u32 pcs_control_status0, pcs_control_status1;
2393
2394 for (i = 0; i < 10; i++) {
2395 pcs_control_status0 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0);
2396 pcs_control_status1 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2397 if (((0x0F000000 == (pcs_control_status0 & 0x0F000000))
2398 && (pcs_control_status0 & 0x00100000))
2399 || ((0x0F000000 == (pcs_control_status1 & 0x0F000000))
2400 && (pcs_control_status1 & 0x00100000)))
2401 continue;
2402 else
2403 break;
2404 }
2405 if (10 == i) {
2406 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2407 if (0x00000040 & u32temp)
2408 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2409 else
2410 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2411
2412 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2413
2414 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET)
2415 & 0x00000040) != 0x00000040) && (i++ < 5000));
2416 }
2417 }
2418 }
2419
2420 /**
2421 * nes_process_mac_intr
2422 */
2423 static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2424 {
2425 unsigned long flags;
2426 u32 pcs_control_status;
2427 struct nes_adapter *nesadapter = nesdev->nesadapter;
2428 struct nes_vnic *nesvnic;
2429 u32 mac_status;
2430 u32 mac_index = nesdev->mac_index;
2431 u32 u32temp;
2432 u16 phy_data;
2433 u16 temp_phy_data;
2434 u32 pcs_val = 0x0f0f0000;
2435 u32 pcs_mask = 0x0f1f0000;
2436 u32 cdr_ctrl;
2437
2438 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2439 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
2440 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2441 return;
2442 }
2443 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_INTERRUPT;
2444
2445 /* ack the MAC interrupt */
2446 mac_status = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200));
2447 /* Clear the interrupt */
2448 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200), mac_status);
2449
2450 nes_debug(NES_DBG_PHY, "MAC%u interrupt status = 0x%X.\n", mac_number, mac_status);
2451
2452 if (mac_status & (NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT)) {
2453 nesdev->link_status_interrupts++;
2454 if (0 == (++nesadapter->link_interrupt_count[mac_index] % ((u16)NES_MAX_LINK_INTERRUPTS)))
2455 nes_reset_link(nesdev, mac_index);
2456
2457 /* read the PHY interrupt status register */
2458 if ((nesadapter->OneG_Mode) &&
2459 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
2460 do {
2461 nes_read_1G_phy_reg(nesdev, 0x1a,
2462 nesadapter->phy_index[mac_index], &phy_data);
2463 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1a = 0x%X.\n",
2464 nesadapter->phy_index[mac_index], phy_data);
2465 } while (phy_data&0x8000);
2466
2467 temp_phy_data = 0;
2468 do {
2469 nes_read_1G_phy_reg(nesdev, 0x11,
2470 nesadapter->phy_index[mac_index], &phy_data);
2471 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x11 = 0x%X.\n",
2472 nesadapter->phy_index[mac_index], phy_data);
2473 if (temp_phy_data == phy_data)
2474 break;
2475 temp_phy_data = phy_data;
2476 } while (1);
2477
2478 nes_read_1G_phy_reg(nesdev, 0x1e,
2479 nesadapter->phy_index[mac_index], &phy_data);
2480 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1e = 0x%X.\n",
2481 nesadapter->phy_index[mac_index], phy_data);
2482
2483 nes_read_1G_phy_reg(nesdev, 1,
2484 nesadapter->phy_index[mac_index], &phy_data);
2485 nes_debug(NES_DBG_PHY, "1G phy%u data from register 1 = 0x%X\n",
2486 nesadapter->phy_index[mac_index], phy_data);
2487
2488 if (temp_phy_data & 0x1000) {
2489 nes_debug(NES_DBG_PHY, "The Link is up according to the PHY\n");
2490 phy_data = 4;
2491 } else {
2492 nes_debug(NES_DBG_PHY, "The Link is down according to the PHY\n");
2493 }
2494 }
2495 nes_debug(NES_DBG_PHY, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2496 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0),
2497 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0+0x200));
2498
2499 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_PUMA_1G) {
2500 switch (mac_index) {
2501 case 1:
2502 case 3:
2503 pcs_control_status = nes_read_indexed(nesdev,
2504 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2505 break;
2506 default:
2507 pcs_control_status = nes_read_indexed(nesdev,
2508 NES_IDX_PHY_PCS_CONTROL_STATUS0);
2509 break;
2510 }
2511 } else {
2512 pcs_control_status = nes_read_indexed(nesdev,
2513 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2514 pcs_control_status = nes_read_indexed(nesdev,
2515 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2516 }
2517
2518 nes_debug(NES_DBG_PHY, "PCS PHY Control/Status%u: 0x%08X\n",
2519 mac_index, pcs_control_status);
2520 if ((nesadapter->OneG_Mode) &&
2521 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
2522 u32temp = 0x01010000;
2523 if (nesadapter->port_count > 2) {
2524 u32temp |= 0x02020000;
2525 }
2526 if ((pcs_control_status & u32temp)!= u32temp) {
2527 phy_data = 0;
2528 nes_debug(NES_DBG_PHY, "PCS says the link is down\n");
2529 }
2530 } else {
2531 switch (nesadapter->phy_type[mac_index]) {
2532 case NES_PHY_TYPE_ARGUS:
2533 case NES_PHY_TYPE_SFP_D:
2534 case NES_PHY_TYPE_KR:
2535 /* clear the alarms */
2536 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008);
2537 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001);
2538 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc002);
2539 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc005);
2540 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc006);
2541 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2542 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2543 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2544 /* check link status */
2545 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2546 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2547
2548 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2549 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2550 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2551 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2552
2553 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2554
2555 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2556 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2557 break;
2558
2559 case NES_PHY_TYPE_PUMA_1G:
2560 if (mac_index < 2)
2561 pcs_val = pcs_mask = 0x01010000;
2562 else
2563 pcs_val = pcs_mask = 0x02020000;
2564 /* fall through */
2565 default:
2566 phy_data = (pcs_val == (pcs_control_status & pcs_mask)) ? 0x4 : 0x0;
2567 break;
2568 }
2569 }
2570
2571 if (phy_data & 0x0004) {
2572 if (wide_ppm_offset &&
2573 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2574 (nesadapter->hw_rev != NE020_REV)) {
2575 cdr_ctrl = nes_read_indexed(nesdev,
2576 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2577 mac_index * 0x200);
2578 nes_write_indexed(nesdev,
2579 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2580 mac_index * 0x200,
2581 cdr_ctrl | 0x000F0000);
2582 }
2583 nesadapter->mac_link_down[mac_index] = 0;
2584 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2585 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
2586 nesvnic->linkup);
2587 if (nesvnic->linkup == 0) {
2588 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2589 nesvnic->netdev->name, nesvnic->netdev);
2590 if (netif_queue_stopped(nesvnic->netdev))
2591 netif_start_queue(nesvnic->netdev);
2592 nesvnic->linkup = 1;
2593 netif_carrier_on(nesvnic->netdev);
2594
2595 spin_lock(&nesvnic->port_ibevent_lock);
2596 if (nesvnic->of_device_registered) {
2597 if (nesdev->iw_status == 0) {
2598 nesdev->iw_status = 1;
2599 nes_port_ibevent(nesvnic);
2600 }
2601 }
2602 spin_unlock(&nesvnic->port_ibevent_lock);
2603 }
2604 }
2605 } else {
2606 if (wide_ppm_offset &&
2607 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2608 (nesadapter->hw_rev != NE020_REV)) {
2609 cdr_ctrl = nes_read_indexed(nesdev,
2610 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2611 mac_index * 0x200);
2612 nes_write_indexed(nesdev,
2613 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2614 mac_index * 0x200,
2615 cdr_ctrl & 0xFFF0FFFF);
2616 }
2617 nesadapter->mac_link_down[mac_index] = 1;
2618 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2619 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
2620 nesvnic->linkup);
2621 if (nesvnic->linkup == 1) {
2622 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2623 nesvnic->netdev->name, nesvnic->netdev);
2624 if (!(netif_queue_stopped(nesvnic->netdev)))
2625 netif_stop_queue(nesvnic->netdev);
2626 nesvnic->linkup = 0;
2627 netif_carrier_off(nesvnic->netdev);
2628
2629 spin_lock(&nesvnic->port_ibevent_lock);
2630 if (nesvnic->of_device_registered) {
2631 if (nesdev->iw_status == 1) {
2632 nesdev->iw_status = 0;
2633 nes_port_ibevent(nesvnic);
2634 }
2635 }
2636 spin_unlock(&nesvnic->port_ibevent_lock);
2637 }
2638 }
2639 }
2640 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_SFP_D) {
2641 nesdev->link_recheck = 1;
2642 mod_delayed_work(system_wq, &nesdev->work,
2643 NES_LINK_RECHECK_DELAY);
2644 }
2645 }
2646
2647 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2648
2649 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_IDLE;
2650 }
2651
2652 void nes_recheck_link_status(struct work_struct *work)
2653 {
2654 unsigned long flags;
2655 struct nes_device *nesdev = container_of(work, struct nes_device, work.work);
2656 struct nes_adapter *nesadapter = nesdev->nesadapter;
2657 struct nes_vnic *nesvnic;
2658 u32 mac_index = nesdev->mac_index;
2659 u16 phy_data;
2660 u16 temp_phy_data;
2661
2662 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2663
2664 /* check link status */
2665 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2666 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2667
2668 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2669 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2670 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2671 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2672
2673 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2674
2675 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2676 __func__, phy_data,
2677 nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2678
2679 if (phy_data & 0x0004) {
2680 nesadapter->mac_link_down[mac_index] = 0;
2681 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2682 if (nesvnic->linkup == 0) {
2683 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2684 nesvnic->netdev->name, nesvnic->netdev);
2685 if (netif_queue_stopped(nesvnic->netdev))
2686 netif_start_queue(nesvnic->netdev);
2687 nesvnic->linkup = 1;
2688 netif_carrier_on(nesvnic->netdev);
2689
2690 spin_lock(&nesvnic->port_ibevent_lock);
2691 if (nesvnic->of_device_registered) {
2692 if (nesdev->iw_status == 0) {
2693 nesdev->iw_status = 1;
2694 nes_port_ibevent(nesvnic);
2695 }
2696 }
2697 spin_unlock(&nesvnic->port_ibevent_lock);
2698 }
2699 }
2700
2701 } else {
2702 nesadapter->mac_link_down[mac_index] = 1;
2703 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2704 if (nesvnic->linkup == 1) {
2705 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2706 nesvnic->netdev->name, nesvnic->netdev);
2707 if (!(netif_queue_stopped(nesvnic->netdev)))
2708 netif_stop_queue(nesvnic->netdev);
2709 nesvnic->linkup = 0;
2710 netif_carrier_off(nesvnic->netdev);
2711
2712 spin_lock(&nesvnic->port_ibevent_lock);
2713 if (nesvnic->of_device_registered) {
2714 if (nesdev->iw_status == 1) {
2715 nesdev->iw_status = 0;
2716 nes_port_ibevent(nesvnic);
2717 }
2718 }
2719 spin_unlock(&nesvnic->port_ibevent_lock);
2720 }
2721 }
2722 }
2723 if (nesdev->link_recheck++ < NES_LINK_RECHECK_MAX)
2724 schedule_delayed_work(&nesdev->work, NES_LINK_RECHECK_DELAY);
2725 else
2726 nesdev->link_recheck = 0;
2727
2728 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2729 }
2730
2731
2732 static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2733 {
2734 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2735
2736 napi_schedule(&nesvnic->napi);
2737 }
2738
2739
2740 /* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2741 * getting out of nic_ce_handler
2742 */
2743 #define MAX_RQES_TO_PROCESS 384
2744
2745 /**
2746 * nes_nic_ce_handler
2747 */
2748 void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2749 {
2750 u64 u64temp;
2751 dma_addr_t bus_address;
2752 struct nes_hw_nic *nesnic;
2753 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2754 struct nes_adapter *nesadapter = nesdev->nesadapter;
2755 struct nes_hw_nic_rq_wqe *nic_rqe;
2756 struct nes_hw_nic_sq_wqe *nic_sqe;
2757 struct sk_buff *skb;
2758 struct sk_buff *rx_skb;
2759 struct nes_rskb_cb *cb;
2760 __le16 *wqe_fragment_length;
2761 u32 head;
2762 u32 cq_size;
2763 u32 rx_pkt_size;
2764 u32 cqe_count=0;
2765 u32 cqe_errv;
2766 u32 cqe_misc;
2767 u16 wqe_fragment_index = 1; /* first fragment (0) is used by copy buffer */
2768 u16 vlan_tag;
2769 u16 pkt_type;
2770 u16 rqes_processed = 0;
2771 u8 sq_cqes = 0;
2772
2773 head = cq->cq_head;
2774 cq_size = cq->cq_size;
2775 cq->cqes_pending = 1;
2776 do {
2777 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]) &
2778 NES_NIC_CQE_VALID) {
2779 nesnic = &nesvnic->nic;
2780 cqe_misc = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]);
2781 if (cqe_misc & NES_NIC_CQE_SQ) {
2782 sq_cqes++;
2783 wqe_fragment_index = 1;
2784 nic_sqe = &nesnic->sq_vbase[nesnic->sq_tail];
2785 skb = nesnic->tx_skb[nesnic->sq_tail];
2786 wqe_fragment_length = (__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
2787 /* bump past the vlan tag */
2788 wqe_fragment_length++;
2789 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
2790 u64temp = (u64) le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2791 wqe_fragment_index * 2]);
2792 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX +
2793 wqe_fragment_index * 2])) << 32;
2794 bus_address = (dma_addr_t)u64temp;
2795 if (test_and_clear_bit(nesnic->sq_tail, nesnic->first_frag_overflow)) {
2796 pci_unmap_single(nesdev->pcidev,
2797 bus_address,
2798 le16_to_cpu(wqe_fragment_length[wqe_fragment_index++]),
2799 PCI_DMA_TODEVICE);
2800 }
2801 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
2802 if (wqe_fragment_length[wqe_fragment_index]) {
2803 u64temp = le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2804 wqe_fragment_index * 2]);
2805 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
2806 + wqe_fragment_index * 2])) <<32;
2807 bus_address = (dma_addr_t)u64temp;
2808 pci_unmap_page(nesdev->pcidev,
2809 bus_address,
2810 le16_to_cpu(wqe_fragment_length[wqe_fragment_index]),
2811 PCI_DMA_TODEVICE);
2812 } else
2813 break;
2814 }
2815 }
2816 if (skb)
2817 dev_kfree_skb_any(skb);
2818 nesnic->sq_tail++;
2819 nesnic->sq_tail &= nesnic->sq_size-1;
2820 if (sq_cqes > 128) {
2821 barrier();
2822 /* restart the queue if it had been stopped */
2823 if (netif_queue_stopped(nesvnic->netdev))
2824 netif_wake_queue(nesvnic->netdev);
2825 sq_cqes = 0;
2826 }
2827 } else {
2828 rqes_processed ++;
2829
2830 cq->rx_cqes_completed++;
2831 cq->rx_pkts_indicated++;
2832 rx_pkt_size = cqe_misc & 0x0000ffff;
2833 nic_rqe = &nesnic->rq_vbase[nesnic->rq_tail];
2834 /* Get the skb */
2835 rx_skb = nesnic->rx_skb[nesnic->rq_tail];
2836 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_tail];
2837 bus_address = (dma_addr_t)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
2838 bus_address += ((u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX])) << 32;
2839 pci_unmap_single(nesdev->pcidev, bus_address,
2840 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
2841 cb = (struct nes_rskb_cb *)&rx_skb->cb[0];
2842 cb->busaddr = 0;
2843 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2844 /* rx_skb->len = rx_pkt_size; */
2845 rx_skb->len = 0; /* TODO: see if this is necessary */
2846 skb_put(rx_skb, rx_pkt_size);
2847 rx_skb->protocol = eth_type_trans(rx_skb, nesvnic->netdev);
2848 nesnic->rq_tail++;
2849 nesnic->rq_tail &= nesnic->rq_size - 1;
2850
2851 atomic_inc(&nesvnic->rx_skbs_needed);
2852 if (atomic_read(&nesvnic->rx_skbs_needed) > (nesvnic->nic.rq_size>>1)) {
2853 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2854 cq->cq_number | (cqe_count << 16));
2855 /* nesadapter->tune_timer.cq_count += cqe_count; */
2856 nesdev->currcq_count += cqe_count;
2857 cqe_count = 0;
2858 nes_replenish_nic_rq(nesvnic);
2859 }
2860 pkt_type = (u16)(le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX]));
2861 cqe_errv = (cqe_misc & NES_NIC_CQE_ERRV_MASK) >> NES_NIC_CQE_ERRV_SHIFT;
2862 rx_skb->ip_summed = CHECKSUM_NONE;
2863
2864 if ((NES_PKT_TYPE_TCPV4_BITS == (pkt_type & NES_PKT_TYPE_TCPV4_MASK)) ||
2865 (NES_PKT_TYPE_UDPV4_BITS == (pkt_type & NES_PKT_TYPE_UDPV4_MASK))) {
2866 if ((cqe_errv &
2867 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
2868 NES_NIC_ERRV_BITS_IPH_ERR | NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2869 if (nesvnic->netdev->features & NETIF_F_RXCSUM)
2870 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2871 } else
2872 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2873 " errv = 0x%X, pkt_type = 0x%X.\n",
2874 nesvnic->netdev->name, cqe_errv, pkt_type);
2875
2876 } else if ((pkt_type & NES_PKT_TYPE_IPV4_MASK) == NES_PKT_TYPE_IPV4_BITS) {
2877 if ((cqe_errv &
2878 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_IPH_ERR |
2879 NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
2880 if (nesvnic->netdev->features & NETIF_F_RXCSUM) {
2881 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2882 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2883 nesvnic->netdev->name); */
2884 }
2885 } else
2886 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2887 " errv = 0x%X, pkt_type = 0x%X.\n",
2888 nesvnic->netdev->name, cqe_errv, pkt_type);
2889 }
2890 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2891 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2892
2893 if ((pkt_type & NES_PKT_TYPE_APBVT_MASK) == NES_PKT_TYPE_APBVT_BITS) {
2894 if (nes_cm_recv(rx_skb, nesvnic->netdev))
2895 rx_skb = NULL;
2896 }
2897 if (rx_skb == NULL)
2898 goto skip_rx_indicate0;
2899
2900
2901 if (cqe_misc & NES_NIC_CQE_TAG_VALID) {
2902 vlan_tag = (u16)(le32_to_cpu(
2903 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX])
2904 >> 16);
2905 nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2906 nesvnic->netdev->name, vlan_tag);
2907
2908 __vlan_hwaccel_put_tag(rx_skb, htons(ETH_P_8021Q), vlan_tag);
2909 }
2910 napi_gro_receive(&nesvnic->napi, rx_skb);
2911
2912 skip_rx_indicate0:
2913 ;
2914 /* nesvnic->netstats.rx_packets++; */
2915 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2916 }
2917
2918 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX] = 0;
2919 /* Accounting... */
2920 cqe_count++;
2921 if (++head >= cq_size)
2922 head = 0;
2923 if (cqe_count == 255) {
2924 /* Replenish Nic CQ */
2925 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2926 cq->cq_number | (cqe_count << 16));
2927 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2928 nesdev->currcq_count += cqe_count;
2929 cqe_count = 0;
2930 }
2931
2932 if (cq->rx_cqes_completed >= nesvnic->budget)
2933 break;
2934 } else {
2935 cq->cqes_pending = 0;
2936 break;
2937 }
2938
2939 } while (1);
2940
2941 if (sq_cqes) {
2942 barrier();
2943 /* restart the queue if it had been stopped */
2944 if (netif_queue_stopped(nesvnic->netdev))
2945 netif_wake_queue(nesvnic->netdev);
2946 }
2947 cq->cq_head = head;
2948 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
2949 cq->cq_number, cqe_count, cq->cq_head); */
2950 cq->cqe_allocs_pending = cqe_count;
2951 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2952 {
2953 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2954 nesdev->currcq_count += cqe_count;
2955 nes_nic_tune_timer(nesdev);
2956 }
2957 if (atomic_read(&nesvnic->rx_skbs_needed))
2958 nes_replenish_nic_rq(nesvnic);
2959 }
2960
2961
2962
2963 /**
2964 * nes_cqp_ce_handler
2965 */
2966 static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
2967 {
2968 u64 u64temp;
2969 unsigned long flags;
2970 struct nes_hw_cqp *cqp = NULL;
2971 struct nes_cqp_request *cqp_request;
2972 struct nes_hw_cqp_wqe *cqp_wqe;
2973 u32 head;
2974 u32 cq_size;
2975 u32 cqe_count=0;
2976 u32 error_code;
2977 u32 opcode;
2978 u32 ctx_index;
2979 /* u32 counter; */
2980
2981 head = cq->cq_head;
2982 cq_size = cq->cq_size;
2983
2984 do {
2985 /* process the CQE */
2986 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
2987 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
2988
2989 opcode = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX]);
2990 if (opcode & NES_CQE_VALID) {
2991 cqp = &nesdev->cqp;
2992
2993 error_code = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_ERROR_CODE_IDX]);
2994 if (error_code) {
2995 nes_debug(NES_DBG_CQP, "Bad Completion code for opcode 0x%02X from CQP,"
2996 " Major/Minor codes = 0x%04X:%04X.\n",
2997 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])&0x3f,
2998 (u16)(error_code >> 16),
2999 (u16)error_code);
3000 }
3001
3002 u64temp = (((u64)(le32_to_cpu(cq->cq_vbase[head].
3003 cqe_words[NES_CQE_COMP_COMP_CTX_HIGH_IDX]))) << 32) |
3004 ((u64)(le32_to_cpu(cq->cq_vbase[head].
3005 cqe_words[NES_CQE_COMP_COMP_CTX_LOW_IDX])));
3006
3007 cqp_request = (struct nes_cqp_request *)(unsigned long)u64temp;
3008 if (cqp_request) {
3009 if (cqp_request->waiting) {
3010 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
3011 cqp_request->major_code = (u16)(error_code >> 16);
3012 cqp_request->minor_code = (u16)error_code;
3013 barrier();
3014 cqp_request->request_done = 1;
3015 wake_up(&cqp_request->waitq);
3016 nes_put_cqp_request(nesdev, cqp_request);
3017 } else {
3018 if (cqp_request->callback)
3019 cqp_request->cqp_callback(nesdev, cqp_request);
3020 nes_free_cqp_request(nesdev, cqp_request);
3021 }
3022 } else {
3023 wake_up(&nesdev->cqp.waitq);
3024 }
3025
3026 cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX] = 0;
3027 nes_write32(nesdev->regs + NES_CQE_ALLOC, cq->cq_number | (1 << 16));
3028 if (++cqp->sq_tail >= cqp->sq_size)
3029 cqp->sq_tail = 0;
3030
3031 /* Accounting... */
3032 cqe_count++;
3033 if (++head >= cq_size)
3034 head = 0;
3035 } else {
3036 break;
3037 }
3038 } while (1);
3039 cq->cq_head = head;
3040
3041 spin_lock_irqsave(&nesdev->cqp.lock, flags);
3042 while ((!list_empty(&nesdev->cqp_pending_reqs)) &&
3043 ((((nesdev->cqp.sq_tail+nesdev->cqp.sq_size)-nesdev->cqp.sq_head) &
3044 (nesdev->cqp.sq_size - 1)) != 1)) {
3045 cqp_request = list_entry(nesdev->cqp_pending_reqs.next,
3046 struct nes_cqp_request, list);
3047 list_del_init(&cqp_request->list);
3048 head = nesdev->cqp.sq_head++;
3049 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
3050 cqp_wqe = &nesdev->cqp.sq_vbase[head];
3051 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
3052 barrier();
3053
3054 opcode = le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX]);
3055 if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
3056 ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
3057 else
3058 ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
3059 cqp_wqe->wqe_words[ctx_index] =
3060 cpu_to_le32((u32)((unsigned long)cqp_request));
3061 cqp_wqe->wqe_words[ctx_index + 1] =
3062 cpu_to_le32((u32)(upper_32_bits((unsigned long)cqp_request)));
3063 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
3064 cqp_request, le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f, head);
3065 /* Ring doorbell (1 WQEs) */
3066 barrier();
3067 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
3068 }
3069 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
3070
3071 /* Arm the CCQ */
3072 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
3073 cq->cq_number);
3074 nes_read32(nesdev->regs+NES_CQE_ALLOC);
3075 }
3076
3077 static u8 *locate_mpa(u8 *pkt, u32 aeq_info)
3078 {
3079 if (aeq_info & NES_AEQE_Q2_DATA_ETHERNET) {
3080 /* skip over ethernet header */
3081 pkt += ETH_HLEN;
3082
3083 /* Skip over IP and TCP headers */
3084 pkt += 4 * (pkt[0] & 0x0f);
3085 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
3086 }
3087 return pkt;
3088 }
3089
3090 /* Determine if incoming error pkt is rdma layer */
3091 static u32 iwarp_opcode(struct nes_qp *nesqp, u32 aeq_info)
3092 {
3093 u8 *pkt;
3094 u16 *mpa;
3095 u32 opcode = 0xffffffff;
3096
3097 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3098 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3099 mpa = (u16 *)locate_mpa(pkt, aeq_info);
3100 opcode = be16_to_cpu(mpa[1]) & 0xf;
3101 }
3102
3103 return opcode;
3104 }
3105
3106 /* Build iWARP terminate header */
3107 static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 aeq_info)
3108 {
3109 u8 *pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3110 u16 ddp_seg_len;
3111 int copy_len = 0;
3112 u8 is_tagged = 0;
3113 u8 flush_code = 0;
3114 struct nes_terminate_hdr *termhdr;
3115
3116 termhdr = (struct nes_terminate_hdr *)nesqp->hwqp.q2_vbase;
3117 memset(termhdr, 0, 64);
3118
3119 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3120
3121 /* Use data from offending packet to fill in ddp & rdma hdrs */
3122 pkt = locate_mpa(pkt, aeq_info);
3123 ddp_seg_len = be16_to_cpu(*(u16 *)pkt);
3124 if (ddp_seg_len) {
3125 copy_len = 2;
3126 termhdr->hdrct = DDP_LEN_FLAG;
3127 if (pkt[2] & 0x80) {
3128 is_tagged = 1;
3129 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
3130 copy_len += TERM_DDP_LEN_TAGGED;
3131 termhdr->hdrct |= DDP_HDR_FLAG;
3132 }
3133 } else {
3134 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
3135 copy_len += TERM_DDP_LEN_UNTAGGED;
3136 termhdr->hdrct |= DDP_HDR_FLAG;
3137 }
3138
3139 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
3140 if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
3141 copy_len += TERM_RDMA_LEN;
3142 termhdr->hdrct |= RDMA_HDR_FLAG;
3143 }
3144 }
3145 }
3146 }
3147 }
3148
3149 switch (async_event_id) {
3150 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
3151 switch (iwarp_opcode(nesqp, aeq_info)) {
3152 case IWARP_OPCODE_WRITE:
3153 flush_code = IB_WC_LOC_PROT_ERR;
3154 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3155 termhdr->error_code = DDP_TAGGED_INV_STAG;
3156 break;
3157 default:
3158 flush_code = IB_WC_REM_ACCESS_ERR;
3159 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3160 termhdr->error_code = RDMAP_INV_STAG;
3161 }
3162 break;
3163 case NES_AEQE_AEID_AMP_INVALID_STAG:
3164 flush_code = IB_WC_REM_ACCESS_ERR;
3165 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3166 termhdr->error_code = RDMAP_INV_STAG;
3167 break;
3168 case NES_AEQE_AEID_AMP_BAD_QP:
3169 flush_code = IB_WC_LOC_QP_OP_ERR;
3170 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3171 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3172 break;
3173 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3174 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3175 switch (iwarp_opcode(nesqp, aeq_info)) {
3176 case IWARP_OPCODE_SEND_INV:
3177 case IWARP_OPCODE_SEND_SE_INV:
3178 flush_code = IB_WC_REM_OP_ERR;
3179 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3180 termhdr->error_code = RDMAP_CANT_INV_STAG;
3181 break;
3182 default:
3183 flush_code = IB_WC_REM_ACCESS_ERR;
3184 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3185 termhdr->error_code = RDMAP_INV_STAG;
3186 }
3187 break;
3188 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3189 if (aeq_info & (NES_AEQE_Q2_DATA_ETHERNET | NES_AEQE_Q2_DATA_MPA)) {
3190 flush_code = IB_WC_LOC_PROT_ERR;
3191 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3192 termhdr->error_code = DDP_TAGGED_BOUNDS;
3193 } else {
3194 flush_code = IB_WC_REM_ACCESS_ERR;
3195 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3196 termhdr->error_code = RDMAP_INV_BOUNDS;
3197 }
3198 break;
3199 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3200 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3201 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
3202 flush_code = IB_WC_REM_ACCESS_ERR;
3203 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3204 termhdr->error_code = RDMAP_ACCESS;
3205 break;
3206 case NES_AEQE_AEID_AMP_TO_WRAP:
3207 flush_code = IB_WC_REM_ACCESS_ERR;
3208 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3209 termhdr->error_code = RDMAP_TO_WRAP;
3210 break;
3211 case NES_AEQE_AEID_AMP_BAD_PD:
3212 switch (iwarp_opcode(nesqp, aeq_info)) {
3213 case IWARP_OPCODE_WRITE:
3214 flush_code = IB_WC_LOC_PROT_ERR;
3215 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3216 termhdr->error_code = DDP_TAGGED_UNASSOC_STAG;
3217 break;
3218 case IWARP_OPCODE_SEND_INV:
3219 case IWARP_OPCODE_SEND_SE_INV:
3220 flush_code = IB_WC_REM_ACCESS_ERR;
3221 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3222 termhdr->error_code = RDMAP_CANT_INV_STAG;
3223 break;
3224 default:
3225 flush_code = IB_WC_REM_ACCESS_ERR;
3226 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3227 termhdr->error_code = RDMAP_UNASSOC_STAG;
3228 }
3229 break;
3230 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3231 flush_code = IB_WC_LOC_LEN_ERR;
3232 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3233 termhdr->error_code = MPA_MARKER;
3234 break;
3235 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3236 flush_code = IB_WC_GENERAL_ERR;
3237 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3238 termhdr->error_code = MPA_CRC;
3239 break;
3240 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3241 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3242 flush_code = IB_WC_LOC_LEN_ERR;
3243 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3244 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3245 break;
3246 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3247 case NES_AEQE_AEID_DDP_NO_L_BIT:
3248 flush_code = IB_WC_FATAL_ERR;
3249 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3250 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3251 break;
3252 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3253 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3254 flush_code = IB_WC_GENERAL_ERR;
3255 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3256 termhdr->error_code = DDP_UNTAGGED_INV_MSN_RANGE;
3257 break;
3258 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3259 flush_code = IB_WC_LOC_LEN_ERR;
3260 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3261 termhdr->error_code = DDP_UNTAGGED_INV_TOO_LONG;
3262 break;
3263 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3264 flush_code = IB_WC_GENERAL_ERR;
3265 if (is_tagged) {
3266 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3267 termhdr->error_code = DDP_TAGGED_INV_DDP_VER;
3268 } else {
3269 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3270 termhdr->error_code = DDP_UNTAGGED_INV_DDP_VER;
3271 }
3272 break;
3273 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3274 flush_code = IB_WC_GENERAL_ERR;
3275 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3276 termhdr->error_code = DDP_UNTAGGED_INV_MO;
3277 break;
3278 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3279 flush_code = IB_WC_REM_OP_ERR;
3280 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3281 termhdr->error_code = DDP_UNTAGGED_INV_MSN_NO_BUF;
3282 break;
3283 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
3284 flush_code = IB_WC_GENERAL_ERR;
3285 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3286 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3287 break;
3288 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3289 flush_code = IB_WC_GENERAL_ERR;
3290 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3291 termhdr->error_code = RDMAP_INV_RDMAP_VER;
3292 break;
3293 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3294 flush_code = IB_WC_LOC_QP_OP_ERR;
3295 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3296 termhdr->error_code = RDMAP_UNEXPECTED_OP;
3297 break;
3298 default:
3299 flush_code = IB_WC_FATAL_ERR;
3300 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3301 termhdr->error_code = RDMAP_UNSPECIFIED;
3302 break;
3303 }
3304
3305 if (copy_len)
3306 memcpy(termhdr + 1, pkt, copy_len);
3307
3308 if ((flush_code) && ((NES_AEQE_INBOUND_RDMA & aeq_info) == 0)) {
3309 if (aeq_info & NES_AEQE_SQ)
3310 nesqp->term_sq_flush_code = flush_code;
3311 else
3312 nesqp->term_rq_flush_code = flush_code;
3313 }
3314
3315 return sizeof(struct nes_terminate_hdr) + copy_len;
3316 }
3317
3318 static void nes_terminate_connection(struct nes_device *nesdev, struct nes_qp *nesqp,
3319 struct nes_hw_aeqe *aeqe, enum ib_event_type eventtype)
3320 {
3321 u64 context;
3322 unsigned long flags;
3323 u32 aeq_info;
3324 u16 async_event_id;
3325 u8 tcp_state;
3326 u8 iwarp_state;
3327 u32 termlen = 0;
3328 u32 mod_qp_flags = NES_CQP_QP_IWARP_STATE_TERMINATE |
3329 NES_CQP_QP_TERM_DONT_SEND_FIN;
3330 struct nes_adapter *nesadapter = nesdev->nesadapter;
3331
3332 if (nesqp->term_flags & NES_TERM_SENT)
3333 return; /* Sanity check */
3334
3335 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3336 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3337 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3338 async_event_id = (u16)aeq_info;
3339
3340 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
3341 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3342 if (!context) {
3343 WARN_ON(!context);
3344 return;
3345 }
3346
3347 nesqp = (struct nes_qp *)(unsigned long)context;
3348 spin_lock_irqsave(&nesqp->lock, flags);
3349 nesqp->hw_iwarp_state = iwarp_state;
3350 nesqp->hw_tcp_state = tcp_state;
3351 nesqp->last_aeq = async_event_id;
3352 nesqp->terminate_eventtype = eventtype;
3353 spin_unlock_irqrestore(&nesqp->lock, flags);
3354
3355 if (nesadapter->send_term_ok)
3356 termlen = nes_bld_terminate_hdr(nesqp, async_event_id, aeq_info);
3357 else
3358 mod_qp_flags |= NES_CQP_QP_TERM_DONT_SEND_TERM_MSG;
3359
3360 if (!nesdev->iw_status) {
3361 nesqp->term_flags = NES_TERM_DONE;
3362 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_ERROR, 0, 0);
3363 nes_cm_disconn(nesqp);
3364 } else {
3365 nes_terminate_start_timer(nesqp);
3366 nesqp->term_flags |= NES_TERM_SENT;
3367 nes_hw_modify_qp(nesdev, nesqp, mod_qp_flags, termlen, 0);
3368 }
3369 }
3370
3371 static void nes_terminate_send_fin(struct nes_device *nesdev,
3372 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3373 {
3374 u32 aeq_info;
3375 u16 async_event_id;
3376 u8 tcp_state;
3377 u8 iwarp_state;
3378 unsigned long flags;
3379
3380 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3381 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3382 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3383 async_event_id = (u16)aeq_info;
3384
3385 spin_lock_irqsave(&nesqp->lock, flags);
3386 nesqp->hw_iwarp_state = iwarp_state;
3387 nesqp->hw_tcp_state = tcp_state;
3388 nesqp->last_aeq = async_event_id;
3389 spin_unlock_irqrestore(&nesqp->lock, flags);
3390
3391 /* Send the fin only */
3392 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_TERMINATE |
3393 NES_CQP_QP_TERM_DONT_SEND_TERM_MSG, 0, 0);
3394 }
3395
3396 /* Cleanup after a terminate sent or received */
3397 static void nes_terminate_done(struct nes_qp *nesqp, int timeout_occurred)
3398 {
3399 u32 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR;
3400 unsigned long flags;
3401 struct nes_vnic *nesvnic = to_nesvnic(nesqp->ibqp.device);
3402 struct nes_device *nesdev = nesvnic->nesdev;
3403 u8 first_time = 0;
3404
3405 spin_lock_irqsave(&nesqp->lock, flags);
3406 if (nesqp->hte_added) {
3407 nesqp->hte_added = 0;
3408 next_iwarp_state |= NES_CQP_QP_DEL_HTE;
3409 }
3410
3411 first_time = (nesqp->term_flags & NES_TERM_DONE) == 0;
3412 nesqp->term_flags |= NES_TERM_DONE;
3413 spin_unlock_irqrestore(&nesqp->lock, flags);
3414
3415 /* Make sure we go through this only once */
3416 if (first_time) {
3417 if (timeout_occurred == 0)
3418 del_timer(&nesqp->terminate_timer);
3419 else
3420 next_iwarp_state |= NES_CQP_QP_RESET;
3421
3422 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3423 nes_cm_disconn(nesqp);
3424 }
3425 }
3426
3427 static void nes_terminate_received(struct nes_device *nesdev,
3428 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3429 {
3430 u32 aeq_info;
3431 u8 *pkt;
3432 u32 *mpa;
3433 u8 ddp_ctl;
3434 u8 rdma_ctl;
3435 u16 aeq_id = 0;
3436
3437 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3438 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3439 /* Terminate is not a performance path so the silicon */
3440 /* did not validate the frame - do it now */
3441 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3442 mpa = (u32 *)locate_mpa(pkt, aeq_info);
3443 ddp_ctl = (be32_to_cpu(mpa[0]) >> 8) & 0xff;
3444 rdma_ctl = be32_to_cpu(mpa[0]) & 0xff;
3445 if ((ddp_ctl & 0xc0) != 0x40)
3446 aeq_id = NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC;
3447 else if ((ddp_ctl & 0x03) != 1)
3448 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION;
3449 else if (be32_to_cpu(mpa[2]) != 2)
3450 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_QN;
3451 else if (be32_to_cpu(mpa[3]) != 1)
3452 aeq_id = NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN;
3453 else if (be32_to_cpu(mpa[4]) != 0)
3454 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_MO;
3455 else if ((rdma_ctl & 0xc0) != 0x40)
3456 aeq_id = NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION;
3457
3458 if (aeq_id) {
3459 /* Bad terminate recvd - send back a terminate */
3460 aeq_info = (aeq_info & 0xffff0000) | aeq_id;
3461 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3462 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3463 return;
3464 }
3465 }
3466
3467 nesqp->term_flags |= NES_TERM_RCVD;
3468 nesqp->terminate_eventtype = IB_EVENT_QP_FATAL;
3469 nes_terminate_start_timer(nesqp);
3470 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3471 }
3472
3473 /* Timeout routine in case terminate fails to complete */
3474 void nes_terminate_timeout(struct timer_list *t)
3475 {
3476 struct nes_qp *nesqp = from_timer(nesqp, t, terminate_timer);
3477
3478 nes_terminate_done(nesqp, 1);
3479 }
3480
3481 /* Set a timer in case hw cannot complete the terminate sequence */
3482 static void nes_terminate_start_timer(struct nes_qp *nesqp)
3483 {
3484 mod_timer(&nesqp->terminate_timer, (jiffies + HZ));
3485 }
3486
3487 /**
3488 * nes_process_iwarp_aeqe
3489 */
3490 static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
3491 struct nes_hw_aeqe *aeqe)
3492 {
3493 u64 context;
3494 unsigned long flags;
3495 struct nes_qp *nesqp;
3496 struct nes_hw_cq *hw_cq;
3497 struct nes_cq *nescq;
3498 int resource_allocated;
3499 struct nes_adapter *nesadapter = nesdev->nesadapter;
3500 u32 aeq_info;
3501 u32 next_iwarp_state = 0;
3502 u32 aeqe_cq_id;
3503 u16 async_event_id;
3504 u8 tcp_state;
3505 u8 iwarp_state;
3506 struct ib_event ibevent;
3507
3508 nes_debug(NES_DBG_AEQ, "\n");
3509 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3510 if ((NES_AEQE_INBOUND_RDMA & aeq_info) || (!(NES_AEQE_QP & aeq_info))) {
3511 context = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX]);
3512 context += ((u64)le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])) << 32;
3513 } else {
3514 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
3515 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3516 BUG_ON(!context);
3517 }
3518
3519 /* context is nesqp unless async_event_id == CQ ERROR */
3520 nesqp = (struct nes_qp *)(unsigned long)context;
3521 async_event_id = (u16)aeq_info;
3522 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3523 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3524 nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
3525 " Tcp state = %s, iWARP state = %s\n",
3526 async_event_id,
3527 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), aeqe,
3528 nes_tcp_state_str[tcp_state], nes_iwarp_state_str[iwarp_state]);
3529
3530 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
3531 if (aeq_info & NES_AEQE_QP) {
3532 if (!nes_is_resource_allocated(nesadapter,
3533 nesadapter->allocated_qps,
3534 aeqe_cq_id))
3535 return;
3536 }
3537
3538 switch (async_event_id) {
3539 case NES_AEQE_AEID_LLP_FIN_RECEIVED:
3540 if (nesqp->term_flags)
3541 return; /* Ignore it, wait for close complete */
3542
3543 if (atomic_inc_return(&nesqp->close_timer_started) == 1) {
3544 if ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) &&
3545 (nesqp->ibqp_state == IB_QPS_RTS)) {
3546 spin_lock_irqsave(&nesqp->lock, flags);
3547 nesqp->hw_iwarp_state = iwarp_state;
3548 nesqp->hw_tcp_state = tcp_state;
3549 nesqp->last_aeq = async_event_id;
3550 next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING;
3551 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING;
3552 spin_unlock_irqrestore(&nesqp->lock, flags);
3553 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3554 nes_cm_disconn(nesqp);
3555 }
3556 nesqp->cm_id->add_ref(nesqp->cm_id);
3557 schedule_nes_timer(nesqp->cm_node, (struct sk_buff *)nesqp,
3558 NES_TIMER_TYPE_CLOSE, 1, 0);
3559 nes_debug(NES_DBG_AEQ, "QP%u Not decrementing QP refcount (%d),"
3560 " need ae to finish up, original_last_aeq = 0x%04X."
3561 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
3562 nesqp->hwqp.qp_id, atomic_read(&nesqp->refcount),
3563 async_event_id, nesqp->last_aeq, tcp_state);
3564 }
3565 break;
3566 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE:
3567 spin_lock_irqsave(&nesqp->lock, flags);
3568 nesqp->hw_iwarp_state = iwarp_state;
3569 nesqp->hw_tcp_state = tcp_state;
3570 nesqp->last_aeq = async_event_id;
3571 spin_unlock_irqrestore(&nesqp->lock, flags);
3572 nes_cm_disconn(nesqp);
3573 break;
3574
3575 case NES_AEQE_AEID_RESET_SENT:
3576 tcp_state = NES_AEQE_TCP_STATE_CLOSED;
3577 spin_lock_irqsave(&nesqp->lock, flags);
3578 nesqp->hw_iwarp_state = iwarp_state;
3579 nesqp->hw_tcp_state = tcp_state;
3580 nesqp->last_aeq = async_event_id;
3581 nesqp->hte_added = 0;
3582 spin_unlock_irqrestore(&nesqp->lock, flags);
3583 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE;
3584 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3585 nes_cm_disconn(nesqp);
3586 break;
3587
3588 case NES_AEQE_AEID_LLP_CONNECTION_RESET:
3589 if (atomic_read(&nesqp->close_timer_started))
3590 return;
3591 spin_lock_irqsave(&nesqp->lock, flags);
3592 nesqp->hw_iwarp_state = iwarp_state;
3593 nesqp->hw_tcp_state = tcp_state;
3594 nesqp->last_aeq = async_event_id;
3595 spin_unlock_irqrestore(&nesqp->lock, flags);
3596 nes_cm_disconn(nesqp);
3597 break;
3598
3599 case NES_AEQE_AEID_TERMINATE_SENT:
3600 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3601 break;
3602
3603 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED:
3604 nes_terminate_received(nesdev, nesqp, aeqe);
3605 break;
3606
3607 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3608 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3609 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
3610 case NES_AEQE_AEID_AMP_INVALID_STAG:
3611 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3612 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3613 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
3614 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3615 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3616 case NES_AEQE_AEID_AMP_TO_WRAP:
3617 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_ACCESS_ERR\n",
3618 nesqp->hwqp.qp_id, async_event_id);
3619 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_ACCESS_ERR);
3620 break;
3621
3622 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3623 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3624 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3625 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
3626 if (iwarp_opcode(nesqp, aeq_info) > IWARP_OPCODE_TERM) {
3627 aeq_info &= 0xffff0000;
3628 aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE;
3629 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3630 }
3631 /* fall through */
3632 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE:
3633 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES:
3634 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3635 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3636 case NES_AEQE_AEID_AMP_BAD_QP:
3637 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3638 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3639 case NES_AEQE_AEID_DDP_NO_L_BIT:
3640 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3641 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3642 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3643 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3644 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3645 case NES_AEQE_AEID_AMP_BAD_PD:
3646 case NES_AEQE_AEID_AMP_FASTREG_SHARED:
3647 case NES_AEQE_AEID_AMP_FASTREG_VALID_STAG:
3648 case NES_AEQE_AEID_AMP_FASTREG_MW_STAG:
3649 case NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS:
3650 case NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW:
3651 case NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH:
3652 case NES_AEQE_AEID_AMP_INVALIDATE_SHARED:
3653 case NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS:
3654 case NES_AEQE_AEID_AMP_MWBIND_VALID_STAG:
3655 case NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG:
3656 case NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG:
3657 case NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG:
3658 case NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS:
3659 case NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS:
3660 case NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT:
3661 case NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED:
3662 case NES_AEQE_AEID_BAD_CLOSE:
3663 case NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO:
3664 case NES_AEQE_AEID_STAG_ZERO_INVALID:
3665 case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST:
3666 case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
3667 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_FATAL\n",
3668 nesqp->hwqp.qp_id, async_event_id);
3669 print_ip(nesqp->cm_node);
3670 if (!atomic_read(&nesqp->close_timer_started))
3671 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3672 break;
3673
3674 case NES_AEQE_AEID_CQ_OPERATION_ERROR:
3675 context <<= 1;
3676 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
3677 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), (void *)(unsigned long)context);
3678 resource_allocated = nes_is_resource_allocated(nesadapter, nesadapter->allocated_cqs,
3679 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3680 if (resource_allocated) {
3681 printk(KERN_ERR PFX "%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
3682 __func__, le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3683 hw_cq = (struct nes_hw_cq *)(unsigned long)context;
3684 if (hw_cq) {
3685 nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3686 if (nescq->ibcq.event_handler) {
3687 ibevent.device = nescq->ibcq.device;
3688 ibevent.event = IB_EVENT_CQ_ERR;
3689 ibevent.element.cq = &nescq->ibcq;
3690 nescq->ibcq.event_handler(&ibevent, nescq->ibcq.cq_context);
3691 }
3692 }
3693 }
3694 break;
3695
3696 default:
3697 nes_debug(NES_DBG_AEQ, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
3698 async_event_id);
3699 break;
3700 }
3701
3702 }
3703
3704 /**
3705 * nes_iwarp_ce_handler
3706 */
3707 void nes_iwarp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *hw_cq)
3708 {
3709 struct nes_cq *nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3710
3711 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
3712 nescq->hw_cq.cq_number); */
3713 nes_write32(nesdev->regs+NES_CQ_ACK, nescq->hw_cq.cq_number);
3714
3715 if (nescq->ibcq.comp_handler)
3716 nescq->ibcq.comp_handler(&nescq->ibcq, nescq->ibcq.cq_context);
3717
3718 return;
3719 }
3720
3721
3722 /**
3723 * nes_manage_apbvt()
3724 */
3725 int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
3726 u32 nic_index, u32 add_port)
3727 {
3728 struct nes_device *nesdev = nesvnic->nesdev;
3729 struct nes_hw_cqp_wqe *cqp_wqe;
3730 struct nes_cqp_request *cqp_request;
3731 int ret = 0;
3732 u16 major_code;
3733
3734 /* Send manage APBVT request to CQP */
3735 cqp_request = nes_get_cqp_request(nesdev);
3736 if (cqp_request == NULL) {
3737 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3738 return -ENOMEM;
3739 }
3740 cqp_request->waiting = 1;
3741 cqp_wqe = &cqp_request->cqp_wqe;
3742
3743 nes_debug(NES_DBG_QP, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
3744 (add_port == NES_MANAGE_APBVT_ADD) ? "ADD" : "DEL",
3745 accel_local_port, accel_local_port, nic_index);
3746
3747 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3748 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, (NES_CQP_MANAGE_APBVT |
3749 ((add_port == NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0)));
3750 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
3751 ((nic_index << NES_CQP_APBVT_NIC_SHIFT) | accel_local_port));
3752
3753 nes_debug(NES_DBG_QP, "Waiting for CQP completion for APBVT.\n");
3754
3755 atomic_set(&cqp_request->refcount, 2);
3756 nes_post_cqp_request(nesdev, cqp_request);
3757
3758 if (add_port == NES_MANAGE_APBVT_ADD)
3759 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3760 NES_EVENT_TIMEOUT);
3761 nes_debug(NES_DBG_QP, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
3762 ret, cqp_request->major_code, cqp_request->minor_code);
3763 major_code = cqp_request->major_code;
3764
3765 nes_put_cqp_request(nesdev, cqp_request);
3766
3767 if (!ret)
3768 return -ETIME;
3769 else if (major_code)
3770 return -EIO;
3771 else
3772 return 0;
3773 }
3774
3775
3776 /**
3777 * nes_manage_arp_cache
3778 */
3779 void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
3780 u32 ip_addr, u32 action)
3781 {
3782 struct nes_hw_cqp_wqe *cqp_wqe;
3783 struct nes_vnic *nesvnic = netdev_priv(netdev);
3784 struct nes_device *nesdev;
3785 struct nes_cqp_request *cqp_request;
3786 int arp_index;
3787
3788 nesdev = nesvnic->nesdev;
3789 arp_index = nes_arp_table(nesdev, ip_addr, mac_addr, action);
3790 if (arp_index == -1) {
3791 return;
3792 }
3793
3794 /* update the ARP entry */
3795 cqp_request = nes_get_cqp_request(nesdev);
3796 if (cqp_request == NULL) {
3797 nes_debug(NES_DBG_NETDEV, "Failed to get a cqp_request.\n");
3798 return;
3799 }
3800 cqp_request->waiting = 0;
3801 cqp_wqe = &cqp_request->cqp_wqe;
3802 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3803
3804 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
3805 NES_CQP_MANAGE_ARP_CACHE | NES_CQP_ARP_PERM);
3806 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(
3807 (u32)PCI_FUNC(nesdev->pcidev->devfn) << NES_CQP_ARP_AEQ_INDEX_SHIFT);
3808 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(arp_index);
3809
3810 if (action == NES_ARP_ADD) {
3811 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(NES_CQP_ARP_VALID);
3812 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = cpu_to_le32(
3813 (((u32)mac_addr[2]) << 24) | (((u32)mac_addr[3]) << 16) |
3814 (((u32)mac_addr[4]) << 8) | (u32)mac_addr[5]);
3815 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = cpu_to_le32(
3816 (((u32)mac_addr[0]) << 8) | (u32)mac_addr[1]);
3817 } else {
3818 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = 0;
3819 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = 0;
3820 }
3821
3822 nes_debug(NES_DBG_NETDEV, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3823 nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
3824
3825 atomic_set(&cqp_request->refcount, 1);
3826 nes_post_cqp_request(nesdev, cqp_request);
3827 }
3828
3829
3830 /**
3831 * flush_wqes
3832 */
3833 void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3834 u32 which_wq, u32 wait_completion)
3835 {
3836 struct nes_cqp_request *cqp_request;
3837 struct nes_hw_cqp_wqe *cqp_wqe;
3838 u32 sq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3839 u32 rq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3840 int ret;
3841
3842 cqp_request = nes_get_cqp_request(nesdev);
3843 if (cqp_request == NULL) {
3844 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3845 return;
3846 }
3847 if (wait_completion) {
3848 cqp_request->waiting = 1;
3849 atomic_set(&cqp_request->refcount, 2);
3850 } else {
3851 cqp_request->waiting = 0;
3852 }
3853 cqp_wqe = &cqp_request->cqp_wqe;
3854 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3855
3856 /* If wqe in error was identified, set code to be put into cqe */
3857 if ((nesqp->term_sq_flush_code) && (which_wq & NES_CQP_FLUSH_SQ)) {
3858 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3859 sq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_sq_flush_code;
3860 nesqp->term_sq_flush_code = 0;
3861 }
3862
3863 if ((nesqp->term_rq_flush_code) && (which_wq & NES_CQP_FLUSH_RQ)) {
3864 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3865 rq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_rq_flush_code;
3866 nesqp->term_rq_flush_code = 0;
3867 }
3868
3869 if (which_wq & NES_CQP_FLUSH_MAJ_MIN) {
3870 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_SQ_CODE] = cpu_to_le32(sq_code);
3871 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_RQ_CODE] = cpu_to_le32(rq_code);
3872 }
3873
3874 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
3875 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq);
3876 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id);
3877
3878 nes_post_cqp_request(nesdev, cqp_request);
3879
3880 if (wait_completion) {
3881 /* Wait for CQP */
3882 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3883 NES_EVENT_TIMEOUT);
3884 nes_debug(NES_DBG_QP, "Flush SQ QP WQEs completed, ret=%u,"
3885 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3886 ret, cqp_request->major_code, cqp_request->minor_code);
3887 nes_put_cqp_request(nesdev, cqp_request);
3888 }
3889 }
CRIS linux kernel tree