drivers/infiniband/hw/qib/qib_pcie.c

   1 /*
   2  * Copyright (c) 2010 - 2017 Intel Corporation.  All rights reserved.
   3  * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/aer.h>
  39 #include <linux/module.h>
  40
  41 #include "qib.h"
  42
  43 /*
  44  * This file contains PCIe utility routines that are common to the
  45  * various QLogic InfiniPath adapters
  46  */
  47
  48 /*
  49  * Code to adjust PCIe capabilities.
  50  * To minimize the change footprint, we call it
  51  * from qib_pcie_params, which every chip-specific
  52  * file calls, even though this violates some
  53  * expectations of harmlessness.
  54  */
  55 static void qib_tune_pcie_caps(struct qib_devdata *);
  56 static void qib_tune_pcie_coalesce(struct qib_devdata *);
  57
  58 /*
  59  * Do all the common PCIe setup and initialization.
  60  * devdata is not yet allocated, and is not allocated until after this
  61  * routine returns success.  Therefore qib_dev_err() can't be used for error
  62  * printing.
  63  */
  64 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
  65 {
  66         int ret;
  67
  68         ret = pci_enable_device(pdev);
  69         if (ret) {
  70                 /*
  71                  * This can happen (in theory) iff:
  72                  * We did a chip reset, and then failed to reprogram the
  73                  * BAR, or the chip reset due to an internal error.  We then
  74                  * unloaded the driver and reloaded it.
  75                  *
  76                  * Both reset cases set the BAR back to initial state.  For
  77                  * the latter case, the AER sticky error bit at offset 0x718
  78                  * should be set, but the Linux kernel doesn't yet know
  79                  * about that, it appears.  If the original BAR was retained
  80                  * in the kernel data structures, this may be OK.
  81                  */
  82                 qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
  83                               -ret);
  84                 goto done;
  85         }
  86
  87         ret = pci_request_regions(pdev, QIB_DRV_NAME);
  88         if (ret) {
  89                 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
  90                 goto bail;
  91         }
  92
  93         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  94         if (ret) {
  95                 /*
  96                  * If the 64 bit setup fails, try 32 bit.  Some systems
  97                  * do not setup 64 bit maps on systems with 2GB or less
  98                  * memory installed.
  99                  */
 100                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 101                 if (ret) {
 102                         qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
 103                         goto bail;
 104                 }
 105                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 106         } else
 107                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 108         if (ret) {
 109                 qib_early_err(&pdev->dev,
 110                               "Unable to set DMA consistent mask: %d\n", ret);
 111                 goto bail;
 112         }
 113
 114         pci_set_master(pdev);
 115         ret = pci_enable_pcie_error_reporting(pdev);
 116         if (ret) {
 117                 qib_early_err(&pdev->dev,
 118                               "Unable to enable pcie error reporting: %d\n",
 119                               ret);
 120                 ret = 0;
 121         }
 122         goto done;
 123
 124 bail:
 125         pci_disable_device(pdev);
 126         pci_release_regions(pdev);
 127 done:
 128         return ret;
 129 }
 130
 131 /*
 132  * Do remaining PCIe setup, once dd is allocated, and save away
 133  * fields required to re-initialize after a chip reset, or for
 134  * various other purposes
 135  */
 136 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
 137                     const struct pci_device_id *ent)
 138 {
 139         unsigned long len;
 140         resource_size_t addr;
 141
 142         dd->pcidev = pdev;
 143         pci_set_drvdata(pdev, dd);
 144
 145         addr = pci_resource_start(pdev, 0);
 146         len = pci_resource_len(pdev, 0);
 147
 148         dd->kregbase = ioremap_nocache(addr, len);
 149         if (!dd->kregbase)
 150                 return -ENOMEM;
 151
 152         dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
 153         dd->physaddr = addr;        /* used for io_remap, etc. */
 154
 155         /*
 156          * Save BARs to rewrite after device reset.  Save all 64 bits of
 157          * BAR, just in case.
 158          */
 159         dd->pcibar0 = addr;
 160         dd->pcibar1 = addr >> 32;
 161         dd->deviceid = ent->device; /* save for later use */
 162         dd->vendorid = ent->vendor;
 163
 164         return 0;
 165 }
 166
 167 /*
 168  * Do PCIe cleanup, after chip-specific cleanup, etc.  Just prior
 169  * to releasing the dd memory.
 170  * void because none of the core pcie cleanup returns are void
 171  */
 172 void qib_pcie_ddcleanup(struct qib_devdata *dd)
 173 {
 174         u64 __iomem *base = (void __iomem *) dd->kregbase;
 175
 176         dd->kregbase = NULL;
 177         iounmap(base);
 178         if (dd->piobase)
 179                 iounmap(dd->piobase);
 180         if (dd->userbase)
 181                 iounmap(dd->userbase);
 182         if (dd->piovl15base)
 183                 iounmap(dd->piovl15base);
 184
 185         pci_disable_device(dd->pcidev);
 186         pci_release_regions(dd->pcidev);
 187
 188         pci_set_drvdata(dd->pcidev, NULL);
 189 }
 190
 191 /**
 192  * We save the msi lo and hi values, so we can restore them after
 193  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 194  * correctly.
 195  */
 196 static void qib_cache_msi_info(struct qib_devdata *dd, int pos)
 197 {
 198         struct pci_dev *pdev = dd->pcidev;
 199         u16 control;
 200
 201         pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo);
 202         pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi);
 203         pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
 204
 205         /* now save the data (vector) info */
 206         pci_read_config_word(pdev,
 207                              pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 208                              &dd->msi_data);
 209 }
 210
 211 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
 212 {
 213         u16 linkstat, speed;
 214         int nvec;
 215         int maxvec;
 216         unsigned int flags = PCI_IRQ_MSIX | PCI_IRQ_MSI;
 217
 218         if (!pci_is_pcie(dd->pcidev)) {
 219                 qib_dev_err(dd, "Can't find PCI Express capability!\n");
 220                 /* set up something... */
 221                 dd->lbus_width = 1;
 222                 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
 223                 nvec = -1;
 224                 goto bail;
 225         }
 226
 227         if (dd->flags & QIB_HAS_INTX)
 228                 flags |= PCI_IRQ_LEGACY;
 229         maxvec = (nent && *nent) ? *nent : 1;
 230         nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
 231         if (nvec < 0)
 232                 goto bail;
 233
 234         /*
 235          * If nent exists, make sure to record how many vectors were allocated.
 236          * If msix_enabled is false, return 0 so the fallback code works
 237          * correctly.
 238          */
 239         if (nent)
 240                 *nent = !dd->pcidev->msix_enabled ? 0 : nvec;
 241
 242         if (dd->pcidev->msi_enabled)
 243                 qib_cache_msi_info(dd, dd->pcidev->msi_cap);
 244
 245         pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
 246         /*
 247          * speed is bits 0-3, linkwidth is bits 4-8
 248          * no defines for them in headers
 249          */
 250         speed = linkstat & 0xf;
 251         linkstat >>= 4;
 252         linkstat &= 0x1f;
 253         dd->lbus_width = linkstat;
 254
 255         switch (speed) {
 256         case 1:
 257                 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
 258                 break;
 259         case 2:
 260                 dd->lbus_speed = 5000; /* Gen1, 5GHz */
 261                 break;
 262         default: /* not defined, assume gen1 */
 263                 dd->lbus_speed = 2500;
 264                 break;
 265         }
 266
 267         /*
 268          * Check against expected pcie width and complain if "wrong"
 269          * on first initialization, not afterwards (i.e., reset).
 270          */
 271         if (minw && linkstat < minw)
 272                 qib_dev_err(dd,
 273                             "PCIe width %u (x%u HCA), performance reduced\n",
 274                             linkstat, minw);
 275
 276         qib_tune_pcie_caps(dd);
 277
 278         qib_tune_pcie_coalesce(dd);
 279
 280 bail:
 281         /* fill in string, even on errors */
 282         snprintf(dd->lbus_info, sizeof(dd->lbus_info),
 283                  "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
 284         return nvec < 0 ? nvec : 0;
 285 }
 286
 287 /**
 288  * qib_free_irq - Cleanup INTx and MSI interrupts
 289  * @dd: valid pointer to qib dev data
 290  *
 291  * Since cleanup for INTx and MSI interrupts is trivial, have a common
 292  * routine.
 293  *
 294  */
 295 void qib_free_irq(struct qib_devdata *dd)
 296 {
 297         pci_free_irq(dd->pcidev, 0, dd);
 298         pci_free_irq_vectors(dd->pcidev);
 299 }
 300
 301 /*
 302  * Setup pcie interrupt stuff again after a reset.  I'd like to just call
 303  * pci_enable_msi() again for msi, but when I do that,
 304  * the MSI enable bit doesn't get set in the command word, and
 305  * we switch to to a different interrupt vector, which is confusing,
 306  * so I instead just do it all inline.  Perhaps somehow can tie this
 307  * into the PCIe hotplug support at some point
 308  */
 309 int qib_reinit_intr(struct qib_devdata *dd)
 310 {
 311         int pos;
 312         u16 control;
 313         int ret = 0;
 314
 315         /* If we aren't using MSI, don't restore it */
 316         if (!dd->msi_lo)
 317                 goto bail;
 318
 319         pos = dd->pcidev->msi_cap;
 320         if (!pos) {
 321                 qib_dev_err(dd,
 322                         "Can't find MSI capability, can't restore MSI settings\n");
 323                 ret = 0;
 324                 /* nothing special for MSIx, just MSI */
 325                 goto bail;
 326         }
 327         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 328                                dd->msi_lo);
 329         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 330                                dd->msi_hi);
 331         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
 332         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
 333                 control |= PCI_MSI_FLAGS_ENABLE;
 334                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 335                                       control);
 336         }
 337         /* now rewrite the data (vector) info */
 338         pci_write_config_word(dd->pcidev, pos +
 339                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 340                               dd->msi_data);
 341         ret = 1;
 342 bail:
 343         qib_free_irq(dd);
 344
 345         if (!ret && (dd->flags & QIB_HAS_INTX))
 346                 ret = 1;
 347
 348         /* and now set the pci master bit again */
 349         pci_set_master(dd->pcidev);
 350
 351         return ret;
 352 }
 353
 354 /*
 355  * These two routines are helper routines for the device reset code
 356  * to move all the pcie code out of the chip-specific driver code.
 357  */
 358 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
 359 {
 360         pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
 361         pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
 362         pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
 363 }
 364
 365 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
 366 {
 367         int r;
 368
 369         r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
 370                                    dd->pcibar0);
 371         if (r)
 372                 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
 373         r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
 374                                    dd->pcibar1);
 375         if (r)
 376                 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
 377         /* now re-enable memory access, and restore cosmetic settings */
 378         pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
 379         pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
 380         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
 381         r = pci_enable_device(dd->pcidev);
 382         if (r)
 383                 qib_dev_err(dd,
 384                         "pci_enable_device failed after reset: %d\n", r);
 385 }
 386
 387
 388 static int qib_pcie_coalesce;
 389 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
 390 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
 391
 392 /*
 393  * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
 394  * chipsets.   This is known to be unsafe for some revisions of some
 395  * of these chipsets, with some BIOS settings, and enabling it on those
 396  * systems may result in the system crashing, and/or data corruption.
 397  */
 398 static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
 399 {
 400         struct pci_dev *parent;
 401         u16 devid;
 402         u32 mask, bits, val;
 403
 404         if (!qib_pcie_coalesce)
 405                 return;
 406
 407         /* Find out supported and configured values for parent (root) */
 408         parent = dd->pcidev->bus->self;
 409         if (parent->bus->parent) {
 410                 qib_devinfo(dd->pcidev, "Parent not root\n");
 411                 return;
 412         }
 413         if (!pci_is_pcie(parent))
 414                 return;
 415         if (parent->vendor != 0x8086)
 416                 return;
 417
 418         /*
 419          *  - bit 12: Max_rdcmp_Imt_EN: need to set to 1
 420          *  - bit 11: COALESCE_FORCE: need to set to 0
 421          *  - bit 10: COALESCE_EN: need to set to 1
 422          *  (but limitations on some on some chipsets)
 423          *
 424          *  On the Intel 5000, 5100, and 7300 chipsets, there is
 425          *  also: - bit 25:24: COALESCE_MODE, need to set to 0
 426          */
 427         devid = parent->device;
 428         if (devid >= 0x25e2 && devid <= 0x25fa) {
 429                 /* 5000 P/V/X/Z */
 430                 if (parent->revision <= 0xb2)
 431                         bits = 1U << 10;
 432                 else
 433                         bits = 7U << 10;
 434                 mask = (3U << 24) | (7U << 10);
 435         } else if (devid >= 0x65e2 && devid <= 0x65fa) {
 436                 /* 5100 */
 437                 bits = 1U << 10;
 438                 mask = (3U << 24) | (7U << 10);
 439         } else if (devid >= 0x4021 && devid <= 0x402e) {
 440                 /* 5400 */
 441                 bits = 7U << 10;
 442                 mask = 7U << 10;
 443         } else if (devid >= 0x3604 && devid <= 0x360a) {
 444                 /* 7300 */
 445                 bits = 7U << 10;
 446                 mask = (3U << 24) | (7U << 10);
 447         } else {
 448                 /* not one of the chipsets that we know about */
 449                 return;
 450         }
 451         pci_read_config_dword(parent, 0x48, &val);
 452         val &= ~mask;
 453         val |= bits;
 454         pci_write_config_dword(parent, 0x48, val);
 455 }
 456
 457 /*
 458  * BIOS may not set PCIe bus-utilization parameters for best performance.
 459  * Check and optionally adjust them to maximize our throughput.
 460  */
 461 static int qib_pcie_caps;
 462 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
 463 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
 464
 465 static void qib_tune_pcie_caps(struct qib_devdata *dd)
 466 {
 467         struct pci_dev *parent;
 468         u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
 469         u16 rc_mrrs, ep_mrrs, max_mrrs;
 470
 471         /* Find out supported and configured values for parent (root) */
 472         parent = dd->pcidev->bus->self;
 473         if (!pci_is_root_bus(parent->bus)) {
 474                 qib_devinfo(dd->pcidev, "Parent not root\n");
 475                 return;
 476         }
 477
 478         if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
 479                 return;
 480
 481         rc_mpss = parent->pcie_mpss;
 482         rc_mps = ffs(pcie_get_mps(parent)) - 8;
 483         /* Find out supported and configured values for endpoint (us) */
 484         ep_mpss = dd->pcidev->pcie_mpss;
 485         ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
 486
 487         /* Find max payload supported by root, endpoint */
 488         if (rc_mpss > ep_mpss)
 489                 rc_mpss = ep_mpss;
 490
 491         /* If Supported greater than limit in module param, limit it */
 492         if (rc_mpss > (qib_pcie_caps & 7))
 493                 rc_mpss = qib_pcie_caps & 7;
 494         /* If less than (allowed, supported), bump root payload */
 495         if (rc_mpss > rc_mps) {
 496                 rc_mps = rc_mpss;
 497                 pcie_set_mps(parent, 128 << rc_mps);
 498         }
 499         /* If less than (allowed, supported), bump endpoint payload */
 500         if (rc_mpss > ep_mps) {
 501                 ep_mps = rc_mpss;
 502                 pcie_set_mps(dd->pcidev, 128 << ep_mps);
 503         }
 504
 505         /*
 506          * Now the Read Request size.
 507          * No field for max supported, but PCIe spec limits it to 4096,
 508          * which is code '5' (log2(4096) - 7)
 509          */
 510         max_mrrs = 5;
 511         if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
 512                 max_mrrs = (qib_pcie_caps >> 4) & 7;
 513
 514         max_mrrs = 128 << max_mrrs;
 515         rc_mrrs = pcie_get_readrq(parent);
 516         ep_mrrs = pcie_get_readrq(dd->pcidev);
 517
 518         if (max_mrrs > rc_mrrs) {
 519                 rc_mrrs = max_mrrs;
 520                 pcie_set_readrq(parent, rc_mrrs);
 521         }
 522         if (max_mrrs > ep_mrrs) {
 523                 ep_mrrs = max_mrrs;
 524                 pcie_set_readrq(dd->pcidev, ep_mrrs);
 525         }
 526 }
 527 /* End of PCIe capability tuning */
 528
 529 /*
 530  * From here through qib_pci_err_handler definition is invoked via
 531  * PCI error infrastructure, registered via pci
 532  */
 533 static pci_ers_result_t
 534 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
 535 {
 536         struct qib_devdata *dd = pci_get_drvdata(pdev);
 537         pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
 538
 539         switch (state) {
 540         case pci_channel_io_normal:
 541                 qib_devinfo(pdev, "State Normal, ignoring\n");
 542                 break;
 543
 544         case pci_channel_io_frozen:
 545                 qib_devinfo(pdev, "State Frozen, requesting reset\n");
 546                 pci_disable_device(pdev);
 547                 ret = PCI_ERS_RESULT_NEED_RESET;
 548                 break;
 549
 550         case pci_channel_io_perm_failure:
 551                 qib_devinfo(pdev, "State Permanent Failure, disabling\n");
 552                 if (dd) {
 553                         /* no more register accesses! */
 554                         dd->flags &= ~QIB_PRESENT;
 555                         qib_disable_after_error(dd);
 556                 }
 557                  /* else early, or other problem */
 558                 ret =  PCI_ERS_RESULT_DISCONNECT;
 559                 break;
 560
 561         default: /* shouldn't happen */
 562                 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
 563                         state);
 564                 break;
 565         }
 566         return ret;
 567 }
 568
 569 static pci_ers_result_t
 570 qib_pci_mmio_enabled(struct pci_dev *pdev)
 571 {
 572         u64 words = 0U;
 573         struct qib_devdata *dd = pci_get_drvdata(pdev);
 574         pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
 575
 576         if (dd && dd->pport) {
 577                 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
 578                 if (words == ~0ULL)
 579                         ret = PCI_ERS_RESULT_NEED_RESET;
 580         }
 581         qib_devinfo(pdev,
 582                 "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
 583                 words, ret);
 584         return  ret;
 585 }
 586
 587 static pci_ers_result_t
 588 qib_pci_slot_reset(struct pci_dev *pdev)
 589 {
 590         qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
 591         return PCI_ERS_RESULT_CAN_RECOVER;
 592 }
 593
 594 static void
 595 qib_pci_resume(struct pci_dev *pdev)
 596 {
 597         struct qib_devdata *dd = pci_get_drvdata(pdev);
 598
 599         qib_devinfo(pdev, "QIB resume function called\n");
 600         pci_cleanup_aer_uncorrect_error_status(pdev);
 601         /*
 602          * Running jobs will fail, since it's asynchronous
 603          * unlike sysfs-requested reset.   Better than
 604          * doing nothing.
 605          */
 606         qib_init(dd, 1); /* same as re-init after reset */
 607 }
 608
 609 const struct pci_error_handlers qib_pci_err_handler = {
 610         .error_detected = qib_pci_error_detected,
 611         .mmio_enabled = qib_pci_mmio_enabled,
 612         .slot_reset = qib_pci_slot_reset,
 613         .resume = qib_pci_resume,
 614 };