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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / isdn / hisax / diva.c
blobd23df7a7784df324d63567bd481e109d396d95ce
1 /* $Id: diva.c,v 1.33.2.6 2004/02/11 13:21:33 keil Exp $
2 *
3 * low level stuff for Eicon.Diehl Diva Family ISDN cards
4 *
5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * For changes and modifications please read
12 * Documentation/isdn/HiSax.cert
13 *
14 * Thanks to Eicon Technology for documents and information
15 *
16 */
17
18 #include <linux/init.h>
19 #include "hisax.h"
20 #include "isac.h"
21 #include "hscx.h"
22 #include "ipac.h"
23 #include "ipacx.h"
24 #include "isdnl1.h"
25 #include <linux/pci.h>
26 #include <linux/isapnp.h>
27
28 static const char *Diva_revision = "$Revision: 1.33.2.6 $";
29
30 #define byteout(addr, val) outb(val, addr)
31 #define bytein(addr) inb(addr)
32
33 #define DIVA_HSCX_DATA 0
34 #define DIVA_HSCX_ADR 4
35 #define DIVA_ISA_ISAC_DATA 2
36 #define DIVA_ISA_ISAC_ADR 6
37 #define DIVA_ISA_CTRL 7
38 #define DIVA_IPAC_ADR 0
39 #define DIVA_IPAC_DATA 1
40
41 #define DIVA_PCI_ISAC_DATA 8
42 #define DIVA_PCI_ISAC_ADR 0xc
43 #define DIVA_PCI_CTRL 0x10
44
45 /* SUB Types */
46 #define DIVA_ISA 1
47 #define DIVA_PCI 2
48 #define DIVA_IPAC_ISA 3
49 #define DIVA_IPAC_PCI 4
50 #define DIVA_IPACX_PCI 5
51
52 /* CTRL (Read) */
53 #define DIVA_IRQ_STAT 0x01
54 #define DIVA_EEPROM_SDA 0x02
55
56 /* CTRL (Write) */
57 #define DIVA_IRQ_REQ 0x01
58 #define DIVA_RESET 0x08
59 #define DIVA_EEPROM_CLK 0x40
60 #define DIVA_PCI_LED_A 0x10
61 #define DIVA_PCI_LED_B 0x20
62 #define DIVA_ISA_LED_A 0x20
63 #define DIVA_ISA_LED_B 0x40
64 #define DIVA_IRQ_CLR 0x80
65
66 /* Siemens PITA */
67 #define PITA_MISC_REG 0x1c
68 #ifdef __BIG_ENDIAN
69 #define PITA_PARA_SOFTRESET 0x00000001
70 #define PITA_SER_SOFTRESET 0x00000002
71 #define PITA_PARA_MPX_MODE 0x00000004
72 #define PITA_INT0_ENABLE 0x00000200
73 #else
74 #define PITA_PARA_SOFTRESET 0x01000000
75 #define PITA_SER_SOFTRESET 0x02000000
76 #define PITA_PARA_MPX_MODE 0x04000000
77 #define PITA_INT0_ENABLE 0x00020000
78 #endif
79 #define PITA_INT0_STATUS 0x02
80
81 static inline u_char
82 readreg(unsigned int ale, unsigned int adr, u_char off)
83 {
84 register u_char ret;
85
86 byteout(ale, off);
87 ret = bytein(adr);
88 return (ret);
89 }
90
91 static inline void
92 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
93 {
94 byteout(ale, off);
95 insb(adr, data, size);
96 }
97
98
99 static inline void
100 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
101 {
102 byteout(ale, off);
103 byteout(adr, data);
104 }
105
106 static inline void
107 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
108 {
109 byteout(ale, off);
110 outsb(adr, data, size);
111 }
112
113 static inline u_char
114 memreadreg(unsigned long adr, u_char off)
115 {
116 return (*((unsigned char *)
117 (((unsigned int *)adr) + off)));
118 }
119
120 static inline void
121 memwritereg(unsigned long adr, u_char off, u_char data)
122 {
123 register u_char *p;
124
125 p = (unsigned char *)(((unsigned int *)adr) + off);
126 *p = data;
127 }
128
129 /* Interface functions */
130
131 static u_char
132 ReadISAC(struct IsdnCardState *cs, u_char offset)
133 {
134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset));
135 }
136
137 static void
138 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
139 {
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
141 }
142
143 static void
144 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
145 {
146 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
147 }
148
149 static void
150 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
151 {
152 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size);
153 }
154
155 static u_char
156 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
157 {
158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80));
159 }
160
161 static void
162 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
163 {
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value);
165 }
166
167 static void
168 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
169 {
170 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
171 }
172
173 static void
174 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
175 {
176 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size);
177 }
178
179 static u_char
180 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
181 {
182 return (readreg(cs->hw.diva.hscx_adr,
183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
184 }
185
186 static void
187 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
188 {
189 writereg(cs->hw.diva.hscx_adr,
190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
191 }
192
193 static u_char
194 MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset)
195 {
196 return (memreadreg(cs->hw.diva.cfg_reg, offset + 0x80));
197 }
198
199 static void
200 MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value)
201 {
202 memwritereg(cs->hw.diva.cfg_reg, offset | 0x80, value);
203 }
204
205 static void
206 MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
207 {
208 while (size--)
209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80);
210 }
211
212 static void
213 MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size)
214 {
215 while (size--)
216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++);
217 }
218
219 static u_char
220 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
221 {
222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
223 }
224
225 static void
226 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
227 {
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
229 }
230
231 /* IO-Functions for IPACX type cards */
232 static u_char
233 MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset)
234 {
235 return (memreadreg(cs->hw.diva.cfg_reg, offset));
236 }
237
238 static void
239 MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value)
240 {
241 memwritereg(cs->hw.diva.cfg_reg, offset, value);
242 }
243
244 static void
245 MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size)
246 {
247 while (size--)
248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0);
249 }
250
251 static void
252 MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size)
253 {
254 while (size--)
255 memwritereg(cs->hw.diva.cfg_reg, 0, *data++);
256 }
257
258 static u_char
259 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset)
260 {
261 return (memreadreg(cs->hw.diva.cfg_reg, offset +
262 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
263 }
264
265 static void
266 MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
267 {
268 memwritereg(cs->hw.diva.cfg_reg, offset +
269 (hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
270 }
271
272 /*
273 * fast interrupt HSCX stuff goes here
274 */
275
276 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
277 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
280
281 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
282 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
283
284 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
285 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
286
287 #include "hscx_irq.c"
288
289 static irqreturn_t
290 diva_interrupt(int intno, void *dev_id)
291 {
292 struct IsdnCardState *cs = dev_id;
293 u_char val, sval;
294 u_long flags;
295 int cnt = 5;
296
297 spin_lock_irqsave(&cs->lock, flags);
298 while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) {
299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40);
300 if (val)
301 hscx_int_main(cs, val);
302 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA);
303 if (val)
304 isac_interrupt(cs, val);
305 cnt--;
306 }
307 if (!cnt)
308 printk(KERN_WARNING "Diva: IRQ LOOP\n");
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0);
314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0);
315 spin_unlock_irqrestore(&cs->lock, flags);
316 return IRQ_HANDLED;
317 }
318
319 static irqreturn_t
320 diva_irq_ipac_isa(int intno, void *dev_id)
321 {
322 struct IsdnCardState *cs = dev_id;
323 u_char ista, val;
324 u_long flags;
325 int icnt = 5;
326
327 spin_lock_irqsave(&cs->lock, flags);
328 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
329 Start_IPACISA:
330 if (cs->debug & L1_DEB_IPAC)
331 debugl1(cs, "IPAC ISTA %02X", ista);
332 if (ista & 0x0f) {
333 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40);
334 if (ista & 0x01)
335 val |= 0x01;
336 if (ista & 0x04)
337 val |= 0x02;
338 if (ista & 0x08)
339 val |= 0x04;
340 if (val)
341 hscx_int_main(cs, val);
342 }
343 if (ista & 0x20) {
344 val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80);
345 if (val) {
346 isac_interrupt(cs, val);
347 }
348 }
349 if (ista & 0x10) {
350 val = 0x01;
351 isac_interrupt(cs, val);
352 }
353 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA);
354 if ((ista & 0x3f) && icnt) {
355 icnt--;
356 goto Start_IPACISA;
357 }
358 if (!icnt)
359 printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n");
360 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF);
361 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0);
362 spin_unlock_irqrestore(&cs->lock, flags);
363 return IRQ_HANDLED;
364 }
365
366 static inline void
367 MemwaitforCEC(struct IsdnCardState *cs, int hscx)
368 {
369 int to = 50;
370
371 while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
372 udelay(1);
373 to--;
374 }
375 if (!to)
376 printk(KERN_WARNING "HiSax: waitforCEC timeout\n");
377 }
378
379
380 static inline void
381 MemwaitforXFW(struct IsdnCardState *cs, int hscx)
382 {
383 int to = 50;
384
385 while (((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) {
386 udelay(1);
387 to--;
388 }
389 if (!to)
390 printk(KERN_WARNING "HiSax: waitforXFW timeout\n");
391 }
392
393 static inline void
394 MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data)
395 {
396 MemwaitforCEC(cs, hscx);
397 MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
398 }
399
400 static void
401 Memhscx_empty_fifo(struct BCState *bcs, int count)
402 {
403 u_char *ptr;
404 struct IsdnCardState *cs = bcs->cs;
405 int cnt;
406
407 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
408 debugl1(cs, "hscx_empty_fifo");
409
410 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
411 if (cs->debug & L1_DEB_WARN)
412 debugl1(cs, "hscx_empty_fifo: incoming packet too large");
413 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
414 bcs->hw.hscx.rcvidx = 0;
415 return;
416 }
417 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
418 cnt = count;
419 while (cnt--)
420 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);
421 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
422 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
423 bcs->hw.hscx.rcvidx += count;
424 if (cs->debug & L1_DEB_HSCX_FIFO) {
425 char *t = bcs->blog;
426
427 t += sprintf(t, "hscx_empty_fifo %c cnt %d",
428 bcs->hw.hscx.hscx ? 'B' : 'A', count);
429 QuickHex(t, ptr, count);
430 debugl1(cs, "%s", bcs->blog);
431 }
432 }
433
434 static void
435 Memhscx_fill_fifo(struct BCState *bcs)
436 {
437 struct IsdnCardState *cs = bcs->cs;
438 int more, count, cnt;
439 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
440 u_char *ptr, *p;
441
442 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
443 debugl1(cs, "hscx_fill_fifo");
444
445 if (!bcs->tx_skb)
446 return;
447 if (bcs->tx_skb->len <= 0)
448 return;
449
450 more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
451 if (bcs->tx_skb->len > fifo_size) {
452 more = !0;
453 count = fifo_size;
454 } else
455 count = bcs->tx_skb->len;
456 cnt = count;
457 MemwaitforXFW(cs, bcs->hw.hscx.hscx);
458 p = ptr = bcs->tx_skb->data;
459 skb_pull(bcs->tx_skb, count);
460 bcs->tx_cnt -= count;
461 bcs->hw.hscx.count += count;
462 while (cnt--)
463 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,
464 *p++);
465 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
466 if (cs->debug & L1_DEB_HSCX_FIFO) {
467 char *t = bcs->blog;
468
469 t += sprintf(t, "hscx_fill_fifo %c cnt %d",
470 bcs->hw.hscx.hscx ? 'B' : 'A', count);
471 QuickHex(t, ptr, count);
472 debugl1(cs, "%s", bcs->blog);
473 }
474 }
475
476 static void
477 Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx)
478 {
479 u_char r;
480 struct BCState *bcs = cs->bcs + hscx;
481 struct sk_buff *skb;
482 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32;
483 int count;
484
485 if (!test_bit(BC_FLG_INIT, &bcs->Flag))
486 return;
487
488 if (val & 0x80) { /* RME */
489 r = MemReadHSCX(cs, hscx, HSCX_RSTA);
490 if ((r & 0xf0) != 0xa0) {
491 if (!(r & 0x80))
492 if (cs->debug & L1_DEB_WARN)
493 debugl1(cs, "HSCX invalid frame");
494 if ((r & 0x40) && bcs->mode)
495 if (cs->debug & L1_DEB_WARN)
496 debugl1(cs, "HSCX RDO mode=%d",
497 bcs->mode);
498 if (!(r & 0x20))
499 if (cs->debug & L1_DEB_WARN)
500 debugl1(cs, "HSCX CRC error");
501 MemWriteHSCXCMDR(cs, hscx, 0x80);
502 } else {
503 count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
504 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x3f : 0x1f);
505 if (count == 0)
506 count = fifo_size;
507 Memhscx_empty_fifo(bcs, count);
508 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
509 if (cs->debug & L1_DEB_HSCX_FIFO)
510 debugl1(cs, "HX Frame %d", count);
511 if (!(skb = dev_alloc_skb(count)))
512 printk(KERN_WARNING "HSCX: receive out of memory\n");
513 else {
514 skb_put_data(skb, bcs->hw.hscx.rcvbuf,
515 count);
516 skb_queue_tail(&bcs->rqueue, skb);
517 }
518 }
519 }
520 bcs->hw.hscx.rcvidx = 0;
521 schedule_event(bcs, B_RCVBUFREADY);
522 }
523 if (val & 0x40) { /* RPF */
524 Memhscx_empty_fifo(bcs, fifo_size);
525 if (bcs->mode == L1_MODE_TRANS) {
526 /* receive audio data */
527 if (!(skb = dev_alloc_skb(fifo_size)))
528 printk(KERN_WARNING "HiSax: receive out of memory\n");
529 else {
530 skb_put_data(skb, bcs->hw.hscx.rcvbuf,
531 fifo_size);
532 skb_queue_tail(&bcs->rqueue, skb);
533 }
534 bcs->hw.hscx.rcvidx = 0;
535 schedule_event(bcs, B_RCVBUFREADY);
536 }
537 }
538 if (val & 0x10) { /* XPR */
539 if (bcs->tx_skb) {
540 if (bcs->tx_skb->len) {
541 Memhscx_fill_fifo(bcs);
542 return;
543 } else {
544 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
545 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
546 u_long flags;
547 spin_lock_irqsave(&bcs->aclock, flags);
548 bcs->ackcnt += bcs->hw.hscx.count;
549 spin_unlock_irqrestore(&bcs->aclock, flags);
550 schedule_event(bcs, B_ACKPENDING);
551 }
552 dev_kfree_skb_irq(bcs->tx_skb);
553 bcs->hw.hscx.count = 0;
554 bcs->tx_skb = NULL;
555 }
556 }
557 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
558 bcs->hw.hscx.count = 0;
559 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
560 Memhscx_fill_fifo(bcs);
561 } else {
562 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
563 schedule_event(bcs, B_XMTBUFREADY);
564 }
565 }
566 }
567
568 static inline void
569 Memhscx_int_main(struct IsdnCardState *cs, u_char val)
570 {
571
572 u_char exval;
573 struct BCState *bcs;
574
575 if (val & 0x01) { // EXB
576 bcs = cs->bcs + 1;
577 exval = MemReadHSCX(cs, 1, HSCX_EXIR);
578 if (exval & 0x40) {
579 if (bcs->mode == 1)
580 Memhscx_fill_fifo(bcs);
581 else {
582 /* Here we lost an TX interrupt, so
583 * restart transmitting the whole frame.
584 */
585 if (bcs->tx_skb) {
586 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
587 bcs->tx_cnt += bcs->hw.hscx.count;
588 bcs->hw.hscx.count = 0;
589 }
590 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
591 if (cs->debug & L1_DEB_WARN)
592 debugl1(cs, "HSCX B EXIR %x Lost TX", exval);
593 }
594 } else if (cs->debug & L1_DEB_HSCX)
595 debugl1(cs, "HSCX B EXIR %x", exval);
596 }
597 if (val & 0xf8) {
598 if (cs->debug & L1_DEB_HSCX)
599 debugl1(cs, "HSCX B interrupt %x", val);
600 Memhscx_interrupt(cs, val, 1);
601 }
602 if (val & 0x02) { // EXA
603 bcs = cs->bcs;
604 exval = MemReadHSCX(cs, 0, HSCX_EXIR);
605 if (exval & 0x40) {
606 if (bcs->mode == L1_MODE_TRANS)
607 Memhscx_fill_fifo(bcs);
608 else {
609 /* Here we lost an TX interrupt, so
610 * restart transmitting the whole frame.
611 */
612 if (bcs->tx_skb) {
613 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
614 bcs->tx_cnt += bcs->hw.hscx.count;
615 bcs->hw.hscx.count = 0;
616 }
617 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);
618 if (cs->debug & L1_DEB_WARN)
619 debugl1(cs, "HSCX A EXIR %x Lost TX", exval);
620 }
621 } else if (cs->debug & L1_DEB_HSCX)
622 debugl1(cs, "HSCX A EXIR %x", exval);
623 }
624 if (val & 0x04) { // ICA
625 exval = MemReadHSCX(cs, 0, HSCX_ISTA);
626 if (cs->debug & L1_DEB_HSCX)
627 debugl1(cs, "HSCX A interrupt %x", exval);
628 Memhscx_interrupt(cs, exval, 0);
629 }
630 }
631
632 static irqreturn_t
633 diva_irq_ipac_pci(int intno, void *dev_id)
634 {
635 struct IsdnCardState *cs = dev_id;
636 u_char ista, val;
637 int icnt = 5;
638 u_char *cfg;
639 u_long flags;
640
641 spin_lock_irqsave(&cs->lock, flags);
642 cfg = (u_char *) cs->hw.diva.pci_cfg;
643 val = *cfg;
644 if (!(val & PITA_INT0_STATUS)) {
645 spin_unlock_irqrestore(&cs->lock, flags);
646 return IRQ_NONE; /* other shared IRQ */
647 }
648 *cfg = PITA_INT0_STATUS; /* Reset pending INT0 */
649 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
650 Start_IPACPCI:
651 if (cs->debug & L1_DEB_IPAC)
652 debugl1(cs, "IPAC ISTA %02X", ista);
653 if (ista & 0x0f) {
654 val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);
655 if (ista & 0x01)
656 val |= 0x01;
657 if (ista & 0x04)
658 val |= 0x02;
659 if (ista & 0x08)
660 val |= 0x04;
661 if (val)
662 Memhscx_int_main(cs, val);
663 }
664 if (ista & 0x20) {
665 val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);
666 if (val) {
667 isac_interrupt(cs, val);
668 }
669 }
670 if (ista & 0x10) {
671 val = 0x01;
672 isac_interrupt(cs, val);
673 }
674 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);
675 if ((ista & 0x3f) && icnt) {
676 icnt--;
677 goto Start_IPACPCI;
678 }
679 if (!icnt)
680 printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");
681 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);
682 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);
683 spin_unlock_irqrestore(&cs->lock, flags);
684 return IRQ_HANDLED;
685 }
686
687 static irqreturn_t
688 diva_irq_ipacx_pci(int intno, void *dev_id)
689 {
690 struct IsdnCardState *cs = dev_id;
691 u_char val;
692 u_char *cfg;
693 u_long flags;
694
695 spin_lock_irqsave(&cs->lock, flags);
696 cfg = (u_char *) cs->hw.diva.pci_cfg;
697 val = *cfg;
698 if (!(val & PITA_INT0_STATUS)) {
699 spin_unlock_irqrestore(&cs->lock, flags);
700 return IRQ_NONE; // other shared IRQ
701 }
702 interrupt_ipacx(cs); // handler for chip
703 *cfg = PITA_INT0_STATUS; // Reset PLX interrupt
704 spin_unlock_irqrestore(&cs->lock, flags);
705 return IRQ_HANDLED;
706 }
707
708 static void
709 release_io_diva(struct IsdnCardState *cs)
710 {
711 int bytecnt;
712
713 if ((cs->subtyp == DIVA_IPAC_PCI) ||
714 (cs->subtyp == DIVA_IPACX_PCI)) {
715 u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;
716
717 *cfg = 0; /* disable INT0/1 */
718 *cfg = 2; /* reset pending INT0 */
719 if (cs->hw.diva.cfg_reg)
720 iounmap((void *)cs->hw.diva.cfg_reg);
721 if (cs->hw.diva.pci_cfg)
722 iounmap((void *)cs->hw.diva.pci_cfg);
723 return;
724 } else if (cs->subtyp != DIVA_IPAC_ISA) {
725 del_timer(&cs->hw.diva.tl);
726 if (cs->hw.diva.cfg_reg)
727 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */
728 }
729 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
730 bytecnt = 8;
731 else
732 bytecnt = 32;
733 if (cs->hw.diva.cfg_reg) {
734 release_region(cs->hw.diva.cfg_reg, bytecnt);
735 }
736 }
737
738 static void
739 iounmap_diva(struct IsdnCardState *cs)
740 {
741 if ((cs->subtyp == DIVA_IPAC_PCI) || (cs->subtyp == DIVA_IPACX_PCI)) {
742 if (cs->hw.diva.cfg_reg) {
743 iounmap((void *)cs->hw.diva.cfg_reg);
744 cs->hw.diva.cfg_reg = 0;
745 }
746 if (cs->hw.diva.pci_cfg) {
747 iounmap((void *)cs->hw.diva.pci_cfg);
748 cs->hw.diva.pci_cfg = 0;
749 }
750 }
751
752 return;
753 }
754
755 static void
756 reset_diva(struct IsdnCardState *cs)
757 {
758 if (cs->subtyp == DIVA_IPAC_ISA) {
759 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);
760 mdelay(10);
761 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);
762 mdelay(10);
763 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);
764 } else if (cs->subtyp == DIVA_IPAC_PCI) {
765 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
766 PITA_MISC_REG);
767 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
768 mdelay(10);
769 *ireg = PITA_PARA_MPX_MODE;
770 mdelay(10);
771 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);
772 } else if (cs->subtyp == DIVA_IPACX_PCI) {
773 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +
774 PITA_MISC_REG);
775 *ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;
776 mdelay(10);
777 *ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;
778 mdelay(10);
779 MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off
780 } else { /* DIVA 2.0 */
781 cs->hw.diva.ctrl_reg = 0; /* Reset On */
782 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
783 mdelay(10);
784 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */
785 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
786 mdelay(10);
787 if (cs->subtyp == DIVA_ISA)
788 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;
789 else {
790 /* Workaround PCI9060 */
791 byteout(cs->hw.diva.pci_cfg + 0x69, 9);
792 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;
793 }
794 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
795 }
796 }
797
798 #define DIVA_ASSIGN 1
799
800 static void
801 diva_led_handler(struct timer_list *t)
802 {
803 struct IsdnCardState *cs = from_timer(cs, t, hw.diva.tl);
804 int blink = 0;
805
806 if ((cs->subtyp == DIVA_IPAC_ISA) ||
807 (cs->subtyp == DIVA_IPAC_PCI) ||
808 (cs->subtyp == DIVA_IPACX_PCI))
809 return;
810 del_timer(&cs->hw.diva.tl);
811 if (cs->hw.diva.status & DIVA_ASSIGN)
812 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
813 DIVA_ISA_LED_A : DIVA_PCI_LED_A;
814 else {
815 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
816 DIVA_ISA_LED_A : DIVA_PCI_LED_A;
817 blink = 250;
818 }
819 if (cs->hw.diva.status & 0xf000)
820 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ?
821 DIVA_ISA_LED_B : DIVA_PCI_LED_B;
822 else if (cs->hw.diva.status & 0x0f00) {
823 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ?
824 DIVA_ISA_LED_B : DIVA_PCI_LED_B;
825 blink = 500;
826 } else
827 cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ?
828 DIVA_ISA_LED_B : DIVA_PCI_LED_B);
829
830 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);
831 if (blink) {
832 cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000);
833 add_timer(&cs->hw.diva.tl);
834 }
835 }
836
837 static int
838 Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg)
839 {
840 u_int *ireg;
841 u_long flags;
842
843 switch (mt) {
844 case CARD_RESET:
845 spin_lock_irqsave(&cs->lock, flags);
846 reset_diva(cs);
847 spin_unlock_irqrestore(&cs->lock, flags);
848 return (0);
849 case CARD_RELEASE:
850 release_io_diva(cs);
851 return (0);
852 case CARD_INIT:
853 spin_lock_irqsave(&cs->lock, flags);
854 reset_diva(cs);
855 if (cs->subtyp == DIVA_IPACX_PCI) {
856 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
857 *ireg = PITA_INT0_ENABLE;
858 init_ipacx(cs, 3); // init chip and enable interrupts
859 spin_unlock_irqrestore(&cs->lock, flags);
860 return (0);
861 }
862 if (cs->subtyp == DIVA_IPAC_PCI) {
863 ireg = (unsigned int *)cs->hw.diva.pci_cfg;
864 *ireg = PITA_INT0_ENABLE;
865 }
866 inithscxisac(cs, 3);
867 spin_unlock_irqrestore(&cs->lock, flags);
868 return (0);
869 case CARD_TEST:
870 return (0);
871 case (MDL_REMOVE | REQUEST):
872 cs->hw.diva.status = 0;
873 break;
874 case (MDL_ASSIGN | REQUEST):
875 cs->hw.diva.status |= DIVA_ASSIGN;
876 break;
877 case MDL_INFO_SETUP:
878 if ((long)arg)
879 cs->hw.diva.status |= 0x0200;
880 else
881 cs->hw.diva.status |= 0x0100;
882 break;
883 case MDL_INFO_CONN:
884 if ((long)arg)
885 cs->hw.diva.status |= 0x2000;
886 else
887 cs->hw.diva.status |= 0x1000;
888 break;
889 case MDL_INFO_REL:
890 if ((long)arg) {
891 cs->hw.diva.status &= ~0x2000;
892 cs->hw.diva.status &= ~0x0200;
893 } else {
894 cs->hw.diva.status &= ~0x1000;
895 cs->hw.diva.status &= ~0x0100;
896 }
897 break;
898 }
899 if ((cs->subtyp != DIVA_IPAC_ISA) &&
900 (cs->subtyp != DIVA_IPAC_PCI) &&
901 (cs->subtyp != DIVA_IPACX_PCI)) {
902 spin_lock_irqsave(&cs->lock, flags);
903 diva_led_handler(&cs->hw.diva.tl);
904 spin_unlock_irqrestore(&cs->lock, flags);
905 }
906 return (0);
907 }
908
909 static int setup_diva_common(struct IsdnCardState *cs)
910 {
911 int bytecnt;
912 u_char val;
913
914 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))
915 bytecnt = 8;
916 else
917 bytecnt = 32;
918
919 printk(KERN_INFO
920 "Diva: %s card configured at %#lx IRQ %d\n",
921 (cs->subtyp == DIVA_PCI) ? "PCI" :
922 (cs->subtyp == DIVA_ISA) ? "ISA" :
923 (cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" :
924 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
925 cs->hw.diva.cfg_reg, cs->irq);
926 if ((cs->subtyp == DIVA_IPAC_PCI) ||
927 (cs->subtyp == DIVA_IPACX_PCI) ||
928 (cs->subtyp == DIVA_PCI))
929 printk(KERN_INFO "Diva: %s space at %#lx\n",
930 (cs->subtyp == DIVA_PCI) ? "PCI" :
931 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI",
932 cs->hw.diva.pci_cfg);
933 if ((cs->subtyp != DIVA_IPAC_PCI) &&
934 (cs->subtyp != DIVA_IPACX_PCI)) {
935 if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) {
936 printk(KERN_WARNING
937 "HiSax: %s config port %lx-%lx already in use\n",
938 "diva",
939 cs->hw.diva.cfg_reg,
940 cs->hw.diva.cfg_reg + bytecnt);
941 iounmap_diva(cs);
942 return (0);
943 }
944 }
945 cs->BC_Read_Reg = &ReadHSCX;
946 cs->BC_Write_Reg = &WriteHSCX;
947 cs->BC_Send_Data = &hscx_fill_fifo;
948 cs->cardmsg = &Diva_card_msg;
949 setup_isac(cs);
950 if (cs->subtyp == DIVA_IPAC_ISA) {
951 cs->readisac = &ReadISAC_IPAC;
952 cs->writeisac = &WriteISAC_IPAC;
953 cs->readisacfifo = &ReadISACfifo_IPAC;
954 cs->writeisacfifo = &WriteISACfifo_IPAC;
955 cs->irq_func = &diva_irq_ipac_isa;
956 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID);
957 printk(KERN_INFO "Diva: IPAC version %x\n", val);
958 } else if (cs->subtyp == DIVA_IPAC_PCI) {
959 cs->readisac = &MemReadISAC_IPAC;
960 cs->writeisac = &MemWriteISAC_IPAC;
961 cs->readisacfifo = &MemReadISACfifo_IPAC;
962 cs->writeisacfifo = &MemWriteISACfifo_IPAC;
963 cs->BC_Read_Reg = &MemReadHSCX;
964 cs->BC_Write_Reg = &MemWriteHSCX;
965 cs->BC_Send_Data = &Memhscx_fill_fifo;
966 cs->irq_func = &diva_irq_ipac_pci;
967 val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID);
968 printk(KERN_INFO "Diva: IPAC version %x\n", val);
969 } else if (cs->subtyp == DIVA_IPACX_PCI) {
970 cs->readisac = &MemReadISAC_IPACX;
971 cs->writeisac = &MemWriteISAC_IPACX;
972 cs->readisacfifo = &MemReadISACfifo_IPACX;
973 cs->writeisacfifo = &MemWriteISACfifo_IPACX;
974 cs->BC_Read_Reg = &MemReadHSCX_IPACX;
975 cs->BC_Write_Reg = &MemWriteHSCX_IPACX;
976 cs->BC_Send_Data = NULL; // function located in ipacx module
977 cs->irq_func = &diva_irq_ipacx_pci;
978 printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
979 MemReadISAC_IPACX(cs, IPACX_ID) & 0x3F);
980 } else { /* DIVA 2.0 */
981 timer_setup(&cs->hw.diva.tl, diva_led_handler, 0);
982 cs->readisac = &ReadISAC;
983 cs->writeisac = &WriteISAC;
984 cs->readisacfifo = &ReadISACfifo;
985 cs->writeisacfifo = &WriteISACfifo;
986 cs->irq_func = &diva_interrupt;
987 ISACVersion(cs, "Diva:");
988 if (HscxVersion(cs, "Diva:")) {
989 printk(KERN_WARNING
990 "Diva: wrong HSCX versions check IO address\n");
991 release_io_diva(cs);
992 return (0);
993 }
994 }
995 return (1);
996 }
997
998 #ifdef CONFIG_ISA
999
1000 static int setup_diva_isa(struct IsdnCard *card)
1001 {
1002 struct IsdnCardState *cs = card->cs;
1003 u_char val;
1004
1005 if (!card->para[1])
1006 return (-1); /* card not found; continue search */
1007
1008 cs->hw.diva.ctrl_reg = 0;
1009 cs->hw.diva.cfg_reg = card->para[1];
1010 val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR,
1011 cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID);
1012 printk(KERN_INFO "Diva: IPAC version %x\n", val);
1013 if ((val == 1) || (val == 2)) {
1014 cs->subtyp = DIVA_IPAC_ISA;
1015 cs->hw.diva.ctrl = 0;
1016 cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA;
1017 cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA;
1018 cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR;
1019 cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR;
1020 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1021 } else {
1022 cs->subtyp = DIVA_ISA;
1023 cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL;
1024 cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA;
1025 cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA;
1026 cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR;
1027 cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR;
1028 }
1029 cs->irq = card->para[0];
1030
1031 return (1); /* card found */
1032 }
1033
1034 #else /* if !CONFIG_ISA */
1035
1036 static int setup_diva_isa(struct IsdnCard *card)
1037 {
1038 return (-1); /* card not found; continue search */
1039 }
1040
1041 #endif /* CONFIG_ISA */
1042
1043 #ifdef __ISAPNP__
1044 static struct isapnp_device_id diva_ids[] = {
1045 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1046 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1047 (unsigned long) "Diva picola" },
1048 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
1049 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x51),
1050 (unsigned long) "Diva picola" },
1051 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1052 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1053 (unsigned long) "Diva 2.0" },
1054 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
1055 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x71),
1056 (unsigned long) "Diva 2.0" },
1057 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1058 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1059 (unsigned long) "Diva 2.01" },
1060 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
1061 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0xA1),
1062 (unsigned long) "Diva 2.01" },
1063 { 0, }
1064 };
1065
1066 static struct isapnp_device_id *ipid = &diva_ids[0];
1067 static struct pnp_card *pnp_c = NULL;
1068
1069 static int setup_diva_isapnp(struct IsdnCard *card)
1070 {
1071 struct IsdnCardState *cs = card->cs;
1072 struct pnp_dev *pnp_d;
1073
1074 if (!isapnp_present())
1075 return (-1); /* card not found; continue search */
1076
1077 while (ipid->card_vendor) {
1078 if ((pnp_c = pnp_find_card(ipid->card_vendor,
1079 ipid->card_device, pnp_c))) {
1080 pnp_d = NULL;
1081 if ((pnp_d = pnp_find_dev(pnp_c,
1082 ipid->vendor, ipid->function, pnp_d))) {
1083 int err;
1084
1085 printk(KERN_INFO "HiSax: %s detected\n",
1086 (char *)ipid->driver_data);
1087 pnp_disable_dev(pnp_d);
1088 err = pnp_activate_dev(pnp_d);
1089 if (err < 0) {
1090 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1091 __func__, err);
1092 return (0);
1093 }
1094 card->para[1] = pnp_port_start(pnp_d, 0);
1095 card->para[0] = pnp_irq(pnp_d, 0);
1096 if (card->para[0] == -1 || !card->para[1]) {
1097 printk(KERN_ERR "Diva PnP:some resources are missing %ld/%lx\n",
1098 card->para[0], card->para[1]);
1099 pnp_disable_dev(pnp_d);
1100 return (0);
1101 }
1102 cs->hw.diva.cfg_reg = card->para[1];
1103 cs->irq = card->para[0];
1104 if (ipid->function == ISAPNP_FUNCTION(0xA1)) {
1105 cs->subtyp = DIVA_IPAC_ISA;
1106 cs->hw.diva.ctrl = 0;
1107 cs->hw.diva.isac =
1108 card->para[1] + DIVA_IPAC_DATA;
1109 cs->hw.diva.hscx =
1110 card->para[1] + DIVA_IPAC_DATA;
1111 cs->hw.diva.isac_adr =
1112 card->para[1] + DIVA_IPAC_ADR;
1113 cs->hw.diva.hscx_adr =
1114 card->para[1] + DIVA_IPAC_ADR;
1115 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1116 } else {
1117 cs->subtyp = DIVA_ISA;
1118 cs->hw.diva.ctrl =
1119 card->para[1] + DIVA_ISA_CTRL;
1120 cs->hw.diva.isac =
1121 card->para[1] + DIVA_ISA_ISAC_DATA;
1122 cs->hw.diva.hscx =
1123 card->para[1] + DIVA_HSCX_DATA;
1124 cs->hw.diva.isac_adr =
1125 card->para[1] + DIVA_ISA_ISAC_ADR;
1126 cs->hw.diva.hscx_adr =
1127 card->para[1] + DIVA_HSCX_ADR;
1128 }
1129 return (1); /* card found */
1130 } else {
1131 printk(KERN_ERR "Diva PnP: PnP error card found, no device\n");
1132 return (0);
1133 }
1134 }
1135 ipid++;
1136 pnp_c = NULL;
1137 }
1138
1139 return (-1); /* card not found; continue search */
1140 }
1141
1142 #else /* if !ISAPNP */
1143
1144 static int setup_diva_isapnp(struct IsdnCard *card)
1145 {
1146 return (-1); /* card not found; continue search */
1147 }
1148
1149 #endif /* ISAPNP */
1150
1151 #ifdef CONFIG_PCI
1152 static struct pci_dev *dev_diva = NULL;
1153 static struct pci_dev *dev_diva_u = NULL;
1154 static struct pci_dev *dev_diva201 = NULL;
1155 static struct pci_dev *dev_diva202 = NULL;
1156
1157 static int setup_diva_pci(struct IsdnCard *card)
1158 {
1159 struct IsdnCardState *cs = card->cs;
1160
1161 cs->subtyp = 0;
1162 if ((dev_diva = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1163 PCI_DEVICE_ID_EICON_DIVA20, dev_diva))) {
1164 if (pci_enable_device(dev_diva))
1165 return (0);
1166 cs->subtyp = DIVA_PCI;
1167 cs->irq = dev_diva->irq;
1168 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2);
1169 } else if ((dev_diva_u = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1170 PCI_DEVICE_ID_EICON_DIVA20_U, dev_diva_u))) {
1171 if (pci_enable_device(dev_diva_u))
1172 return (0);
1173 cs->subtyp = DIVA_PCI;
1174 cs->irq = dev_diva_u->irq;
1175 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2);
1176 } else if ((dev_diva201 = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1177 PCI_DEVICE_ID_EICON_DIVA201, dev_diva201))) {
1178 if (pci_enable_device(dev_diva201))
1179 return (0);
1180 cs->subtyp = DIVA_IPAC_PCI;
1181 cs->irq = dev_diva201->irq;
1182 cs->hw.diva.pci_cfg =
1183 (ulong) ioremap(pci_resource_start(dev_diva201, 0), 4096);
1184 cs->hw.diva.cfg_reg =
1185 (ulong) ioremap(pci_resource_start(dev_diva201, 1), 4096);
1186 } else if ((dev_diva202 = hisax_find_pci_device(PCI_VENDOR_ID_EICON,
1187 PCI_DEVICE_ID_EICON_DIVA202, dev_diva202))) {
1188 if (pci_enable_device(dev_diva202))
1189 return (0);
1190 cs->subtyp = DIVA_IPACX_PCI;
1191 cs->irq = dev_diva202->irq;
1192 cs->hw.diva.pci_cfg =
1193 (ulong) ioremap(pci_resource_start(dev_diva202, 0), 4096);
1194 cs->hw.diva.cfg_reg =
1195 (ulong) ioremap(pci_resource_start(dev_diva202, 1), 4096);
1196 } else {
1197 return (-1); /* card not found; continue search */
1198 }
1199
1200 if (!cs->irq) {
1201 printk(KERN_WARNING "Diva: No IRQ for PCI card found\n");
1202 iounmap_diva(cs);
1203 return (0);
1204 }
1205
1206 if (!cs->hw.diva.cfg_reg) {
1207 printk(KERN_WARNING "Diva: No IO-Adr for PCI card found\n");
1208 iounmap_diva(cs);
1209 return (0);
1210 }
1211 cs->irq_flags |= IRQF_SHARED;
1212
1213 if ((cs->subtyp == DIVA_IPAC_PCI) ||
1214 (cs->subtyp == DIVA_IPACX_PCI)) {
1215 cs->hw.diva.ctrl = 0;
1216 cs->hw.diva.isac = 0;
1217 cs->hw.diva.hscx = 0;
1218 cs->hw.diva.isac_adr = 0;
1219 cs->hw.diva.hscx_adr = 0;
1220 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
1221 } else {
1222 cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL;
1223 cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA;
1224 cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA;
1225 cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR;
1226 cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR;
1227 }
1228
1229 return (1); /* card found */
1230 }
1231
1232 #else /* if !CONFIG_PCI */
1233
1234 static int setup_diva_pci(struct IsdnCard *card)
1235 {
1236 return (-1); /* card not found; continue search */
1237 }
1238
1239 #endif /* CONFIG_PCI */
1240
1241 int setup_diva(struct IsdnCard *card)
1242 {
1243 int rc, have_card = 0;
1244 struct IsdnCardState *cs = card->cs;
1245 char tmp[64];
1246
1247 strcpy(tmp, Diva_revision);
1248 printk(KERN_INFO "HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp));
1249 if (cs->typ != ISDN_CTYPE_DIEHLDIVA)
1250 return (0);
1251 cs->hw.diva.status = 0;
1252
1253 rc = setup_diva_isa(card);
1254 if (!rc)
1255 return rc;
1256 if (rc > 0) {
1257 have_card = 1;
1258 goto ready;
1259 }
1260
1261 rc = setup_diva_isapnp(card);
1262 if (!rc)
1263 return rc;
1264 if (rc > 0) {
1265 have_card = 1;
1266 goto ready;
1267 }
1268
1269 rc = setup_diva_pci(card);
1270 if (!rc)
1271 return rc;
1272 if (rc > 0)
1273 have_card = 1;
1274
1275 ready:
1276 if (!have_card) {
1277 printk(KERN_WARNING "Diva: No ISA, ISAPNP or PCI card found\n");
1278 return (0);
1279 }
1280
1281 return setup_diva_common(card->cs);
1282 }
CRIS linux kernel tree