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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / media / dvb-frontends / mxl5xx.c
blobe899821018a0b5431f23ac9833527043060742b7
1 /*
2 * Driver for the MaxLinear MxL5xx family of tuners/demods
3 *
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
7 *
8 * based on code:
9 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
10 * which was released under GPL V2
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/firmware.h>
29 #include <linux/i2c.h>
30 #include <linux/version.h>
31 #include <linux/mutex.h>
32 #include <linux/vmalloc.h>
33 #include <asm/div64.h>
34 #include <asm/unaligned.h>
35
36 #include <media/dvb_frontend.h>
37 #include "mxl5xx.h"
38 #include "mxl5xx_regs.h"
39 #include "mxl5xx_defs.h"
40
41 #define BYTE0(v) ((v >> 0) & 0xff)
42 #define BYTE1(v) ((v >> 8) & 0xff)
43 #define BYTE2(v) ((v >> 16) & 0xff)
44 #define BYTE3(v) ((v >> 24) & 0xff)
45
46 static LIST_HEAD(mxllist);
47
48 struct mxl_base {
49 struct list_head mxllist;
50 struct list_head mxls;
51
52 u8 adr;
53 struct i2c_adapter *i2c;
54
55 u32 count;
56 u32 type;
57 u32 sku_type;
58 u32 chipversion;
59 u32 clock;
60 u32 fwversion;
61
62 u8 *ts_map;
63 u8 can_clkout;
64 u8 chan_bond;
65 u8 demod_num;
66 u8 tuner_num;
67
68 unsigned long next_tune;
69
70 struct mutex i2c_lock;
71 struct mutex status_lock;
72 struct mutex tune_lock;
73
74 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
75
76 u32 cmd_size;
77 u8 cmd_data[MAX_CMD_DATA];
78 };
79
80 struct mxl {
81 struct list_head mxl;
82
83 struct mxl_base *base;
84 struct dvb_frontend fe;
85 struct device *i2cdev;
86 u32 demod;
87 u32 tuner;
88 u32 tuner_in_use;
89 u8 xbar[3];
90
91 unsigned long tune_time;
92 };
93
94 static void convert_endian(u8 flag, u32 size, u8 *d)
95 {
96 u32 i;
97
98 if (!flag)
99 return;
100 for (i = 0; i < (size & ~3); i += 4) {
101 d[i + 0] ^= d[i + 3];
102 d[i + 3] ^= d[i + 0];
103 d[i + 0] ^= d[i + 3];
104
105 d[i + 1] ^= d[i + 2];
106 d[i + 2] ^= d[i + 1];
107 d[i + 1] ^= d[i + 2];
108 }
109
110 switch (size & 3) {
111 case 0:
112 case 1:
113 /* do nothing */
114 break;
115 case 2:
116 d[i + 0] ^= d[i + 1];
117 d[i + 1] ^= d[i + 0];
118 d[i + 0] ^= d[i + 1];
119 break;
120
121 case 3:
122 d[i + 0] ^= d[i + 2];
123 d[i + 2] ^= d[i + 0];
124 d[i + 0] ^= d[i + 2];
125 break;
126 }
127
128 }
129
130 static int i2c_write(struct i2c_adapter *adap, u8 adr,
131 u8 *data, u32 len)
132 {
133 struct i2c_msg msg = {.addr = adr, .flags = 0,
134 .buf = data, .len = len};
135
136 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
137 }
138
139 static int i2c_read(struct i2c_adapter *adap, u8 adr,
140 u8 *data, u32 len)
141 {
142 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
143 .buf = data, .len = len};
144
145 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
146 }
147
148 static int i2cread(struct mxl *state, u8 *data, int len)
149 {
150 return i2c_read(state->base->i2c, state->base->adr, data, len);
151 }
152
153 static int i2cwrite(struct mxl *state, u8 *data, int len)
154 {
155 return i2c_write(state->base->i2c, state->base->adr, data, len);
156 }
157
158 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
159 {
160 int stat;
161 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
162 MXL_HYDRA_PLID_REG_READ, 0x04,
163 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
164 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
165 };
166
167 stat = i2cwrite(state, data,
168 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
169 if (stat)
170 dev_err(state->i2cdev, "i2c read error 1\n");
171 if (!stat)
172 stat = i2cread(state, (u8 *) val,
173 MXL_HYDRA_REG_SIZE_IN_BYTES);
174 le32_to_cpus(val);
175 if (stat)
176 dev_err(state->i2cdev, "i2c read error 2\n");
177 return stat;
178 }
179
180 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C
181 #define DMA_INTR_PROT_WR_CMP 0x08
182
183 static int send_command(struct mxl *state, u32 size, u8 *buf)
184 {
185 int stat;
186 u32 val, count = 10;
187
188 mutex_lock(&state->base->i2c_lock);
189 if (state->base->fwversion > 0x02010109) {
190 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
191 if (DMA_INTR_PROT_WR_CMP & val)
192 dev_info(state->i2cdev, "%s busy\n", __func__);
193 while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
194 mutex_unlock(&state->base->i2c_lock);
195 usleep_range(1000, 2000);
196 mutex_lock(&state->base->i2c_lock);
197 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
198 &val);
199 }
200 if (!count) {
201 dev_info(state->i2cdev, "%s busy\n", __func__);
202 mutex_unlock(&state->base->i2c_lock);
203 return -EBUSY;
204 }
205 }
206 stat = i2cwrite(state, buf, size);
207 mutex_unlock(&state->base->i2c_lock);
208 return stat;
209 }
210
211 static int write_register(struct mxl *state, u32 reg, u32 val)
212 {
213 int stat;
214 u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
215 MXL_HYDRA_PLID_REG_WRITE, 0x08,
216 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
217 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
218 };
219 mutex_lock(&state->base->i2c_lock);
220 stat = i2cwrite(state, data, sizeof(data));
221 mutex_unlock(&state->base->i2c_lock);
222 if (stat)
223 dev_err(state->i2cdev, "i2c write error\n");
224 return stat;
225 }
226
227 static int write_firmware_block(struct mxl *state,
228 u32 reg, u32 size, u8 *reg_data_ptr)
229 {
230 int stat;
231 u8 *buf = state->base->buf;
232
233 mutex_lock(&state->base->i2c_lock);
234 buf[0] = MXL_HYDRA_PLID_REG_WRITE;
235 buf[1] = size + 4;
236 buf[2] = GET_BYTE(reg, 0);
237 buf[3] = GET_BYTE(reg, 1);
238 buf[4] = GET_BYTE(reg, 2);
239 buf[5] = GET_BYTE(reg, 3);
240 memcpy(&buf[6], reg_data_ptr, size);
241 stat = i2cwrite(state, buf,
242 MXL_HYDRA_I2C_HDR_SIZE +
243 MXL_HYDRA_REG_SIZE_IN_BYTES + size);
244 mutex_unlock(&state->base->i2c_lock);
245 if (stat)
246 dev_err(state->i2cdev, "fw block write failed\n");
247 return stat;
248 }
249
250 static int read_register(struct mxl *state, u32 reg, u32 *val)
251 {
252 int stat;
253 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
254 MXL_HYDRA_PLID_REG_READ, 0x04,
255 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
256 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
257 };
258
259 mutex_lock(&state->base->i2c_lock);
260 stat = i2cwrite(state, data,
261 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
262 if (stat)
263 dev_err(state->i2cdev, "i2c read error 1\n");
264 if (!stat)
265 stat = i2cread(state, (u8 *) val,
266 MXL_HYDRA_REG_SIZE_IN_BYTES);
267 mutex_unlock(&state->base->i2c_lock);
268 le32_to_cpus(val);
269 if (stat)
270 dev_err(state->i2cdev, "i2c read error 2\n");
271 return stat;
272 }
273
274 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
275 {
276 int stat;
277 u8 *buf = state->base->buf;
278
279 mutex_lock(&state->base->i2c_lock);
280
281 buf[0] = MXL_HYDRA_PLID_REG_READ;
282 buf[1] = size + 4;
283 buf[2] = GET_BYTE(reg, 0);
284 buf[3] = GET_BYTE(reg, 1);
285 buf[4] = GET_BYTE(reg, 2);
286 buf[5] = GET_BYTE(reg, 3);
287 stat = i2cwrite(state, buf,
288 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
289 if (!stat) {
290 stat = i2cread(state, data, size);
291 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
292 }
293 mutex_unlock(&state->base->i2c_lock);
294 return stat;
295 }
296
297 static int read_by_mnemonic(struct mxl *state,
298 u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
299 {
300 u32 data = 0, mask = 0;
301 int stat;
302
303 stat = read_register(state, reg, &data);
304 if (stat)
305 return stat;
306 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
307 data &= mask;
308 data >>= lsbloc;
309 *val = data;
310 return 0;
311 }
312
313
314 static int update_by_mnemonic(struct mxl *state,
315 u32 reg, u8 lsbloc, u8 numofbits, u32 val)
316 {
317 u32 data, mask;
318 int stat;
319
320 stat = read_register(state, reg, &data);
321 if (stat)
322 return stat;
323 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
324 data = (data & ~mask) | ((val << lsbloc) & mask);
325 stat = write_register(state, reg, data);
326 return stat;
327 }
328
329 static int firmware_is_alive(struct mxl *state)
330 {
331 u32 hb0, hb1;
332
333 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
334 return 0;
335 msleep(20);
336 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
337 return 0;
338 if (hb1 == hb0)
339 return 0;
340 return 1;
341 }
342
343 static int init(struct dvb_frontend *fe)
344 {
345 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
346
347 /* init fe stats */
348 p->strength.len = 1;
349 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
350 p->cnr.len = 1;
351 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
352 p->pre_bit_error.len = 1;
353 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
354 p->pre_bit_count.len = 1;
355 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
356 p->post_bit_error.len = 1;
357 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
358 p->post_bit_count.len = 1;
359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
360
361 return 0;
362 }
363
364 static void release(struct dvb_frontend *fe)
365 {
366 struct mxl *state = fe->demodulator_priv;
367
368 list_del(&state->mxl);
369 /* Release one frontend, two more shall take its place! */
370 state->base->count--;
371 if (state->base->count == 0) {
372 list_del(&state->base->mxllist);
373 kfree(state->base);
374 }
375 kfree(state);
376 }
377
378 static int get_algo(struct dvb_frontend *fe)
379 {
380 return DVBFE_ALGO_HW;
381 }
382
383 static int cfg_demod_abort_tune(struct mxl *state)
384 {
385 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
386 u8 cmd_size = sizeof(abort_tune_cmd);
387 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
388
389 abort_tune_cmd.demod_id = state->demod;
390 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
391 cmd_size, &abort_tune_cmd, cmd_buff);
392 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
393 &cmd_buff[0]);
394 }
395
396 static int send_master_cmd(struct dvb_frontend *fe,
397 struct dvb_diseqc_master_cmd *cmd)
398 {
399 /*struct mxl *state = fe->demodulator_priv;*/
400
401 return 0; /*CfgDemodAbortTune(state);*/
402 }
403
404 static int set_parameters(struct dvb_frontend *fe)
405 {
406 struct mxl *state = fe->demodulator_priv;
407 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
408 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
409 u8 cmd_size = sizeof(demod_chan_cfg);
410 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
411 u32 srange = 10;
412 int stat;
413
414 if (p->frequency < 950000 || p->frequency > 2150000)
415 return -EINVAL;
416 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
417 return -EINVAL;
418
419 /* CfgDemodAbortTune(state); */
420
421 switch (p->delivery_system) {
422 case SYS_DSS:
423 demod_chan_cfg.standard = MXL_HYDRA_DSS;
424 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
425 break;
426 case SYS_DVBS:
427 srange = p->symbol_rate / 1000000;
428 if (srange > 10)
429 srange = 10;
430 demod_chan_cfg.standard = MXL_HYDRA_DVBS;
431 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
432 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
433 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
434 break;
435 case SYS_DVBS2:
436 demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
437 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
438 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
439 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
440 /* cfg_scrambler(state); */
441 break;
442 default:
443 return -EINVAL;
444 }
445 demod_chan_cfg.tuner_index = state->tuner;
446 demod_chan_cfg.demod_index = state->demod;
447 demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
448 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
449 demod_chan_cfg.max_carrier_offset_in_mhz = srange;
450 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
451 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
452
453 mutex_lock(&state->base->tune_lock);
454 if (time_after(jiffies + msecs_to_jiffies(200),
455 state->base->next_tune))
456 while (time_before(jiffies, state->base->next_tune))
457 usleep_range(10000, 11000);
458 state->base->next_tune = jiffies + msecs_to_jiffies(100);
459 state->tuner_in_use = state->tuner;
460 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
461 cmd_size, &demod_chan_cfg, cmd_buff);
462 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
463 &cmd_buff[0]);
464 mutex_unlock(&state->base->tune_lock);
465 return stat;
466 }
467
468 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
469
470 static int sleep(struct dvb_frontend *fe)
471 {
472 struct mxl *state = fe->demodulator_priv;
473 struct mxl *p;
474
475 cfg_demod_abort_tune(state);
476 if (state->tuner_in_use != 0xffffffff) {
477 mutex_lock(&state->base->tune_lock);
478 state->tuner_in_use = 0xffffffff;
479 list_for_each_entry(p, &state->base->mxls, mxl) {
480 if (p->tuner_in_use == state->tuner)
481 break;
482 }
483 if (&p->mxl == &state->base->mxls)
484 enable_tuner(state, state->tuner, 0);
485 mutex_unlock(&state->base->tune_lock);
486 }
487 return 0;
488 }
489
490 static int read_snr(struct dvb_frontend *fe)
491 {
492 struct mxl *state = fe->demodulator_priv;
493 int stat;
494 u32 reg_data = 0;
495 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
496
497 mutex_lock(&state->base->status_lock);
498 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
499 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
500 HYDRA_DMD_STATUS_OFFSET(state->demod)),
501 &reg_data);
502 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
503 mutex_unlock(&state->base->status_lock);
504
505 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
506 p->cnr.stat[0].svalue = (s16)reg_data * 10;
507
508 return stat;
509 }
510
511 static int read_ber(struct dvb_frontend *fe)
512 {
513 struct mxl *state = fe->demodulator_priv;
514 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
515 u32 reg[8];
516
517 mutex_lock(&state->base->status_lock);
518 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
519 read_register_block(state,
520 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
521 HYDRA_DMD_STATUS_OFFSET(state->demod)),
522 (4 * sizeof(u32)),
523 (u8 *) &reg[0]);
524 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
525
526 switch (p->delivery_system) {
527 case SYS_DSS:
528 case SYS_DVBS:
529 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
530 p->pre_bit_error.stat[0].uvalue = reg[2];
531 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
532 p->pre_bit_count.stat[0].uvalue = reg[3];
533 break;
534 default:
535 break;
536 }
537
538 read_register_block(state,
539 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
540 HYDRA_DMD_STATUS_OFFSET(state->demod)),
541 (7 * sizeof(u32)),
542 (u8 *) &reg[0]);
543
544 switch (p->delivery_system) {
545 case SYS_DSS:
546 case SYS_DVBS:
547 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
548 p->post_bit_error.stat[0].uvalue = reg[5];
549 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
550 p->post_bit_count.stat[0].uvalue = reg[6];
551 break;
552 case SYS_DVBS2:
553 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
554 p->post_bit_error.stat[0].uvalue = reg[1];
555 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
556 p->post_bit_count.stat[0].uvalue = reg[2];
557 break;
558 default:
559 break;
560 }
561
562 mutex_unlock(&state->base->status_lock);
563
564 return 0;
565 }
566
567 static int read_signal_strength(struct dvb_frontend *fe)
568 {
569 struct mxl *state = fe->demodulator_priv;
570 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
571 int stat;
572 u32 reg_data = 0;
573
574 mutex_lock(&state->base->status_lock);
575 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
576 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
577 HYDRA_DMD_STATUS_OFFSET(state->demod)),
578 &reg_data);
579 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
580 mutex_unlock(&state->base->status_lock);
581
582 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
583 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
584
585 return stat;
586 }
587
588 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
589 {
590 struct mxl *state = fe->demodulator_priv;
591 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
592 u32 reg_data = 0;
593
594 mutex_lock(&state->base->status_lock);
595 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
596 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
597 HYDRA_DMD_STATUS_OFFSET(state->demod)),
598 &reg_data);
599 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
600 mutex_unlock(&state->base->status_lock);
601
602 *status = (reg_data == 1) ? 0x1f : 0;
603
604 /* signal statistics */
605
606 /* signal strength is always available */
607 read_signal_strength(fe);
608
609 if (*status & FE_HAS_CARRIER)
610 read_snr(fe);
611 else
612 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
613
614 if (*status & FE_HAS_SYNC)
615 read_ber(fe);
616 else {
617 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
618 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
619 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
620 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
621 }
622
623 return 0;
624 }
625
626 static int tune(struct dvb_frontend *fe, bool re_tune,
627 unsigned int mode_flags,
628 unsigned int *delay, enum fe_status *status)
629 {
630 struct mxl *state = fe->demodulator_priv;
631 int r = 0;
632
633 *delay = HZ / 2;
634 if (re_tune) {
635 r = set_parameters(fe);
636 if (r)
637 return r;
638 state->tune_time = jiffies;
639 }
640
641 return read_status(fe, status);
642 }
643
644 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
645 {
646 enum fe_code_rate fec2fec[11] = {
647 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
648 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
649 FEC_7_8, FEC_8_9, FEC_9_10
650 };
651
652 if (fec > MXL_HYDRA_FEC_9_10)
653 return FEC_NONE;
654 return fec2fec[fec];
655 }
656
657 static int get_frontend(struct dvb_frontend *fe,
658 struct dtv_frontend_properties *p)
659 {
660 struct mxl *state = fe->demodulator_priv;
661 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
662 u32 freq;
663
664 mutex_lock(&state->base->status_lock);
665 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
666 read_register_block(state,
667 (HYDRA_DMD_STANDARD_ADDR_OFFSET +
668 HYDRA_DMD_STATUS_OFFSET(state->demod)),
669 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
670 (u8 *) &reg_data[0]);
671 /* read demod channel parameters */
672 read_register_block(state,
673 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
674 HYDRA_DMD_STATUS_OFFSET(state->demod)),
675 (4), /* 4 bytes */
676 (u8 *) &freq);
677 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
678 mutex_unlock(&state->base->status_lock);
679
680 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
681 freq * 1000, reg_data[DMD_STANDARD_ADDR],
682 reg_data[DMD_SYMBOL_RATE_ADDR]);
683 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
684 p->frequency = freq;
685 /*
686 * p->delivery_system =
687 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
688 * p->inversion =
689 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
690 * freqSearchRangeKHz =
691 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
692 */
693
694 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
695 switch (p->delivery_system) {
696 case SYS_DSS:
697 break;
698 case SYS_DVBS2:
699 switch ((enum MXL_HYDRA_PILOTS_E)
700 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
701 case MXL_HYDRA_PILOTS_OFF:
702 p->pilot = PILOT_OFF;
703 break;
704 case MXL_HYDRA_PILOTS_ON:
705 p->pilot = PILOT_ON;
706 break;
707 default:
708 break;
709 }
710 case SYS_DVBS:
711 switch ((enum MXL_HYDRA_MODULATION_E)
712 reg_data[DMD_MODULATION_SCHEME_ADDR]) {
713 case MXL_HYDRA_MOD_QPSK:
714 p->modulation = QPSK;
715 break;
716 case MXL_HYDRA_MOD_8PSK:
717 p->modulation = PSK_8;
718 break;
719 default:
720 break;
721 }
722 switch ((enum MXL_HYDRA_ROLLOFF_E)
723 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
724 case MXL_HYDRA_ROLLOFF_0_20:
725 p->rolloff = ROLLOFF_20;
726 break;
727 case MXL_HYDRA_ROLLOFF_0_35:
728 p->rolloff = ROLLOFF_35;
729 break;
730 case MXL_HYDRA_ROLLOFF_0_25:
731 p->rolloff = ROLLOFF_25;
732 break;
733 default:
734 break;
735 }
736 break;
737 default:
738 return -EINVAL;
739 }
740 return 0;
741 }
742
743 static int set_input(struct dvb_frontend *fe, int input)
744 {
745 struct mxl *state = fe->demodulator_priv;
746
747 state->tuner = input;
748 return 0;
749 }
750
751 static struct dvb_frontend_ops mxl_ops = {
752 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
753 .info = {
754 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
755 .frequency_min = 300000,
756 .frequency_max = 2350000,
757 .frequency_stepsize = 0,
758 .frequency_tolerance = 0,
759 .symbol_rate_min = 1000000,
760 .symbol_rate_max = 45000000,
761 .caps = FE_CAN_INVERSION_AUTO |
762 FE_CAN_FEC_AUTO |
763 FE_CAN_QPSK |
764 FE_CAN_2G_MODULATION
765 },
766 .init = init,
767 .release = release,
768 .get_frontend_algo = get_algo,
769 .tune = tune,
770 .read_status = read_status,
771 .sleep = sleep,
772 .get_frontend = get_frontend,
773 .diseqc_send_master_cmd = send_master_cmd,
774 };
775
776 static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr)
777 {
778 struct mxl_base *p;
779
780 list_for_each_entry(p, &mxllist, mxllist)
781 if (p->i2c == i2c && p->adr == adr)
782 return p;
783 return NULL;
784 }
785
786 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
787 {
788 if (state->base->can_clkout || !enable)
789 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
790
791 if (freq == 24000000)
792 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
793 else
794 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
795
796 write_register(state, HYDRA_CRYSTAL_CAP, cap);
797 }
798
799 static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
800 {
801 u32 ret_value = 0;
802
803 switch (num_of_bits) {
804 case 24:
805 ret_value = (((u32) buf[0]) << 16) |
806 (((u32) buf[1]) << 8) | buf[2];
807 break;
808 case 32:
809 ret_value = (((u32) buf[0]) << 24) |
810 (((u32) buf[1]) << 16) |
811 (((u32) buf[2]) << 8) | buf[3];
812 break;
813 default:
814 break;
815 }
816
817 return ret_value;
818 }
819
820 static int write_fw_segment(struct mxl *state,
821 u32 mem_addr, u32 total_size, u8 *data_ptr)
822 {
823 int status;
824 u32 data_count = 0;
825 u32 size = 0;
826 u32 orig_size = 0;
827 u8 *w_buf_ptr = NULL;
828 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
829 (MXL_HYDRA_I2C_HDR_SIZE +
830 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
831 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
832 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
833
834 do {
835 size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
836 (total_size - data_count) : block_size;
837
838 if (orig_size & 3)
839 size = (orig_size + 4) & ~3;
840 w_buf_ptr = &w_msg_buffer[0];
841 memset((void *) w_buf_ptr, 0, size);
842 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
843 convert_endian(1, size, w_buf_ptr);
844 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
845 if (status)
846 return status;
847 data_count += size;
848 mem_addr += size;
849 data_ptr += size;
850 } while (data_count < total_size);
851
852 return status;
853 }
854
855 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
856 u32 mbin_buffer_size)
857
858 {
859 int status;
860 u32 index = 0;
861 u32 seg_length = 0;
862 u32 seg_address = 0;
863 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr;
864 struct MBIN_SEGMENT_T *segment_ptr;
865 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
866
867 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
868 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
869 __func__, mbin_ptr->header.id);
870 return -EINVAL;
871 }
872 status = write_register(state, FW_DL_SIGN_ADDR, 0);
873 if (status)
874 return status;
875 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
876 for (index = 0; index < mbin_ptr->header.num_segments; index++) {
877 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
878 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
879 __func__, segment_ptr->header.id);
880 return -EINVAL;
881 }
882 seg_length = get_big_endian(24,
883 &(segment_ptr->header.len24[0]));
884 seg_address = get_big_endian(32,
885 &(segment_ptr->header.address[0]));
886
887 if (state->base->type == MXL_HYDRA_DEVICE_568) {
888 if ((((seg_address & 0x90760000) == 0x90760000) ||
889 ((seg_address & 0x90740000) == 0x90740000)) &&
890 (xcpu_fw_flag == MXL_FALSE)) {
891 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
892 msleep(200);
893 write_register(state, 0x90720000, 0);
894 usleep_range(10000, 11000);
895 xcpu_fw_flag = MXL_TRUE;
896 }
897 status = write_fw_segment(state, seg_address,
898 seg_length,
899 (u8 *) segment_ptr->data);
900 } else {
901 if (((seg_address & 0x90760000) != 0x90760000) &&
902 ((seg_address & 0x90740000) != 0x90740000))
903 status = write_fw_segment(state, seg_address,
904 seg_length, (u8 *) segment_ptr->data);
905 }
906 if (status)
907 return status;
908 segment_ptr = (struct MBIN_SEGMENT_T *)
909 &(segment_ptr->data[((seg_length + 3) / 4) * 4]);
910 }
911 return status;
912 }
913
914 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
915 {
916 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
917 u32 flen = (fh->image_size24[0] << 16) |
918 (fh->image_size24[1] << 8) | fh->image_size24[2];
919 u8 *fw, cs = 0;
920 u32 i;
921
922 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
923 dev_info(state->i2cdev, "Invalid FW Header\n");
924 return -1;
925 }
926 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
927 for (i = 0; i < flen; i += 1)
928 cs += fw[i];
929 if (cs != fh->image_checksum) {
930 dev_info(state->i2cdev, "Invalid FW Checksum\n");
931 return -1;
932 }
933 return 0;
934 }
935
936 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
937 {
938 int status;
939 u32 reg_data = 0;
940 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
941 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
942 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
943
944 if (check_fw(state, mbin, mbin_len))
945 return -1;
946
947 /* put CPU into reset */
948 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
949 if (status)
950 return status;
951 usleep_range(1000, 2000);
952
953 /* Reset TX FIFO's, BBAND, XBAR */
954 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
955 HYDRA_RESET_TRANSPORT_FIFO_DATA);
956 if (status)
957 return status;
958 status = write_register(state, HYDRA_RESET_BBAND_REG,
959 HYDRA_RESET_BBAND_DATA);
960 if (status)
961 return status;
962 status = write_register(state, HYDRA_RESET_XBAR_REG,
963 HYDRA_RESET_XBAR_DATA);
964 if (status)
965 return status;
966
967 /* Disable clock to Baseband, Wideband, SerDes,
968 * Alias ext & Transport modules
969 */
970 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
971 HYDRA_DISABLE_CLK_2);
972 if (status)
973 return status;
974 /* Clear Software & Host interrupt status - (Clear on read) */
975 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, &reg_data);
976 if (status)
977 return status;
978 status = do_firmware_download(state, mbin, mbin_len);
979 if (status)
980 return status;
981
982 if (state->base->type == MXL_HYDRA_DEVICE_568) {
983 usleep_range(10000, 11000);
984
985 /* bring XCPU out of reset */
986 status = write_register(state, 0x90720000, 1);
987 if (status)
988 return status;
989 msleep(500);
990
991 /* Enable XCPU UART message processing in MCPU */
992 status = write_register(state, 0x9076B510, 1);
993 if (status)
994 return status;
995 } else {
996 /* Bring CPU out of reset */
997 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
998 if (status)
999 return status;
1000 /* Wait until FW boots */
1001 msleep(150);
1002 }
1003
1004 /* Initialize XPT XBAR */
1005 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1006 if (status)
1007 return status;
1008
1009 if (!firmware_is_alive(state))
1010 return -1;
1011
1012 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1013
1014 /* sometimes register values are wrong shortly
1015 * after first heart beats
1016 */
1017 msleep(50);
1018
1019 dev_sku_cfg.sku_type = state->base->sku_type;
1020 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
1021 cmd_size, &dev_sku_cfg, cmd_buff);
1022 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1023 &cmd_buff[0]);
1024
1025 return status;
1026 }
1027
1028 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1029 {
1030 int status = 0;
1031 u32 pad_mux_value = 0;
1032
1033 if (enable_serial_ts == MXL_TRUE) {
1034 pad_mux_value = 0;
1035 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1036 (state->base->type == MXL_HYDRA_DEVICE_541S))
1037 pad_mux_value = 2;
1038 } else {
1039 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1040 (state->base->type == MXL_HYDRA_DEVICE_581S))
1041 pad_mux_value = 2;
1042 else
1043 pad_mux_value = 3;
1044 }
1045
1046 switch (state->base->type) {
1047 case MXL_HYDRA_DEVICE_561:
1048 case MXL_HYDRA_DEVICE_581:
1049 case MXL_HYDRA_DEVICE_541:
1050 case MXL_HYDRA_DEVICE_541S:
1051 case MXL_HYDRA_DEVICE_561S:
1052 case MXL_HYDRA_DEVICE_581S:
1053 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1054 pad_mux_value);
1055 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1056 pad_mux_value);
1057 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1058 pad_mux_value);
1059 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1060 pad_mux_value);
1061 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1062 pad_mux_value);
1063 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1064 pad_mux_value);
1065 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1066 pad_mux_value);
1067 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1068 pad_mux_value);
1069 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1070 pad_mux_value);
1071 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1072 pad_mux_value);
1073 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1074 pad_mux_value);
1075 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1076 pad_mux_value);
1077 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1078 pad_mux_value);
1079 break;
1080
1081 case MXL_HYDRA_DEVICE_544:
1082 case MXL_HYDRA_DEVICE_542:
1083 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1084 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1085 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1086 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1087 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1088 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1089 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1090 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1091 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1092 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1093 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1094 if (enable_serial_ts == MXL_ENABLE) {
1095 status |= update_by_mnemonic(state,
1096 0x90000170, 4, 3, 0);
1097 status |= update_by_mnemonic(state,
1098 0x90000170, 8, 3, 0);
1099 status |= update_by_mnemonic(state,
1100 0x90000170, 12, 3, 0);
1101 status |= update_by_mnemonic(state,
1102 0x90000170, 16, 3, 0);
1103 status |= update_by_mnemonic(state,
1104 0x90000170, 20, 3, 1);
1105 status |= update_by_mnemonic(state,
1106 0x90000170, 24, 3, 1);
1107 status |= update_by_mnemonic(state,
1108 0x90000170, 28, 3, 2);
1109 status |= update_by_mnemonic(state,
1110 0x90000174, 0, 3, 2);
1111 status |= update_by_mnemonic(state,
1112 0x90000174, 4, 3, 2);
1113 status |= update_by_mnemonic(state,
1114 0x90000174, 8, 3, 2);
1115 status |= update_by_mnemonic(state,
1116 0x90000174, 12, 3, 2);
1117 status |= update_by_mnemonic(state,
1118 0x90000174, 16, 3, 2);
1119 status |= update_by_mnemonic(state,
1120 0x90000174, 20, 3, 2);
1121 status |= update_by_mnemonic(state,
1122 0x90000174, 24, 3, 2);
1123 status |= update_by_mnemonic(state,
1124 0x90000174, 28, 3, 2);
1125 status |= update_by_mnemonic(state,
1126 0x90000178, 0, 3, 2);
1127 status |= update_by_mnemonic(state,
1128 0x90000178, 4, 3, 2);
1129 status |= update_by_mnemonic(state,
1130 0x90000178, 8, 3, 2);
1131 } else {
1132 status |= update_by_mnemonic(state,
1133 0x90000170, 4, 3, 3);
1134 status |= update_by_mnemonic(state,
1135 0x90000170, 8, 3, 3);
1136 status |= update_by_mnemonic(state,
1137 0x90000170, 12, 3, 3);
1138 status |= update_by_mnemonic(state,
1139 0x90000170, 16, 3, 3);
1140 status |= update_by_mnemonic(state,
1141 0x90000170, 20, 3, 3);
1142 status |= update_by_mnemonic(state,
1143 0x90000170, 24, 3, 3);
1144 status |= update_by_mnemonic(state,
1145 0x90000170, 28, 3, 3);
1146 status |= update_by_mnemonic(state,
1147 0x90000174, 0, 3, 3);
1148 status |= update_by_mnemonic(state,
1149 0x90000174, 4, 3, 3);
1150 status |= update_by_mnemonic(state,
1151 0x90000174, 8, 3, 3);
1152 status |= update_by_mnemonic(state,
1153 0x90000174, 12, 3, 3);
1154 status |= update_by_mnemonic(state,
1155 0x90000174, 16, 3, 3);
1156 status |= update_by_mnemonic(state,
1157 0x90000174, 20, 3, 1);
1158 status |= update_by_mnemonic(state,
1159 0x90000174, 24, 3, 1);
1160 status |= update_by_mnemonic(state,
1161 0x90000174, 28, 3, 1);
1162 status |= update_by_mnemonic(state,
1163 0x90000178, 0, 3, 1);
1164 status |= update_by_mnemonic(state,
1165 0x90000178, 4, 3, 1);
1166 status |= update_by_mnemonic(state,
1167 0x90000178, 8, 3, 1);
1168 }
1169 break;
1170
1171 case MXL_HYDRA_DEVICE_568:
1172 if (enable_serial_ts == MXL_FALSE) {
1173 status |= update_by_mnemonic(state,
1174 0x9000016C, 8, 3, 5);
1175 status |= update_by_mnemonic(state,
1176 0x9000016C, 12, 3, 5);
1177 status |= update_by_mnemonic(state,
1178 0x9000016C, 16, 3, 5);
1179 status |= update_by_mnemonic(state,
1180 0x9000016C, 20, 3, 5);
1181 status |= update_by_mnemonic(state,
1182 0x9000016C, 24, 3, 5);
1183 status |= update_by_mnemonic(state,
1184 0x9000016C, 28, 3, 5);
1185 status |= update_by_mnemonic(state,
1186 0x90000170, 0, 3, 5);
1187 status |= update_by_mnemonic(state,
1188 0x90000170, 4, 3, 5);
1189 status |= update_by_mnemonic(state,
1190 0x90000170, 8, 3, 5);
1191 status |= update_by_mnemonic(state,
1192 0x90000170, 12, 3, 5);
1193 status |= update_by_mnemonic(state,
1194 0x90000170, 16, 3, 5);
1195 status |= update_by_mnemonic(state,
1196 0x90000170, 20, 3, 5);
1197
1198 status |= update_by_mnemonic(state,
1199 0x90000170, 24, 3, pad_mux_value);
1200 status |= update_by_mnemonic(state,
1201 0x90000174, 0, 3, pad_mux_value);
1202 status |= update_by_mnemonic(state,
1203 0x90000174, 4, 3, pad_mux_value);
1204 status |= update_by_mnemonic(state,
1205 0x90000174, 8, 3, pad_mux_value);
1206 status |= update_by_mnemonic(state,
1207 0x90000174, 12, 3, pad_mux_value);
1208 status |= update_by_mnemonic(state,
1209 0x90000174, 16, 3, pad_mux_value);
1210 status |= update_by_mnemonic(state,
1211 0x90000174, 20, 3, pad_mux_value);
1212 status |= update_by_mnemonic(state,
1213 0x90000174, 24, 3, pad_mux_value);
1214 status |= update_by_mnemonic(state,
1215 0x90000174, 28, 3, pad_mux_value);
1216 status |= update_by_mnemonic(state,
1217 0x90000178, 0, 3, pad_mux_value);
1218 status |= update_by_mnemonic(state,
1219 0x90000178, 4, 3, pad_mux_value);
1220
1221 status |= update_by_mnemonic(state,
1222 0x90000178, 8, 3, 5);
1223 status |= update_by_mnemonic(state,
1224 0x90000178, 12, 3, 5);
1225 status |= update_by_mnemonic(state,
1226 0x90000178, 16, 3, 5);
1227 status |= update_by_mnemonic(state,
1228 0x90000178, 20, 3, 5);
1229 status |= update_by_mnemonic(state,
1230 0x90000178, 24, 3, 5);
1231 status |= update_by_mnemonic(state,
1232 0x90000178, 28, 3, 5);
1233 status |= update_by_mnemonic(state,
1234 0x9000017C, 0, 3, 5);
1235 status |= update_by_mnemonic(state,
1236 0x9000017C, 4, 3, 5);
1237 } else {
1238 status |= update_by_mnemonic(state,
1239 0x90000170, 4, 3, pad_mux_value);
1240 status |= update_by_mnemonic(state,
1241 0x90000170, 8, 3, pad_mux_value);
1242 status |= update_by_mnemonic(state,
1243 0x90000170, 12, 3, pad_mux_value);
1244 status |= update_by_mnemonic(state,
1245 0x90000170, 16, 3, pad_mux_value);
1246 status |= update_by_mnemonic(state,
1247 0x90000170, 20, 3, pad_mux_value);
1248 status |= update_by_mnemonic(state,
1249 0x90000170, 24, 3, pad_mux_value);
1250 status |= update_by_mnemonic(state,
1251 0x90000170, 28, 3, pad_mux_value);
1252 status |= update_by_mnemonic(state,
1253 0x90000174, 0, 3, pad_mux_value);
1254 status |= update_by_mnemonic(state,
1255 0x90000174, 4, 3, pad_mux_value);
1256 status |= update_by_mnemonic(state,
1257 0x90000174, 8, 3, pad_mux_value);
1258 status |= update_by_mnemonic(state,
1259 0x90000174, 12, 3, pad_mux_value);
1260 }
1261 break;
1262
1263
1264 case MXL_HYDRA_DEVICE_584:
1265 default:
1266 status |= update_by_mnemonic(state,
1267 0x90000170, 4, 3, pad_mux_value);
1268 status |= update_by_mnemonic(state,
1269 0x90000170, 8, 3, pad_mux_value);
1270 status |= update_by_mnemonic(state,
1271 0x90000170, 12, 3, pad_mux_value);
1272 status |= update_by_mnemonic(state,
1273 0x90000170, 16, 3, pad_mux_value);
1274 status |= update_by_mnemonic(state,
1275 0x90000170, 20, 3, pad_mux_value);
1276 status |= update_by_mnemonic(state,
1277 0x90000170, 24, 3, pad_mux_value);
1278 status |= update_by_mnemonic(state,
1279 0x90000170, 28, 3, pad_mux_value);
1280 status |= update_by_mnemonic(state,
1281 0x90000174, 0, 3, pad_mux_value);
1282 status |= update_by_mnemonic(state,
1283 0x90000174, 4, 3, pad_mux_value);
1284 status |= update_by_mnemonic(state,
1285 0x90000174, 8, 3, pad_mux_value);
1286 status |= update_by_mnemonic(state,
1287 0x90000174, 12, 3, pad_mux_value);
1288 break;
1289 }
1290 return status;
1291 }
1292
1293 static int set_drive_strength(struct mxl *state,
1294 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
1295 {
1296 int stat = 0;
1297 u32 val;
1298
1299 read_register(state, 0x90000194, &val);
1300 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1301 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1302
1303
1304 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1305 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1306 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1307 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1308 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1309 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1310 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1311 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1312 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1313 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1314 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1315 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1316 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1317 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1318 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1319 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1320 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1321
1322 return stat;
1323 }
1324
1325 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1326 {
1327 int stat = 0;
1328 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
1329 u8 cmd_size = sizeof(ctrl_tuner_cmd);
1330 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
1331 u32 val, count = 10;
1332
1333 ctrl_tuner_cmd.tuner_id = tuner;
1334 ctrl_tuner_cmd.enable = enable;
1335 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
1336 cmd_size, &ctrl_tuner_cmd, cmd_buff);
1337 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1338 &cmd_buff[0]);
1339 if (stat)
1340 return stat;
1341 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1342 while (--count && ((val >> tuner) & 1) != enable) {
1343 msleep(20);
1344 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1345 }
1346 if (!count)
1347 return -1;
1348 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1349 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1350 tuner, (val >> tuner) & 1);
1351
1352 return 0;
1353 }
1354
1355
1356 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1357 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
1358 {
1359 int status = 0;
1360 u32 nco_count_min = 0;
1361 u32 clk_type = 0;
1362
1363 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
1364 {0x90700010, 8, 1}, {0x90700010, 9, 1},
1365 {0x90700010, 10, 1}, {0x90700010, 11, 1},
1366 {0x90700010, 12, 1}, {0x90700010, 13, 1},
1367 {0x90700010, 14, 1}, {0x90700010, 15, 1} };
1368 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
1369 {0x90700010, 16, 1}, {0x90700010, 17, 1},
1370 {0x90700010, 18, 1}, {0x90700010, 19, 1},
1371 {0x90700010, 20, 1}, {0x90700010, 21, 1},
1372 {0x90700010, 22, 1}, {0x90700010, 23, 1} };
1373 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
1374 {0x90700014, 0, 1}, {0x90700014, 1, 1},
1375 {0x90700014, 2, 1}, {0x90700014, 3, 1},
1376 {0x90700014, 4, 1}, {0x90700014, 5, 1},
1377 {0x90700014, 6, 1}, {0x90700014, 7, 1} };
1378 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
1379 {0x90700018, 0, 3}, {0x90700018, 4, 3},
1380 {0x90700018, 8, 3}, {0x90700018, 12, 3},
1381 {0x90700018, 16, 3}, {0x90700018, 20, 3},
1382 {0x90700018, 24, 3}, {0x90700018, 28, 3} };
1383 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
1384 {0x9070000C, 16, 1}, {0x9070000C, 17, 1},
1385 {0x9070000C, 18, 1}, {0x9070000C, 19, 1},
1386 {0x9070000C, 20, 1}, {0x9070000C, 21, 1},
1387 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
1388 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
1389 {0x90700010, 0, 1}, {0x90700010, 1, 1},
1390 {0x90700010, 2, 1}, {0x90700010, 3, 1},
1391 {0x90700010, 4, 1}, {0x90700010, 5, 1},
1392 {0x90700010, 6, 1}, {0x90700010, 7, 1} };
1393 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
1394 {0x9070000C, 0, 1}, {0x9070000C, 1, 1},
1395 {0x9070000C, 2, 1}, {0x9070000C, 3, 1},
1396 {0x9070000C, 4, 1}, {0x9070000C, 5, 1},
1397 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
1398 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
1399 {0x9070000C, 24, 1}, {0x9070000C, 25, 1},
1400 {0x9070000C, 26, 1}, {0x9070000C, 27, 1},
1401 {0x9070000C, 28, 1}, {0x9070000C, 29, 1},
1402 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
1403 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
1404 {0x90700014, 8, 1}, {0x90700014, 9, 1},
1405 {0x90700014, 10, 1}, {0x90700014, 11, 1},
1406 {0x90700014, 12, 1}, {0x90700014, 13, 1},
1407 {0x90700014, 14, 1}, {0x90700014, 15, 1} };
1408 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
1409 {0x907001D4, 0, 1}, {0x907001D4, 1, 1},
1410 {0x907001D4, 2, 1}, {0x907001D4, 3, 1},
1411 {0x907001D4, 4, 1}, {0x907001D4, 5, 1},
1412 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
1413 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
1414 {0x90700044, 16, 80}, {0x90700044, 16, 81},
1415 {0x90700044, 16, 82}, {0x90700044, 16, 83},
1416 {0x90700044, 16, 84}, {0x90700044, 16, 85},
1417 {0x90700044, 16, 86}, {0x90700044, 16, 87} };
1418
1419 demod_id = state->base->ts_map[demod_id];
1420
1421 if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
1422 if (mpeg_out_param_ptr->mpeg_mode ==
1423 MXL_HYDRA_MPEG_MODE_PARALLEL) {
1424 } else {
1425 cfg_ts_pad_mux(state, MXL_TRUE);
1426 update_by_mnemonic(state,
1427 0x90700010, 27, 1, MXL_FALSE);
1428 }
1429 }
1430
1431 nco_count_min =
1432 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
1433
1434 if (state->base->chipversion >= 2) {
1435 status |= update_by_mnemonic(state,
1436 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
1437 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
1438 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
1439 nco_count_min); /* Data */
1440 } else
1441 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1442
1443 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
1444 clk_type = 1;
1445
1446 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
1447 status |= update_by_mnemonic(state,
1448 xpt_continuous_clock[demod_id].reg_addr,
1449 xpt_continuous_clock[demod_id].lsb_pos,
1450 xpt_continuous_clock[demod_id].num_of_bits,
1451 clk_type);
1452 } else
1453 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1454
1455 status |= update_by_mnemonic(state,
1456 xpt_sync_polarity[demod_id].reg_addr,
1457 xpt_sync_polarity[demod_id].lsb_pos,
1458 xpt_sync_polarity[demod_id].num_of_bits,
1459 mpeg_out_param_ptr->mpeg_sync_pol);
1460
1461 status |= update_by_mnemonic(state,
1462 xpt_valid_polarity[demod_id].reg_addr,
1463 xpt_valid_polarity[demod_id].lsb_pos,
1464 xpt_valid_polarity[demod_id].num_of_bits,
1465 mpeg_out_param_ptr->mpeg_valid_pol);
1466
1467 status |= update_by_mnemonic(state,
1468 xpt_clock_polarity[demod_id].reg_addr,
1469 xpt_clock_polarity[demod_id].lsb_pos,
1470 xpt_clock_polarity[demod_id].num_of_bits,
1471 mpeg_out_param_ptr->mpeg_clk_pol);
1472
1473 status |= update_by_mnemonic(state,
1474 xpt_sync_byte[demod_id].reg_addr,
1475 xpt_sync_byte[demod_id].lsb_pos,
1476 xpt_sync_byte[demod_id].num_of_bits,
1477 mpeg_out_param_ptr->mpeg_sync_pulse_width);
1478
1479 status |= update_by_mnemonic(state,
1480 xpt_ts_clock_phase[demod_id].reg_addr,
1481 xpt_ts_clock_phase[demod_id].lsb_pos,
1482 xpt_ts_clock_phase[demod_id].num_of_bits,
1483 mpeg_out_param_ptr->mpeg_clk_phase);
1484
1485 status |= update_by_mnemonic(state,
1486 xpt_lsb_first[demod_id].reg_addr,
1487 xpt_lsb_first[demod_id].lsb_pos,
1488 xpt_lsb_first[demod_id].num_of_bits,
1489 mpeg_out_param_ptr->lsb_or_msb_first);
1490
1491 switch (mpeg_out_param_ptr->mpeg_error_indication) {
1492 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
1493 status |= update_by_mnemonic(state,
1494 xpt_err_replace_sync[demod_id].reg_addr,
1495 xpt_err_replace_sync[demod_id].lsb_pos,
1496 xpt_err_replace_sync[demod_id].num_of_bits,
1497 MXL_TRUE);
1498 status |= update_by_mnemonic(state,
1499 xpt_err_replace_valid[demod_id].reg_addr,
1500 xpt_err_replace_valid[demod_id].lsb_pos,
1501 xpt_err_replace_valid[demod_id].num_of_bits,
1502 MXL_FALSE);
1503 break;
1504
1505 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
1506 status |= update_by_mnemonic(state,
1507 xpt_err_replace_sync[demod_id].reg_addr,
1508 xpt_err_replace_sync[demod_id].lsb_pos,
1509 xpt_err_replace_sync[demod_id].num_of_bits,
1510 MXL_FALSE);
1511
1512 status |= update_by_mnemonic(state,
1513 xpt_err_replace_valid[demod_id].reg_addr,
1514 xpt_err_replace_valid[demod_id].lsb_pos,
1515 xpt_err_replace_valid[demod_id].num_of_bits,
1516 MXL_TRUE);
1517 break;
1518
1519 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
1520 default:
1521 status |= update_by_mnemonic(state,
1522 xpt_err_replace_sync[demod_id].reg_addr,
1523 xpt_err_replace_sync[demod_id].lsb_pos,
1524 xpt_err_replace_sync[demod_id].num_of_bits,
1525 MXL_FALSE);
1526
1527 status |= update_by_mnemonic(state,
1528 xpt_err_replace_valid[demod_id].reg_addr,
1529 xpt_err_replace_valid[demod_id].lsb_pos,
1530 xpt_err_replace_valid[demod_id].num_of_bits,
1531 MXL_FALSE);
1532
1533 break;
1534
1535 }
1536
1537 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
1538 status |= update_by_mnemonic(state,
1539 xpt_enable_output[demod_id].reg_addr,
1540 xpt_enable_output[demod_id].lsb_pos,
1541 xpt_enable_output[demod_id].num_of_bits,
1542 mpeg_out_param_ptr->enable);
1543 }
1544 return status;
1545 }
1546
1547 static int config_mux(struct mxl *state)
1548 {
1549 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1550 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1551 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1552 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1553 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1554 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1555 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1556 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1557 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1558 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1559 return 0;
1560 }
1561
1562 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1563 {
1564 int stat = 0;
1565 u8 *buf;
1566
1567 if (cfg->fw)
1568 return firmware_download(state, cfg->fw, cfg->fw_len);
1569
1570 if (!cfg->fw_read)
1571 return -1;
1572
1573 buf = vmalloc(0x40000);
1574 if (!buf)
1575 return -ENOMEM;
1576
1577 cfg->fw_read(cfg->fw_priv, buf, 0x40000);
1578 stat = firmware_download(state, buf, 0x40000);
1579 vfree(buf);
1580
1581 return stat;
1582 }
1583
1584 static int validate_sku(struct mxl *state)
1585 {
1586 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
1587 int status;
1588 u32 type = state->base->type;
1589
1590 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1591 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1592 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1593 if (status)
1594 return -1;
1595
1596 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1597 pad_mux_bond, prcm_chip_id, prcm_so_cid);
1598
1599 if (prcm_chip_id != 0x560) {
1600 switch (pad_mux_bond) {
1601 case MXL_HYDRA_SKU_ID_581:
1602 if (type == MXL_HYDRA_DEVICE_581)
1603 return 0;
1604 if (type == MXL_HYDRA_DEVICE_581S) {
1605 state->base->type = MXL_HYDRA_DEVICE_581;
1606 return 0;
1607 }
1608 break;
1609 case MXL_HYDRA_SKU_ID_584:
1610 if (type == MXL_HYDRA_DEVICE_584)
1611 return 0;
1612 break;
1613 case MXL_HYDRA_SKU_ID_544:
1614 if (type == MXL_HYDRA_DEVICE_544)
1615 return 0;
1616 if (type == MXL_HYDRA_DEVICE_542)
1617 return 0;
1618 break;
1619 case MXL_HYDRA_SKU_ID_582:
1620 if (type == MXL_HYDRA_DEVICE_582)
1621 return 0;
1622 break;
1623 default:
1624 return -1;
1625 }
1626 } else {
1627
1628 }
1629 return -1;
1630 }
1631
1632 static int get_fwinfo(struct mxl *state)
1633 {
1634 int status;
1635 u32 val = 0;
1636
1637 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1638 if (status)
1639 return status;
1640 dev_info(state->i2cdev, "chipID=%08x\n", val);
1641
1642 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1643 if (status)
1644 return status;
1645 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1646
1647 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1648 if (status)
1649 return status;
1650 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1651
1652 state->base->fwversion = val;
1653 return status;
1654 }
1655
1656
1657 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
1658 MXL_HYDRA_DEMOD_ID_0,
1659 MXL_HYDRA_DEMOD_ID_1,
1660 MXL_HYDRA_DEMOD_ID_2,
1661 MXL_HYDRA_DEMOD_ID_3,
1662 MXL_HYDRA_DEMOD_ID_4,
1663 MXL_HYDRA_DEMOD_ID_5,
1664 MXL_HYDRA_DEMOD_ID_6,
1665 MXL_HYDRA_DEMOD_ID_7,
1666 };
1667
1668 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
1669 MXL_HYDRA_DEMOD_ID_2,
1670 MXL_HYDRA_DEMOD_ID_3,
1671 MXL_HYDRA_DEMOD_ID_4,
1672 MXL_HYDRA_DEMOD_ID_5,
1673 MXL_HYDRA_DEMOD_MAX,
1674 MXL_HYDRA_DEMOD_MAX,
1675 MXL_HYDRA_DEMOD_MAX,
1676 MXL_HYDRA_DEMOD_MAX,
1677 };
1678
1679 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1680 {
1681 u32 chipver;
1682 int fw, status, j;
1683 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
1684
1685 state->base->ts_map = ts_map1_to_1;
1686
1687 switch (state->base->type) {
1688 case MXL_HYDRA_DEVICE_581:
1689 case MXL_HYDRA_DEVICE_581S:
1690 state->base->can_clkout = 1;
1691 state->base->demod_num = 8;
1692 state->base->tuner_num = 1;
1693 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1694 break;
1695 case MXL_HYDRA_DEVICE_582:
1696 state->base->can_clkout = 1;
1697 state->base->demod_num = 8;
1698 state->base->tuner_num = 3;
1699 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1700 break;
1701 case MXL_HYDRA_DEVICE_585:
1702 state->base->can_clkout = 0;
1703 state->base->demod_num = 8;
1704 state->base->tuner_num = 4;
1705 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1706 break;
1707 case MXL_HYDRA_DEVICE_544:
1708 state->base->can_clkout = 0;
1709 state->base->demod_num = 4;
1710 state->base->tuner_num = 4;
1711 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1712 state->base->ts_map = ts_map54x;
1713 break;
1714 case MXL_HYDRA_DEVICE_541:
1715 case MXL_HYDRA_DEVICE_541S:
1716 state->base->can_clkout = 0;
1717 state->base->demod_num = 4;
1718 state->base->tuner_num = 1;
1719 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1720 state->base->ts_map = ts_map54x;
1721 break;
1722 case MXL_HYDRA_DEVICE_561:
1723 case MXL_HYDRA_DEVICE_561S:
1724 state->base->can_clkout = 0;
1725 state->base->demod_num = 6;
1726 state->base->tuner_num = 1;
1727 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1728 break;
1729 case MXL_HYDRA_DEVICE_568:
1730 state->base->can_clkout = 0;
1731 state->base->demod_num = 8;
1732 state->base->tuner_num = 1;
1733 state->base->chan_bond = 1;
1734 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1735 break;
1736 case MXL_HYDRA_DEVICE_542:
1737 state->base->can_clkout = 1;
1738 state->base->demod_num = 4;
1739 state->base->tuner_num = 3;
1740 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1741 state->base->ts_map = ts_map54x;
1742 break;
1743 case MXL_HYDRA_DEVICE_TEST:
1744 case MXL_HYDRA_DEVICE_584:
1745 default:
1746 state->base->can_clkout = 0;
1747 state->base->demod_num = 8;
1748 state->base->tuner_num = 4;
1749 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1750 break;
1751 }
1752
1753 status = validate_sku(state);
1754 if (status)
1755 return status;
1756
1757 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1758 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1759 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1760 if (status)
1761 state->base->chipversion = 0;
1762 else
1763 state->base->chipversion = (chipver == 2) ? 2 : 1;
1764 dev_info(state->i2cdev, "Hydra chip version %u\n",
1765 state->base->chipversion);
1766
1767 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1768
1769 fw = firmware_is_alive(state);
1770 if (!fw) {
1771 status = load_fw(state, cfg);
1772 if (status)
1773 return status;
1774 }
1775 get_fwinfo(state);
1776
1777 config_mux(state);
1778 mpeg_interface_cfg.enable = MXL_ENABLE;
1779 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
1780 /* supports only (0-104&139)MHz */
1781 if (cfg->ts_clk)
1782 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
1783 else
1784 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
1785 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
1786 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
1787 /* MXL_HYDRA_MPEG_CLK_GAPPED; */
1788 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
1789 mpeg_interface_cfg.mpeg_error_indication =
1790 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
1791 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
1792 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1793 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
1794 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1795
1796 for (j = 0; j < state->base->demod_num; j++) {
1797 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1798 &mpeg_interface_cfg);
1799 if (status)
1800 return status;
1801 }
1802 set_drive_strength(state, 1);
1803 return 0;
1804 }
1805
1806 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
1807 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
1808 int (**fn_set_input)(struct dvb_frontend *, int))
1809 {
1810 struct mxl *state;
1811 struct mxl_base *base;
1812
1813 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1814 if (!state)
1815 return NULL;
1816
1817 state->demod = demod;
1818 state->tuner = tuner;
1819 state->tuner_in_use = 0xffffffff;
1820 state->i2cdev = &i2c->dev;
1821
1822 base = match_base(i2c, cfg->adr);
1823 if (base) {
1824 base->count++;
1825 if (base->count > base->demod_num)
1826 goto fail;
1827 state->base = base;
1828 } else {
1829 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
1830 if (!base)
1831 goto fail;
1832 base->i2c = i2c;
1833 base->adr = cfg->adr;
1834 base->type = cfg->type;
1835 base->count = 1;
1836 mutex_init(&base->i2c_lock);
1837 mutex_init(&base->status_lock);
1838 mutex_init(&base->tune_lock);
1839 INIT_LIST_HEAD(&base->mxls);
1840
1841 state->base = base;
1842 if (probe(state, cfg) < 0) {
1843 kfree(base);
1844 goto fail;
1845 }
1846 list_add(&base->mxllist, &mxllist);
1847 }
1848 state->fe.ops = mxl_ops;
1849 state->xbar[0] = 4;
1850 state->xbar[1] = demod;
1851 state->xbar[2] = 8;
1852 state->fe.demodulator_priv = state;
1853 *fn_set_input = set_input;
1854
1855 list_add(&state->mxl, &base->mxls);
1856 return &state->fe;
1857
1858 fail:
1859 kfree(state);
1860 return NULL;
1861 }
1862 EXPORT_SYMBOL_GPL(mxl5xx_attach);
1863
1864 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
1865 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
1866 MODULE_LICENSE("GPL");
CRIS linux kernel tree