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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / media / dvb-frontends / stv0910.c
bloba2f7c0c1587f048725a72ddcdd8209c980f699f6
1 /*
2 * Driver for the ST STV0910 DVB-S/S2 demodulator.
3 *
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 only, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/firmware.h>
24 #include <linux/i2c.h>
25 #include <asm/div64.h>
26
27 #include <media/dvb_frontend.h>
28 #include "stv0910.h"
29 #include "stv0910_regs.h"
30
31 #define EXT_CLOCK 30000000
32 #define TUNING_DELAY 200
33 #define BER_SRC_S 0x20
34 #define BER_SRC_S2 0x20
35
36 static LIST_HEAD(stvlist);
37
38 enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
39
40 enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
41
42 enum dvbs2_mod_cod {
43 DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
44 DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
45 DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
46 DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
47 DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
48 DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
49 DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
50 DVBS2_32APSK_9_10
51 };
52
53 enum fe_stv0910_mod_cod {
54 FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
55 FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
56 FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
57 FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
58 FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
59 FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
60 FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
61 FE_32APSK_910
62 };
63
64 enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
65
66 static inline u32 muldiv32(u32 a, u32 b, u32 c)
67 {
68 u64 tmp64;
69
70 tmp64 = (u64)a * (u64)b;
71 do_div(tmp64, c);
72
73 return (u32)tmp64;
74 }
75
76 struct stv_base {
77 struct list_head stvlist;
78
79 u8 adr;
80 struct i2c_adapter *i2c;
81 struct mutex i2c_lock; /* shared I2C access protect */
82 struct mutex reg_lock; /* shared register write protect */
83 int count;
84
85 u32 extclk;
86 u32 mclk;
87 };
88
89 struct stv {
90 struct stv_base *base;
91 struct dvb_frontend fe;
92 int nr;
93 u16 regoff;
94 u8 i2crpt;
95 u8 tscfgh;
96 u8 tsgeneral;
97 u8 tsspeed;
98 u8 single;
99 unsigned long tune_time;
100
101 s32 search_range;
102 u32 started;
103 u32 demod_lock_time;
104 enum receive_mode receive_mode;
105 u32 demod_timeout;
106 u32 fec_timeout;
107 u32 first_time_lock;
108 u8 demod_bits;
109 u32 symbol_rate;
110
111 u8 last_viterbi_rate;
112 enum fe_code_rate puncture_rate;
113 enum fe_stv0910_mod_cod mod_cod;
114 enum dvbs2_fectype fectype;
115 u32 pilots;
116 enum fe_stv0910_roll_off feroll_off;
117
118 int is_standard_broadcast;
119 int is_vcm;
120
121 u32 cur_scrambling_code;
122
123 u32 last_bernumerator;
124 u32 last_berdenominator;
125 u8 berscale;
126
127 u8 vth[6];
128 };
129
130 struct sinit_table {
131 u16 address;
132 u8 data;
133 };
134
135 struct slookup {
136 s16 value;
137 u32 reg_value;
138 };
139
140 static int write_reg(struct stv *state, u16 reg, u8 val)
141 {
142 struct i2c_adapter *adap = state->base->i2c;
143 u8 data[3] = {reg >> 8, reg & 0xff, val};
144 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
145 .buf = data, .len = 3};
146
147 if (i2c_transfer(adap, &msg, 1) != 1) {
148 dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
149 state->base->adr, reg, val);
150 return -EIO;
151 }
152 return 0;
153 }
154
155 static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
156 u16 reg, u8 *val, int count)
157 {
158 u8 msg[2] = {reg >> 8, reg & 0xff};
159 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
160 .buf = msg, .len = 2},
161 {.addr = adr, .flags = I2C_M_RD,
162 .buf = val, .len = count } };
163
164 if (i2c_transfer(adapter, msgs, 2) != 2) {
165 dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
166 adr, reg);
167 return -EIO;
168 }
169 return 0;
170 }
171
172 static int read_reg(struct stv *state, u16 reg, u8 *val)
173 {
174 return i2c_read_regs16(state->base->i2c, state->base->adr,
175 reg, val, 1);
176 }
177
178 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
179 {
180 return i2c_read_regs16(state->base->i2c, state->base->adr,
181 reg, val, len);
182 }
183
184 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
185 {
186 int status;
187 u8 tmp;
188
189 mutex_lock(&state->base->reg_lock);
190 status = read_reg(state, reg, &tmp);
191 if (!status)
192 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
193 mutex_unlock(&state->base->reg_lock);
194 return status;
195 }
196
197 static int write_field(struct stv *state, u32 field, u8 val)
198 {
199 int status;
200 u8 shift, mask, old, new;
201
202 status = read_reg(state, field >> 16, &old);
203 if (status)
204 return status;
205 mask = field & 0xff;
206 shift = (field >> 12) & 0xf;
207 new = ((val << shift) & mask) | (old & ~mask);
208 if (new == old)
209 return 0;
210 return write_reg(state, field >> 16, new);
211 }
212
213 #define SET_FIELD(_reg, _val) \
214 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
215 FSTV0910_P1_##_reg, _val)
216
217 #define SET_REG(_reg, _val) \
218 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
219 RSTV0910_P1_##_reg, _val)
220
221 #define GET_REG(_reg, _val) \
222 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
223 RSTV0910_P1_##_reg, _val)
224
225 static const struct slookup s1_sn_lookup[] = {
226 { 0, 9242 }, /* C/N= 0dB */
227 { 5, 9105 }, /* C/N= 0.5dB */
228 { 10, 8950 }, /* C/N= 1.0dB */
229 { 15, 8780 }, /* C/N= 1.5dB */
230 { 20, 8566 }, /* C/N= 2.0dB */
231 { 25, 8366 }, /* C/N= 2.5dB */
232 { 30, 8146 }, /* C/N= 3.0dB */
233 { 35, 7908 }, /* C/N= 3.5dB */
234 { 40, 7666 }, /* C/N= 4.0dB */
235 { 45, 7405 }, /* C/N= 4.5dB */
236 { 50, 7136 }, /* C/N= 5.0dB */
237 { 55, 6861 }, /* C/N= 5.5dB */
238 { 60, 6576 }, /* C/N= 6.0dB */
239 { 65, 6330 }, /* C/N= 6.5dB */
240 { 70, 6048 }, /* C/N= 7.0dB */
241 { 75, 5768 }, /* C/N= 7.5dB */
242 { 80, 5492 }, /* C/N= 8.0dB */
243 { 85, 5224 }, /* C/N= 8.5dB */
244 { 90, 4959 }, /* C/N= 9.0dB */
245 { 95, 4709 }, /* C/N= 9.5dB */
246 { 100, 4467 }, /* C/N=10.0dB */
247 { 105, 4236 }, /* C/N=10.5dB */
248 { 110, 4013 }, /* C/N=11.0dB */
249 { 115, 3800 }, /* C/N=11.5dB */
250 { 120, 3598 }, /* C/N=12.0dB */
251 { 125, 3406 }, /* C/N=12.5dB */
252 { 130, 3225 }, /* C/N=13.0dB */
253 { 135, 3052 }, /* C/N=13.5dB */
254 { 140, 2889 }, /* C/N=14.0dB */
255 { 145, 2733 }, /* C/N=14.5dB */
256 { 150, 2587 }, /* C/N=15.0dB */
257 { 160, 2318 }, /* C/N=16.0dB */
258 { 170, 2077 }, /* C/N=17.0dB */
259 { 180, 1862 }, /* C/N=18.0dB */
260 { 190, 1670 }, /* C/N=19.0dB */
261 { 200, 1499 }, /* C/N=20.0dB */
262 { 210, 1347 }, /* C/N=21.0dB */
263 { 220, 1213 }, /* C/N=22.0dB */
264 { 230, 1095 }, /* C/N=23.0dB */
265 { 240, 992 }, /* C/N=24.0dB */
266 { 250, 900 }, /* C/N=25.0dB */
267 { 260, 826 }, /* C/N=26.0dB */
268 { 270, 758 }, /* C/N=27.0dB */
269 { 280, 702 }, /* C/N=28.0dB */
270 { 290, 653 }, /* C/N=29.0dB */
271 { 300, 613 }, /* C/N=30.0dB */
272 { 310, 579 }, /* C/N=31.0dB */
273 { 320, 550 }, /* C/N=32.0dB */
274 { 330, 526 }, /* C/N=33.0dB */
275 { 350, 490 }, /* C/N=33.0dB */
276 { 400, 445 }, /* C/N=40.0dB */
277 { 450, 430 }, /* C/N=45.0dB */
278 { 500, 426 }, /* C/N=50.0dB */
279 { 510, 425 } /* C/N=51.0dB */
280 };
281
282 static const struct slookup s2_sn_lookup[] = {
283 { -30, 13950 }, /* C/N=-2.5dB */
284 { -25, 13580 }, /* C/N=-2.5dB */
285 { -20, 13150 }, /* C/N=-2.0dB */
286 { -15, 12760 }, /* C/N=-1.5dB */
287 { -10, 12345 }, /* C/N=-1.0dB */
288 { -5, 11900 }, /* C/N=-0.5dB */
289 { 0, 11520 }, /* C/N= 0dB */
290 { 5, 11080 }, /* C/N= 0.5dB */
291 { 10, 10630 }, /* C/N= 1.0dB */
292 { 15, 10210 }, /* C/N= 1.5dB */
293 { 20, 9790 }, /* C/N= 2.0dB */
294 { 25, 9390 }, /* C/N= 2.5dB */
295 { 30, 8970 }, /* C/N= 3.0dB */
296 { 35, 8575 }, /* C/N= 3.5dB */
297 { 40, 8180 }, /* C/N= 4.0dB */
298 { 45, 7800 }, /* C/N= 4.5dB */
299 { 50, 7430 }, /* C/N= 5.0dB */
300 { 55, 7080 }, /* C/N= 5.5dB */
301 { 60, 6720 }, /* C/N= 6.0dB */
302 { 65, 6320 }, /* C/N= 6.5dB */
303 { 70, 6060 }, /* C/N= 7.0dB */
304 { 75, 5760 }, /* C/N= 7.5dB */
305 { 80, 5480 }, /* C/N= 8.0dB */
306 { 85, 5200 }, /* C/N= 8.5dB */
307 { 90, 4930 }, /* C/N= 9.0dB */
308 { 95, 4680 }, /* C/N= 9.5dB */
309 { 100, 4425 }, /* C/N=10.0dB */
310 { 105, 4210 }, /* C/N=10.5dB */
311 { 110, 3980 }, /* C/N=11.0dB */
312 { 115, 3765 }, /* C/N=11.5dB */
313 { 120, 3570 }, /* C/N=12.0dB */
314 { 125, 3315 }, /* C/N=12.5dB */
315 { 130, 3140 }, /* C/N=13.0dB */
316 { 135, 2980 }, /* C/N=13.5dB */
317 { 140, 2820 }, /* C/N=14.0dB */
318 { 145, 2670 }, /* C/N=14.5dB */
319 { 150, 2535 }, /* C/N=15.0dB */
320 { 160, 2270 }, /* C/N=16.0dB */
321 { 170, 2035 }, /* C/N=17.0dB */
322 { 180, 1825 }, /* C/N=18.0dB */
323 { 190, 1650 }, /* C/N=19.0dB */
324 { 200, 1485 }, /* C/N=20.0dB */
325 { 210, 1340 }, /* C/N=21.0dB */
326 { 220, 1212 }, /* C/N=22.0dB */
327 { 230, 1100 }, /* C/N=23.0dB */
328 { 240, 1000 }, /* C/N=24.0dB */
329 { 250, 910 }, /* C/N=25.0dB */
330 { 260, 836 }, /* C/N=26.0dB */
331 { 270, 772 }, /* C/N=27.0dB */
332 { 280, 718 }, /* C/N=28.0dB */
333 { 290, 671 }, /* C/N=29.0dB */
334 { 300, 635 }, /* C/N=30.0dB */
335 { 310, 602 }, /* C/N=31.0dB */
336 { 320, 575 }, /* C/N=32.0dB */
337 { 330, 550 }, /* C/N=33.0dB */
338 { 350, 517 }, /* C/N=35.0dB */
339 { 400, 480 }, /* C/N=40.0dB */
340 { 450, 466 }, /* C/N=45.0dB */
341 { 500, 464 }, /* C/N=50.0dB */
342 { 510, 463 }, /* C/N=51.0dB */
343 };
344
345 static const struct slookup padc_lookup[] = {
346 { 0, 118000 }, /* PADC= +0dBm */
347 { -100, 93600 }, /* PADC= -1dBm */
348 { -200, 74500 }, /* PADC= -2dBm */
349 { -300, 59100 }, /* PADC= -3dBm */
350 { -400, 47000 }, /* PADC= -4dBm */
351 { -500, 37300 }, /* PADC= -5dBm */
352 { -600, 29650 }, /* PADC= -6dBm */
353 { -700, 23520 }, /* PADC= -7dBm */
354 { -900, 14850 }, /* PADC= -9dBm */
355 { -1100, 9380 }, /* PADC=-11dBm */
356 { -1300, 5910 }, /* PADC=-13dBm */
357 { -1500, 3730 }, /* PADC=-15dBm */
358 { -1700, 2354 }, /* PADC=-17dBm */
359 { -1900, 1485 }, /* PADC=-19dBm */
360 { -2000, 1179 }, /* PADC=-20dBm */
361 { -2100, 1000 }, /* PADC=-21dBm */
362 };
363
364 /*********************************************************************
365 * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
366 *********************************************************************/
367 static const u8 s2car_loop[] = {
368 /*
369 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
370 * 20MPon 20MPoff 30MPon 30MPoff
371 */
372
373 /* FE_QPSK_14 */
374 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
375 /* FE_QPSK_13 */
376 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
377 /* FE_QPSK_25 */
378 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
379 /* FE_QPSK_12 */
380 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
381 /* FE_QPSK_35 */
382 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
383 /* FE_QPSK_23 */
384 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
385 /* FE_QPSK_34 */
386 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
387 /* FE_QPSK_45 */
388 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
389 /* FE_QPSK_56 */
390 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
391 /* FE_QPSK_89 */
392 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
393 /* FE_QPSK_910 */
394 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
395 /* FE_8PSK_35 */
396 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
397 /* FE_8PSK_23 */
398 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
399 /* FE_8PSK_34 */
400 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
401 /* FE_8PSK_56 */
402 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
403 /* FE_8PSK_89 */
404 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
405 /* FE_8PSK_910 */
406 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
407
408 /**********************************************************************
409 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
410 **********************************************************************/
411
412 /*
413 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
414 * 20MPoff 30MPon 30MPoff
415 */
416
417 /* FE_16APSK_23 */
418 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
419 /* FE_16APSK_34 */
420 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
421 /* FE_16APSK_45 */
422 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
423 /* FE_16APSK_56 */
424 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
425 /* FE_16APSK_89 */
426 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
427 /* FE_16APSK_910 */
428 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
429 /* FE_32APSK_34 */
430 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
431 /* FE_32APSK_45 */
432 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
433 /* FE_32APSK_56 */
434 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
435 /* FE_32APSK_89 */
436 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
437 /* FE_32APSK_910 */
438 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
439 };
440
441 static u8 get_optim_cloop(struct stv *state,
442 enum fe_stv0910_mod_cod mod_cod, u32 pilots)
443 {
444 int i = 0;
445
446 if (mod_cod >= FE_32APSK_910)
447 i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
448 else if (mod_cod >= FE_QPSK_14)
449 i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
450
451 if (state->symbol_rate <= 3000000)
452 i += 0;
453 else if (state->symbol_rate <= 7000000)
454 i += 2;
455 else if (state->symbol_rate <= 15000000)
456 i += 4;
457 else if (state->symbol_rate <= 25000000)
458 i += 6;
459 else
460 i += 8;
461
462 if (!pilots)
463 i += 1;
464
465 return s2car_loop[i];
466 }
467
468 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
469 {
470 int status = 0;
471 u8 symb_freq0;
472 u8 symb_freq1;
473 u8 symb_freq2;
474 u8 symb_freq3;
475 u8 tim_offs0;
476 u8 tim_offs1;
477 u8 tim_offs2;
478 u32 symbol_rate;
479 s32 timing_offset;
480
481 *p_symbol_rate = 0;
482 if (!state->started)
483 return status;
484
485 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
486 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
487 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
488 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
489 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
490 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
491 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
492
493 symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
494 ((u32)symb_freq1 << 8) | (u32)symb_freq0;
495 timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
496 (u32)tim_offs0;
497
498 if ((timing_offset & (1 << 23)) != 0)
499 timing_offset |= 0xFF000000; /* Sign extent */
500
501 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
502 timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
503
504 *p_symbol_rate = symbol_rate + timing_offset;
505
506 return 0;
507 }
508
509 static int get_signal_parameters(struct stv *state)
510 {
511 u8 tmp;
512
513 if (!state->started)
514 return -EINVAL;
515
516 if (state->receive_mode == RCVMODE_DVBS2) {
517 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
518 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
519 state->pilots = (tmp & 0x01) != 0;
520 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
521
522 } else if (state->receive_mode == RCVMODE_DVBS) {
523 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
524 state->puncture_rate = FEC_NONE;
525 switch (tmp & 0x1F) {
526 case 0x0d:
527 state->puncture_rate = FEC_1_2;
528 break;
529 case 0x12:
530 state->puncture_rate = FEC_2_3;
531 break;
532 case 0x15:
533 state->puncture_rate = FEC_3_4;
534 break;
535 case 0x18:
536 state->puncture_rate = FEC_5_6;
537 break;
538 case 0x1a:
539 state->puncture_rate = FEC_7_8;
540 break;
541 }
542 state->is_vcm = 0;
543 state->is_standard_broadcast = 1;
544 state->feroll_off = FE_SAT_35;
545 }
546 return 0;
547 }
548
549 static int tracking_optimization(struct stv *state)
550 {
551 u8 tmp;
552
553 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
554 tmp &= ~0xC0;
555
556 switch (state->receive_mode) {
557 case RCVMODE_DVBS:
558 tmp |= 0x40;
559 break;
560 case RCVMODE_DVBS2:
561 tmp |= 0x80;
562 break;
563 default:
564 tmp |= 0xC0;
565 break;
566 }
567 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
568
569 if (state->receive_mode == RCVMODE_DVBS2) {
570 /* Disable Reed-Solomon */
571 write_shared_reg(state,
572 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
573 0x03);
574
575 if (state->fectype == DVBS2_64K) {
576 u8 aclc = get_optim_cloop(state, state->mod_cod,
577 state->pilots);
578
579 if (state->mod_cod <= FE_QPSK_910) {
580 write_reg(state, RSTV0910_P2_ACLC2S2Q +
581 state->regoff, aclc);
582 } else if (state->mod_cod <= FE_8PSK_910) {
583 write_reg(state, RSTV0910_P2_ACLC2S2Q +
584 state->regoff, 0x2a);
585 write_reg(state, RSTV0910_P2_ACLC2S28 +
586 state->regoff, aclc);
587 } else if (state->mod_cod <= FE_16APSK_910) {
588 write_reg(state, RSTV0910_P2_ACLC2S2Q +
589 state->regoff, 0x2a);
590 write_reg(state, RSTV0910_P2_ACLC2S216A +
591 state->regoff, aclc);
592 } else if (state->mod_cod <= FE_32APSK_910) {
593 write_reg(state, RSTV0910_P2_ACLC2S2Q +
594 state->regoff, 0x2a);
595 write_reg(state, RSTV0910_P2_ACLC2S232A +
596 state->regoff, aclc);
597 }
598 }
599 }
600 return 0;
601 }
602
603 static s32 table_lookup(const struct slookup *table,
604 int table_size, u32 reg_value)
605 {
606 s32 value;
607 int imin = 0;
608 int imax = table_size - 1;
609 int i;
610 s32 reg_diff;
611
612 /* Assumes Table[0].RegValue > Table[imax].RegValue */
613 if (reg_value >= table[0].reg_value) {
614 value = table[0].value;
615 } else if (reg_value <= table[imax].reg_value) {
616 value = table[imax].value;
617 } else {
618 while ((imax - imin) > 1) {
619 i = (imax + imin) / 2;
620 if ((table[imin].reg_value >= reg_value) &&
621 (reg_value >= table[i].reg_value))
622 imax = i;
623 else
624 imin = i;
625 }
626
627 reg_diff = table[imax].reg_value - table[imin].reg_value;
628 value = table[imin].value;
629 if (reg_diff != 0)
630 value += ((s32)(reg_value - table[imin].reg_value) *
631 (s32)(table[imax].value
632 - table[imin].value))
633 / (reg_diff);
634 }
635
636 return value;
637 }
638
639 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
640 {
641 u8 data0;
642 u8 data1;
643 u16 data;
644 int n_lookup;
645 const struct slookup *lookup;
646
647 *signal_to_noise = 0;
648
649 if (!state->started)
650 return -EINVAL;
651
652 if (state->receive_mode == RCVMODE_DVBS2) {
653 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
654 &data1);
655 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
656 &data0);
657 n_lookup = ARRAY_SIZE(s2_sn_lookup);
658 lookup = s2_sn_lookup;
659 } else {
660 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
661 &data1);
662 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
663 &data0);
664 n_lookup = ARRAY_SIZE(s1_sn_lookup);
665 lookup = s1_sn_lookup;
666 }
667 data = (((u16)data1) << 8) | (u16)data0;
668 *signal_to_noise = table_lookup(lookup, n_lookup, data);
669 return 0;
670 }
671
672 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
673 u32 *berdenominator)
674 {
675 u8 regs[3];
676
677 int status = read_regs(state,
678 RSTV0910_P2_ERRCNT12 + state->regoff,
679 regs, 3);
680
681 if (status)
682 return -EINVAL;
683
684 if ((regs[0] & 0x80) == 0) {
685 state->last_berdenominator = 1 << ((state->berscale * 2) +
686 10 + 3);
687 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
688 ((u32)regs[1] << 8) | regs[2];
689 if (state->last_bernumerator < 256 && state->berscale < 6) {
690 state->berscale += 1;
691 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
692 state->regoff,
693 0x20 | state->berscale);
694 } else if (state->last_bernumerator > 1024 &&
695 state->berscale > 2) {
696 state->berscale -= 1;
697 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
698 state->regoff, 0x20 |
699 state->berscale);
700 }
701 }
702 *bernumerator = state->last_bernumerator;
703 *berdenominator = state->last_berdenominator;
704 return 0;
705 }
706
707 static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
708 {
709 static const u32 nbch[][2] = {
710 { 0, 0}, /* DUMMY_PLF */
711 {16200, 3240}, /* QPSK_1_4, */
712 {21600, 5400}, /* QPSK_1_3, */
713 {25920, 6480}, /* QPSK_2_5, */
714 {32400, 7200}, /* QPSK_1_2, */
715 {38880, 9720}, /* QPSK_3_5, */
716 {43200, 10800}, /* QPSK_2_3, */
717 {48600, 11880}, /* QPSK_3_4, */
718 {51840, 12600}, /* QPSK_4_5, */
719 {54000, 13320}, /* QPSK_5_6, */
720 {57600, 14400}, /* QPSK_8_9, */
721 {58320, 16000}, /* QPSK_9_10, */
722 {43200, 9720}, /* 8PSK_3_5, */
723 {48600, 10800}, /* 8PSK_2_3, */
724 {51840, 11880}, /* 8PSK_3_4, */
725 {54000, 13320}, /* 8PSK_5_6, */
726 {57600, 14400}, /* 8PSK_8_9, */
727 {58320, 16000}, /* 8PSK_9_10, */
728 {43200, 10800}, /* 16APSK_2_3, */
729 {48600, 11880}, /* 16APSK_3_4, */
730 {51840, 12600}, /* 16APSK_4_5, */
731 {54000, 13320}, /* 16APSK_5_6, */
732 {57600, 14400}, /* 16APSK_8_9, */
733 {58320, 16000}, /* 16APSK_9_10 */
734 {48600, 11880}, /* 32APSK_3_4, */
735 {51840, 12600}, /* 32APSK_4_5, */
736 {54000, 13320}, /* 32APSK_5_6, */
737 {57600, 14400}, /* 32APSK_8_9, */
738 {58320, 16000}, /* 32APSK_9_10 */
739 };
740
741 if (mod_cod >= DVBS2_QPSK_1_4 &&
742 mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
743 return nbch[mod_cod][fectype];
744 return 64800;
745 }
746
747 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
748 u32 *berdenominator)
749 {
750 u8 regs[3];
751
752 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
753 regs, 3);
754
755 if (status)
756 return -EINVAL;
757
758 if ((regs[0] & 0x80) == 0) {
759 state->last_berdenominator =
760 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
761 state->fectype) <<
762 (state->berscale * 2);
763 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
764 ((u32)regs[1] << 8) | regs[2];
765 if (state->last_bernumerator < 256 && state->berscale < 6) {
766 state->berscale += 1;
767 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
768 0x20 | state->berscale);
769 } else if (state->last_bernumerator > 1024 &&
770 state->berscale > 2) {
771 state->berscale -= 1;
772 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
773 0x20 | state->berscale);
774 }
775 }
776 *bernumerator = state->last_bernumerator;
777 *berdenominator = state->last_berdenominator;
778 return status;
779 }
780
781 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
782 u32 *berdenominator)
783 {
784 *bernumerator = 0;
785 *berdenominator = 1;
786
787 switch (state->receive_mode) {
788 case RCVMODE_DVBS:
789 return get_bit_error_rate_s(state,
790 bernumerator, berdenominator);
791 case RCVMODE_DVBS2:
792 return get_bit_error_rate_s2(state,
793 bernumerator, berdenominator);
794 default:
795 break;
796 }
797 return 0;
798 }
799
800 static int set_mclock(struct stv *state, u32 master_clock)
801 {
802 u32 idf = 1;
803 u32 odf = 4;
804 u32 quartz = state->base->extclk / 1000000;
805 u32 fphi = master_clock / 1000000;
806 u32 ndiv = (fphi * odf * idf) / quartz;
807 u32 cp = 7;
808 u32 fvco;
809
810 if (ndiv >= 7 && ndiv <= 71)
811 cp = 7;
812 else if (ndiv >= 72 && ndiv <= 79)
813 cp = 8;
814 else if (ndiv >= 80 && ndiv <= 87)
815 cp = 9;
816 else if (ndiv >= 88 && ndiv <= 95)
817 cp = 10;
818 else if (ndiv >= 96 && ndiv <= 103)
819 cp = 11;
820 else if (ndiv >= 104 && ndiv <= 111)
821 cp = 12;
822 else if (ndiv >= 112 && ndiv <= 119)
823 cp = 13;
824 else if (ndiv >= 120 && ndiv <= 127)
825 cp = 14;
826 else if (ndiv >= 128 && ndiv <= 135)
827 cp = 15;
828 else if (ndiv >= 136 && ndiv <= 143)
829 cp = 16;
830 else if (ndiv >= 144 && ndiv <= 151)
831 cp = 17;
832 else if (ndiv >= 152 && ndiv <= 159)
833 cp = 18;
834 else if (ndiv >= 160 && ndiv <= 167)
835 cp = 19;
836 else if (ndiv >= 168 && ndiv <= 175)
837 cp = 20;
838 else if (ndiv >= 176 && ndiv <= 183)
839 cp = 21;
840 else if (ndiv >= 184 && ndiv <= 191)
841 cp = 22;
842 else if (ndiv >= 192 && ndiv <= 199)
843 cp = 23;
844 else if (ndiv >= 200 && ndiv <= 207)
845 cp = 24;
846 else if (ndiv >= 208 && ndiv <= 215)
847 cp = 25;
848 else if (ndiv >= 216 && ndiv <= 223)
849 cp = 26;
850 else if (ndiv >= 224 && ndiv <= 225)
851 cp = 27;
852
853 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
854 write_reg(state, RSTV0910_NCOARSE2, odf);
855 write_reg(state, RSTV0910_NCOARSE1, ndiv);
856
857 fvco = (quartz * 2 * ndiv) / idf;
858 state->base->mclk = fvco / (2 * odf) * 1000000;
859
860 return 0;
861 }
862
863 static int stop(struct stv *state)
864 {
865 if (state->started) {
866 u8 tmp;
867
868 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
869 state->tscfgh | 0x01);
870 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
871 tmp &= ~0x01; /* release reset DVBS2 packet delin */
872 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
873 /* Blind optim*/
874 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
875 /* Stop the demod */
876 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
877 state->started = 0;
878 }
879 state->receive_mode = RCVMODE_NONE;
880 return 0;
881 }
882
883 static void set_pls(struct stv *state, u32 pls_code)
884 {
885 if (pls_code == state->cur_scrambling_code)
886 return;
887
888 /* PLROOT2 bit 2 = gold code */
889 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
890 pls_code & 0xff);
891 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
892 (pls_code >> 8) & 0xff);
893 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
894 0x04 | ((pls_code >> 16) & 0x03));
895 state->cur_scrambling_code = pls_code;
896 }
897
898 static void set_isi(struct stv *state, u32 isi)
899 {
900 if (isi == NO_STREAM_ID_FILTER)
901 return;
902 if (isi == 0x80000000) {
903 SET_FIELD(FORCE_CONTINUOUS, 1);
904 SET_FIELD(TSOUT_NOSYNC, 1);
905 } else {
906 SET_FIELD(FILTER_EN, 1);
907 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
908 isi & 0xff);
909 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
910 }
911 SET_FIELD(ALGOSWRST, 1);
912 SET_FIELD(ALGOSWRST, 0);
913 }
914
915 static void set_stream_modes(struct stv *state,
916 struct dtv_frontend_properties *p)
917 {
918 set_isi(state, p->stream_id);
919 set_pls(state, p->scrambling_sequence_index);
920 }
921
922 static int init_search_param(struct stv *state,
923 struct dtv_frontend_properties *p)
924 {
925 SET_FIELD(FORCE_CONTINUOUS, 0);
926 SET_FIELD(FRAME_MODE, 0);
927 SET_FIELD(FILTER_EN, 0);
928 SET_FIELD(TSOUT_NOSYNC, 0);
929 SET_FIELD(TSFIFO_EMBINDVB, 0);
930 SET_FIELD(TSDEL_SYNCBYTE, 0);
931 SET_REG(UPLCCST0, 0xe0);
932 SET_FIELD(TSINS_TOKEN, 0);
933 SET_FIELD(HYSTERESIS_THRESHOLD, 0);
934 SET_FIELD(ISIOBS_MODE, 1);
935
936 set_stream_modes(state, p);
937 return 0;
938 }
939
940 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
941 {
942 u8 val;
943
944 switch (rate) {
945 case FEC_1_2:
946 val = 0x01;
947 break;
948 case FEC_2_3:
949 val = 0x02;
950 break;
951 case FEC_3_4:
952 val = 0x04;
953 break;
954 case FEC_5_6:
955 val = 0x08;
956 break;
957 case FEC_7_8:
958 val = 0x20;
959 break;
960 case FEC_NONE:
961 default:
962 val = 0x2f;
963 break;
964 }
965
966 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
967 }
968
969 static int set_vth_default(struct stv *state)
970 {
971 state->vth[0] = 0xd7;
972 state->vth[1] = 0x85;
973 state->vth[2] = 0x58;
974 state->vth[3] = 0x3a;
975 state->vth[4] = 0x34;
976 state->vth[5] = 0x28;
977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
983 return 0;
984 }
985
986 static int set_vth(struct stv *state)
987 {
988 static const struct slookup vthlookup_table[] = {
989 {250, 8780}, /* C/N= 1.5dB */
990 {100, 7405}, /* C/N= 4.5dB */
991 {40, 6330}, /* C/N= 6.5dB */
992 {12, 5224}, /* C/N= 8.5dB */
993 {5, 4236} /* C/N=10.5dB */
994 };
995
996 int i;
997 u8 tmp[2];
998 int status = read_regs(state,
999 RSTV0910_P2_NNOSDATAT1 + state->regoff,
1000 tmp, 2);
1001 u16 reg_value = (tmp[0] << 8) | tmp[1];
1002 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
1003 reg_value);
1004
1005 for (i = 0; i < 6; i += 1)
1006 if (state->vth[i] > vth)
1007 state->vth[i] = vth;
1008
1009 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1015 return status;
1016 }
1017
1018 static int start(struct stv *state, struct dtv_frontend_properties *p)
1019 {
1020 s32 freq;
1021 u8 reg_dmdcfgmd;
1022 u16 symb;
1023
1024 if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
1025 return -EINVAL;
1026
1027 state->receive_mode = RCVMODE_NONE;
1028 state->demod_lock_time = 0;
1029
1030 /* Demod Stop */
1031 if (state->started)
1032 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1033
1034 init_search_param(state, p);
1035
1036 if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
1037 state->demod_timeout = 3000;
1038 state->fec_timeout = 2000;
1039 } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
1040 state->demod_timeout = 2500;
1041 state->fec_timeout = 1300;
1042 } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
1043 state->demod_timeout = 1000;
1044 state->fec_timeout = 650;
1045 } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
1046 state->demod_timeout = 700;
1047 state->fec_timeout = 350;
1048 } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
1049 state->demod_timeout = 400;
1050 state->fec_timeout = 200;
1051 } else { /* SR >=20Msps */
1052 state->demod_timeout = 300;
1053 state->fec_timeout = 200;
1054 }
1055
1056 /* Set the Init Symbol rate */
1057 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1058 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1059 ((symb >> 8) & 0x7F));
1060 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1061
1062 state->demod_bits |= 0x80;
1063 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1064
1065 /* FE_STV0910_SetSearchStandard */
1066 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &reg_dmdcfgmd);
1067 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1068 reg_dmdcfgmd |= 0xC0);
1069
1070 write_shared_reg(state,
1071 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1072
1073 /* Disable DSS */
1074 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1075 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1076
1077 enable_puncture_rate(state, FEC_NONE);
1078
1079 /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
1080 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1081 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1082 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1083 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1084 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1085 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1086
1087 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1088 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1089 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1090 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1091
1092 /*
1093 * Reset CAR3, bug DVBS2->DVBS1 lock
1094 * Note: The bit is only pulsed -> no lock on shared register needed
1095 */
1096 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1097 write_reg(state, RSTV0910_TSTRES0, 0);
1098
1099 set_vth_default(state);
1100 /* Reset demod */
1101 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1102
1103 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1104
1105 if (p->symbol_rate <= 5000000)
1106 freq = (state->search_range / 2000) + 80;
1107 else
1108 freq = (state->search_range / 2000) + 1600;
1109 freq = (freq << 16) / (state->base->mclk / 1000);
1110
1111 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1112 (freq >> 8) & 0xff);
1113 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1114 /* CFR Low Setting */
1115 freq = -freq;
1116 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1117 (freq >> 8) & 0xff);
1118 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1119
1120 /* init the demod frequency offset to 0 */
1121 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1122 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1123
1124 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1125 /* Trigger acq */
1126 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1127
1128 state->demod_lock_time += TUNING_DELAY;
1129 state->started = 1;
1130
1131 return 0;
1132 }
1133
1134 static int init_diseqc(struct stv *state)
1135 {
1136 u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1137 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1138
1139 /* Disable receiver */
1140 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1141 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1143 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1144 return 0;
1145 }
1146
1147 static int probe(struct stv *state)
1148 {
1149 u8 id;
1150
1151 state->receive_mode = RCVMODE_NONE;
1152 state->started = 0;
1153
1154 if (read_reg(state, RSTV0910_MID, &id) < 0)
1155 return -ENODEV;
1156
1157 if (id != 0x51)
1158 return -EINVAL;
1159
1160 /* Configure the I2C repeater to off */
1161 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1162 /* Configure the I2C repeater to off */
1163 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1164 /* Set the I2C to oversampling ratio */
1165 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1166
1167 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1168 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1169 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1170 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1171 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
1172
1173 if (state->single)
1174 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1175 else
1176 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1177
1178 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1179 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1180
1181 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1182 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1183 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1184 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1185
1186 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1187 write_reg(state, RSTV0910_TSTRES0, 0x00);
1188
1189 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1190 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1191
1192 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1193 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1194
1195 set_mclock(state, 135000000);
1196
1197 /* TS output */
1198 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1200 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1201 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1202
1203 /* Speed = 67.5 MHz */
1204 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1205
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1208 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1209 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1210
1211 /* Speed = 67.5 MHz */
1212 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1213
1214 /* Reset stream merger */
1215 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1216 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1217 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1218 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1219
1220 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1221 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1222
1223 init_diseqc(state);
1224 return 0;
1225 }
1226
1227 static int gate_ctrl(struct dvb_frontend *fe, int enable)
1228 {
1229 struct stv *state = fe->demodulator_priv;
1230 u8 i2crpt = state->i2crpt & ~0x86;
1231
1232 /*
1233 * mutex_lock note: Concurrent I2C gate bus accesses must be
1234 * prevented (STV0910 = dual demod on a single IC with a single I2C
1235 * gate/bus, and two tuners attached), similar to most (if not all)
1236 * other I2C host interfaces/busses.
1237 *
1238 * enable=1 (open I2C gate) will grab the lock
1239 * enable=0 (close I2C gate) releases the lock
1240 */
1241
1242 if (enable) {
1243 mutex_lock(&state->base->i2c_lock);
1244 i2crpt |= 0x80;
1245 } else {
1246 i2crpt |= 0x02;
1247 }
1248
1249 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1250 RSTV0910_P1_I2CRPT, i2crpt) < 0) {
1251 /* don't hold the I2C bus lock on failure */
1252 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1253 mutex_unlock(&state->base->i2c_lock);
1254 dev_err(&state->base->i2c->dev,
1255 "%s() write_reg failure (enable=%d)\n",
1256 __func__, enable);
1257 return -EIO;
1258 }
1259
1260 state->i2crpt = i2crpt;
1261
1262 if (!enable)
1263 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1264 mutex_unlock(&state->base->i2c_lock);
1265 return 0;
1266 }
1267
1268 static void release(struct dvb_frontend *fe)
1269 {
1270 struct stv *state = fe->demodulator_priv;
1271
1272 state->base->count--;
1273 if (state->base->count == 0) {
1274 list_del(&state->base->stvlist);
1275 kfree(state->base);
1276 }
1277 kfree(state);
1278 }
1279
1280 static int set_parameters(struct dvb_frontend *fe)
1281 {
1282 int stat = 0;
1283 struct stv *state = fe->demodulator_priv;
1284 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1285
1286 stop(state);
1287 if (fe->ops.tuner_ops.set_params)
1288 fe->ops.tuner_ops.set_params(fe);
1289 state->symbol_rate = p->symbol_rate;
1290 stat = start(state, p);
1291 return stat;
1292 }
1293
1294 static int manage_matype_info(struct stv *state)
1295 {
1296 if (!state->started)
1297 return -EINVAL;
1298 if (state->receive_mode == RCVMODE_DVBS2) {
1299 u8 bbheader[2];
1300
1301 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1302 bbheader, 2);
1303 state->feroll_off =
1304 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
1305 state->is_vcm = (bbheader[0] & 0x10) == 0;
1306 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1307 } else if (state->receive_mode == RCVMODE_DVBS) {
1308 state->is_vcm = 0;
1309 state->is_standard_broadcast = 1;
1310 state->feroll_off = FE_SAT_35;
1311 }
1312 return 0;
1313 }
1314
1315 static int read_snr(struct dvb_frontend *fe)
1316 {
1317 struct stv *state = fe->demodulator_priv;
1318 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1319 s32 snrval;
1320
1321 if (!get_signal_to_noise(state, &snrval)) {
1322 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1323 p->cnr.stat[0].uvalue = 100 * snrval; /* fix scale */
1324 } else {
1325 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static int read_ber(struct dvb_frontend *fe)
1332 {
1333 struct stv *state = fe->demodulator_priv;
1334 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1335 u32 n, d;
1336
1337 get_bit_error_rate(state, &n, &d);
1338
1339 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1340 p->pre_bit_error.stat[0].uvalue = n;
1341 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1342 p->pre_bit_count.stat[0].uvalue = d;
1343
1344 return 0;
1345 }
1346
1347 static void read_signal_strength(struct dvb_frontend *fe)
1348 {
1349 struct stv *state = fe->demodulator_priv;
1350 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1351 u8 reg[2];
1352 u16 agc;
1353 s32 padc, power = 0;
1354 int i;
1355
1356 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1357
1358 agc = (((u32)reg[0]) << 8) | reg[1];
1359
1360 for (i = 0; i < 5; i += 1) {
1361 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1362 power += (u32)reg[0] * (u32)reg[0]
1363 + (u32)reg[1] * (u32)reg[1];
1364 usleep_range(3000, 4000);
1365 }
1366 power /= 5;
1367
1368 padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
1369
1370 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1371 p->strength.stat[0].svalue = (padc - agc);
1372 }
1373
1374 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1375 {
1376 struct stv *state = fe->demodulator_priv;
1377 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1378 u8 dmd_state = 0;
1379 u8 dstatus = 0;
1380 enum receive_mode cur_receive_mode = RCVMODE_NONE;
1381 u32 feclock = 0;
1382
1383 *status = 0;
1384
1385 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1386
1387 if (dmd_state & 0x40) {
1388 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1389 if (dstatus & 0x08)
1390 cur_receive_mode = (dmd_state & 0x20) ?
1391 RCVMODE_DVBS : RCVMODE_DVBS2;
1392 }
1393 if (cur_receive_mode == RCVMODE_NONE) {
1394 set_vth(state);
1395
1396 /* reset signal statistics */
1397 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1398 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1399 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1400 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1401
1402 return 0;
1403 }
1404
1405 *status |= (FE_HAS_SIGNAL
1406 | FE_HAS_CARRIER
1407 | FE_HAS_VITERBI
1408 | FE_HAS_SYNC);
1409
1410 if (state->receive_mode == RCVMODE_NONE) {
1411 state->receive_mode = cur_receive_mode;
1412 state->demod_lock_time = jiffies;
1413 state->first_time_lock = 1;
1414
1415 get_signal_parameters(state);
1416 tracking_optimization(state);
1417
1418 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1419 state->tscfgh);
1420 usleep_range(3000, 4000);
1421 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1422 state->tscfgh | 0x01);
1423 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1424 state->tscfgh);
1425 }
1426 if (dmd_state & 0x40) {
1427 if (state->receive_mode == RCVMODE_DVBS2) {
1428 u8 pdelstatus;
1429
1430 read_reg(state,
1431 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1432 &pdelstatus);
1433 feclock = (pdelstatus & 0x02) != 0;
1434 } else {
1435 u8 vstatus;
1436
1437 read_reg(state,
1438 RSTV0910_P2_VSTATUSVIT + state->regoff,
1439 &vstatus);
1440 feclock = (vstatus & 0x08) != 0;
1441 }
1442 }
1443
1444 if (feclock) {
1445 *status |= FE_HAS_LOCK;
1446
1447 if (state->first_time_lock) {
1448 u8 tmp;
1449
1450 state->first_time_lock = 0;
1451
1452 manage_matype_info(state);
1453
1454 if (state->receive_mode == RCVMODE_DVBS2) {
1455 /*
1456 * FSTV0910_P2_MANUALSX_ROLLOFF,
1457 * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1458 */
1459 state->demod_bits &= ~0x84;
1460 write_reg(state,
1461 RSTV0910_P2_DEMOD + state->regoff,
1462 state->demod_bits);
1463 read_reg(state,
1464 RSTV0910_P2_PDELCTRL2 + state->regoff,
1465 &tmp);
1466 /* reset DVBS2 packet delinator error counter */
1467 tmp |= 0x40;
1468 write_reg(state,
1469 RSTV0910_P2_PDELCTRL2 + state->regoff,
1470 tmp);
1471 /* reset DVBS2 packet delinator error counter */
1472 tmp &= ~0x40;
1473 write_reg(state,
1474 RSTV0910_P2_PDELCTRL2 + state->regoff,
1475 tmp);
1476
1477 state->berscale = 2;
1478 state->last_bernumerator = 0;
1479 state->last_berdenominator = 1;
1480 /* force to PRE BCH Rate */
1481 write_reg(state,
1482 RSTV0910_P2_ERRCTRL1 + state->regoff,
1483 BER_SRC_S2 | state->berscale);
1484 } else {
1485 state->berscale = 2;
1486 state->last_bernumerator = 0;
1487 state->last_berdenominator = 1;
1488 /* force to PRE RS Rate */
1489 write_reg(state,
1490 RSTV0910_P2_ERRCTRL1 + state->regoff,
1491 BER_SRC_S | state->berscale);
1492 }
1493 /* Reset the Total packet counter */
1494 write_reg(state,
1495 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1496 /*
1497 * Reset the packet Error counter2 (and Set it to
1498 * infinit error count mode)
1499 */
1500 write_reg(state,
1501 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1502
1503 set_vth_default(state);
1504 if (state->receive_mode == RCVMODE_DVBS)
1505 enable_puncture_rate(state,
1506 state->puncture_rate);
1507 }
1508
1509 /* Use highest signaled ModCod for quality */
1510 if (state->is_vcm) {
1511 u8 tmp;
1512 enum fe_stv0910_mod_cod mod_cod;
1513
1514 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1515 &tmp);
1516 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
1517
1518 if (mod_cod > state->mod_cod)
1519 state->mod_cod = mod_cod;
1520 }
1521 }
1522
1523 /* read signal statistics */
1524
1525 /* read signal strength */
1526 read_signal_strength(fe);
1527
1528 /* read carrier/noise on FE_HAS_CARRIER */
1529 if (*status & FE_HAS_CARRIER)
1530 read_snr(fe);
1531 else
1532 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1533
1534 /* read ber */
1535 if (*status & FE_HAS_VITERBI) {
1536 read_ber(fe);
1537 } else {
1538 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1539 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1540 }
1541
1542 return 0;
1543 }
1544
1545 static int get_frontend(struct dvb_frontend *fe,
1546 struct dtv_frontend_properties *p)
1547 {
1548 struct stv *state = fe->demodulator_priv;
1549 u8 tmp;
1550 u32 symbolrate;
1551
1552 if (state->receive_mode == RCVMODE_DVBS2) {
1553 u32 mc;
1554 const enum fe_modulation modcod2mod[0x20] = {
1555 QPSK, QPSK, QPSK, QPSK,
1556 QPSK, QPSK, QPSK, QPSK,
1557 QPSK, QPSK, QPSK, QPSK,
1558 PSK_8, PSK_8, PSK_8, PSK_8,
1559 PSK_8, PSK_8, APSK_16, APSK_16,
1560 APSK_16, APSK_16, APSK_16, APSK_16,
1561 APSK_32, APSK_32, APSK_32, APSK_32,
1562 APSK_32,
1563 };
1564 const enum fe_code_rate modcod2fec[0x20] = {
1565 FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1566 FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1567 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1568 FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1569 FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1570 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1571 FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1572 FEC_9_10
1573 };
1574 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1575 mc = ((tmp & 0x7c) >> 2);
1576 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1577 p->modulation = modcod2mod[mc];
1578 p->fec_inner = modcod2fec[mc];
1579 } else if (state->receive_mode == RCVMODE_DVBS) {
1580 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1581 switch (tmp & 0x1F) {
1582 case 0x0d:
1583 p->fec_inner = FEC_1_2;
1584 break;
1585 case 0x12:
1586 p->fec_inner = FEC_2_3;
1587 break;
1588 case 0x15:
1589 p->fec_inner = FEC_3_4;
1590 break;
1591 case 0x18:
1592 p->fec_inner = FEC_5_6;
1593 break;
1594 case 0x1a:
1595 p->fec_inner = FEC_7_8;
1596 break;
1597 default:
1598 p->fec_inner = FEC_NONE;
1599 break;
1600 }
1601 p->rolloff = ROLLOFF_35;
1602 }
1603
1604 if (state->receive_mode != RCVMODE_NONE) {
1605 get_cur_symbol_rate(state, &symbolrate);
1606 p->symbol_rate = symbolrate;
1607 }
1608 return 0;
1609 }
1610
1611 static int tune(struct dvb_frontend *fe, bool re_tune,
1612 unsigned int mode_flags,
1613 unsigned int *delay, enum fe_status *status)
1614 {
1615 struct stv *state = fe->demodulator_priv;
1616 int r;
1617
1618 if (re_tune) {
1619 r = set_parameters(fe);
1620 if (r)
1621 return r;
1622 state->tune_time = jiffies;
1623 }
1624
1625 r = read_status(fe, status);
1626 if (r)
1627 return r;
1628
1629 if (*status & FE_HAS_LOCK)
1630 return 0;
1631 *delay = HZ;
1632
1633 return 0;
1634 }
1635
1636 static int get_algo(struct dvb_frontend *fe)
1637 {
1638 return DVBFE_ALGO_HW;
1639 }
1640
1641 static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1642 {
1643 struct stv *state = fe->demodulator_priv;
1644 u16 offs = state->nr ? 0x40 : 0;
1645
1646 switch (tone) {
1647 case SEC_TONE_ON:
1648 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1649 case SEC_TONE_OFF:
1650 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1651 default:
1652 break;
1653 }
1654 return -EINVAL;
1655 }
1656
1657 static int wait_dis(struct stv *state, u8 flag, u8 val)
1658 {
1659 int i;
1660 u8 stat;
1661 u16 offs = state->nr ? 0x40 : 0;
1662
1663 for (i = 0; i < 10; i++) {
1664 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1665 if ((stat & flag) == val)
1666 return 0;
1667 usleep_range(10000, 11000);
1668 }
1669 return -ETIMEDOUT;
1670 }
1671
1672 static int send_master_cmd(struct dvb_frontend *fe,
1673 struct dvb_diseqc_master_cmd *cmd)
1674 {
1675 struct stv *state = fe->demodulator_priv;
1676 u16 offs = state->nr ? 0x40 : 0;
1677 int i;
1678
1679 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
1680 for (i = 0; i < cmd->msg_len; i++) {
1681 wait_dis(state, 0x40, 0x00);
1682 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]);
1683 }
1684 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
1685 wait_dis(state, 0x20, 0x20);
1686 return 0;
1687 }
1688
1689 static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1690 {
1691 struct stv *state = fe->demodulator_priv;
1692 u16 offs = state->nr ? 0x40 : 0;
1693 u8 value;
1694
1695 if (burst == SEC_MINI_A) {
1696 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3F);
1697 value = 0x00;
1698 } else {
1699 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
1700 value = 0xFF;
1701 }
1702 wait_dis(state, 0x40, 0x00);
1703 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, value);
1704 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
1705 wait_dis(state, 0x20, 0x20);
1706
1707 return 0;
1708 }
1709
1710 static int sleep(struct dvb_frontend *fe)
1711 {
1712 struct stv *state = fe->demodulator_priv;
1713
1714 stop(state);
1715 return 0;
1716 }
1717
1718 static const struct dvb_frontend_ops stv0910_ops = {
1719 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1720 .info = {
1721 .name = "ST STV0910",
1722 .frequency_min = 950000,
1723 .frequency_max = 2150000,
1724 .frequency_stepsize = 0,
1725 .frequency_tolerance = 0,
1726 .symbol_rate_min = 100000,
1727 .symbol_rate_max = 70000000,
1728 .caps = FE_CAN_INVERSION_AUTO |
1729 FE_CAN_FEC_AUTO |
1730 FE_CAN_QPSK |
1731 FE_CAN_2G_MODULATION |
1732 FE_CAN_MULTISTREAM
1733 },
1734 .sleep = sleep,
1735 .release = release,
1736 .i2c_gate_ctrl = gate_ctrl,
1737 .set_frontend = set_parameters,
1738 .get_frontend_algo = get_algo,
1739 .get_frontend = get_frontend,
1740 .tune = tune,
1741 .read_status = read_status,
1742 .set_tone = set_tone,
1743
1744 .diseqc_send_master_cmd = send_master_cmd,
1745 .diseqc_send_burst = send_burst,
1746 };
1747
1748 static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
1749 {
1750 struct stv_base *p;
1751
1752 list_for_each_entry(p, &stvlist, stvlist)
1753 if (p->i2c == i2c && p->adr == adr)
1754 return p;
1755 return NULL;
1756 }
1757
1758 static void stv0910_init_stats(struct stv *state)
1759 {
1760 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1761
1762 p->strength.len = 1;
1763 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1764 p->cnr.len = 1;
1765 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1766 p->pre_bit_error.len = 1;
1767 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1768 p->pre_bit_count.len = 1;
1769 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1770 }
1771
1772 struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1773 struct stv0910_cfg *cfg,
1774 int nr)
1775 {
1776 struct stv *state;
1777 struct stv_base *base;
1778
1779 state = kzalloc(sizeof(*state), GFP_KERNEL);
1780 if (!state)
1781 return NULL;
1782
1783 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1784 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1785 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1786 state->tsspeed = 0x28;
1787 state->nr = nr;
1788 state->regoff = state->nr ? 0 : 0x200;
1789 state->search_range = 16000000;
1790 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1791 state->receive_mode = RCVMODE_NONE;
1792 state->cur_scrambling_code = (~0U);
1793 state->single = cfg->single ? 1 : 0;
1794
1795 base = match_base(i2c, cfg->adr);
1796 if (base) {
1797 base->count++;
1798 state->base = base;
1799 } else {
1800 base = kzalloc(sizeof(*base), GFP_KERNEL);
1801 if (!base)
1802 goto fail;
1803 base->i2c = i2c;
1804 base->adr = cfg->adr;
1805 base->count = 1;
1806 base->extclk = cfg->clk ? cfg->clk : 30000000;
1807
1808 mutex_init(&base->i2c_lock);
1809 mutex_init(&base->reg_lock);
1810 state->base = base;
1811 if (probe(state) < 0) {
1812 dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
1813 cfg->adr, dev_name(&i2c->dev));
1814 kfree(base);
1815 goto fail;
1816 }
1817 list_add(&base->stvlist, &stvlist);
1818 }
1819 state->fe.ops = stv0910_ops;
1820 state->fe.demodulator_priv = state;
1821 state->nr = nr;
1822
1823 dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
1824 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1825
1826 stv0910_init_stats(state);
1827
1828 return &state->fe;
1829
1830 fail:
1831 kfree(state);
1832 return NULL;
1833 }
1834 EXPORT_SYMBOL_GPL(stv0910_attach);
1835
1836 MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1837 MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1838 MODULE_LICENSE("GPL");
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