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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / media / platform / omap3isp / isp.c
blob8eb000e3d8fdd188f0ff6303fb1949204a1ef2cd
1 /*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
43 */
44
45 #include <asm/cacheflush.h>
46
47 #include <linux/clk.h>
48 #include <linux/clkdev.h>
49 #include <linux/delay.h>
50 #include <linux/device.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/i2c.h>
53 #include <linux/interrupt.h>
54 #include <linux/mfd/syscon.h>
55 #include <linux/module.h>
56 #include <linux/omap-iommu.h>
57 #include <linux/platform_device.h>
58 #include <linux/property.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/slab.h>
61 #include <linux/sched.h>
62 #include <linux/vmalloc.h>
63
64 #include <asm/dma-iommu.h>
65
66 #include <media/v4l2-common.h>
67 #include <media/v4l2-fwnode.h>
68 #include <media/v4l2-device.h>
69 #include <media/v4l2-mc.h>
70
71 #include "isp.h"
72 #include "ispreg.h"
73 #include "ispccdc.h"
74 #include "isppreview.h"
75 #include "ispresizer.h"
76 #include "ispcsi2.h"
77 #include "ispccp2.h"
78 #include "isph3a.h"
79 #include "isphist.h"
80
81 static unsigned int autoidle;
82 module_param(autoidle, int, 0444);
83 MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
84
85 static void isp_save_ctx(struct isp_device *isp);
86
87 static void isp_restore_ctx(struct isp_device *isp);
88
89 static const struct isp_res_mapping isp_res_maps[] = {
90 {
91 .isp_rev = ISP_REVISION_2_0,
92 .offset = {
93 /* first MMIO area */
94 0x0000, /* base, len 0x0070 */
95 0x0400, /* ccp2, len 0x01f0 */
96 0x0600, /* ccdc, len 0x00a8 */
97 0x0a00, /* hist, len 0x0048 */
98 0x0c00, /* h3a, len 0x0060 */
99 0x0e00, /* preview, len 0x00a0 */
100 0x1000, /* resizer, len 0x00ac */
101 0x1200, /* sbl, len 0x00fc */
102 /* second MMIO area */
103 0x0000, /* csi2a, len 0x0170 */
104 0x0170, /* csiphy2, len 0x000c */
105 },
106 .phy_type = ISP_PHY_TYPE_3430,
107 },
108 {
109 .isp_rev = ISP_REVISION_15_0,
110 .offset = {
111 /* first MMIO area */
112 0x0000, /* base, len 0x0070 */
113 0x0400, /* ccp2, len 0x01f0 */
114 0x0600, /* ccdc, len 0x00a8 */
115 0x0a00, /* hist, len 0x0048 */
116 0x0c00, /* h3a, len 0x0060 */
117 0x0e00, /* preview, len 0x00a0 */
118 0x1000, /* resizer, len 0x00ac */
119 0x1200, /* sbl, len 0x00fc */
120 /* second MMIO area */
121 0x0000, /* csi2a, len 0x0170 (1st area) */
122 0x0170, /* csiphy2, len 0x000c */
123 0x01c0, /* csi2a, len 0x0040 (2nd area) */
124 0x0400, /* csi2c, len 0x0170 (1st area) */
125 0x0570, /* csiphy1, len 0x000c */
126 0x05c0, /* csi2c, len 0x0040 (2nd area) */
127 },
128 .phy_type = ISP_PHY_TYPE_3630,
129 },
130 };
131
132 /* Structure for saving/restoring ISP module registers */
133 static struct isp_reg isp_reg_list[] = {
134 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
135 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
136 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
137 {0, ISP_TOK_TERM, 0}
138 };
139
140 /*
141 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
142 * @isp: OMAP3 ISP device
143 *
144 * In order to force posting of pending writes, we need to write and
145 * readback the same register, in this case the revision register.
146 *
147 * See this link for reference:
148 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
149 */
150 void omap3isp_flush(struct isp_device *isp)
151 {
152 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
153 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
154 }
155
156 /* -----------------------------------------------------------------------------
157 * XCLK
158 */
159
160 #define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
161
162 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
163 {
164 switch (xclk->id) {
165 case ISP_XCLK_A:
166 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
167 ISPTCTRL_CTRL_DIVA_MASK,
168 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
169 break;
170 case ISP_XCLK_B:
171 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
172 ISPTCTRL_CTRL_DIVB_MASK,
173 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
174 break;
175 }
176 }
177
178 static int isp_xclk_prepare(struct clk_hw *hw)
179 {
180 struct isp_xclk *xclk = to_isp_xclk(hw);
181
182 omap3isp_get(xclk->isp);
183
184 return 0;
185 }
186
187 static void isp_xclk_unprepare(struct clk_hw *hw)
188 {
189 struct isp_xclk *xclk = to_isp_xclk(hw);
190
191 omap3isp_put(xclk->isp);
192 }
193
194 static int isp_xclk_enable(struct clk_hw *hw)
195 {
196 struct isp_xclk *xclk = to_isp_xclk(hw);
197 unsigned long flags;
198
199 spin_lock_irqsave(&xclk->lock, flags);
200 isp_xclk_update(xclk, xclk->divider);
201 xclk->enabled = true;
202 spin_unlock_irqrestore(&xclk->lock, flags);
203
204 return 0;
205 }
206
207 static void isp_xclk_disable(struct clk_hw *hw)
208 {
209 struct isp_xclk *xclk = to_isp_xclk(hw);
210 unsigned long flags;
211
212 spin_lock_irqsave(&xclk->lock, flags);
213 isp_xclk_update(xclk, 0);
214 xclk->enabled = false;
215 spin_unlock_irqrestore(&xclk->lock, flags);
216 }
217
218 static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
220 {
221 struct isp_xclk *xclk = to_isp_xclk(hw);
222
223 return parent_rate / xclk->divider;
224 }
225
226 static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
227 {
228 u32 divider;
229
230 if (*rate >= parent_rate) {
231 *rate = parent_rate;
232 return ISPTCTRL_CTRL_DIV_BYPASS;
233 }
234
235 if (*rate == 0)
236 *rate = 1;
237
238 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
239 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
240 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
241
242 *rate = parent_rate / divider;
243 return divider;
244 }
245
246 static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
247 unsigned long *parent_rate)
248 {
249 isp_xclk_calc_divider(&rate, *parent_rate);
250 return rate;
251 }
252
253 static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
254 unsigned long parent_rate)
255 {
256 struct isp_xclk *xclk = to_isp_xclk(hw);
257 unsigned long flags;
258 u32 divider;
259
260 divider = isp_xclk_calc_divider(&rate, parent_rate);
261
262 spin_lock_irqsave(&xclk->lock, flags);
263
264 xclk->divider = divider;
265 if (xclk->enabled)
266 isp_xclk_update(xclk, divider);
267
268 spin_unlock_irqrestore(&xclk->lock, flags);
269
270 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
271 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
272 return 0;
273 }
274
275 static const struct clk_ops isp_xclk_ops = {
276 .prepare = isp_xclk_prepare,
277 .unprepare = isp_xclk_unprepare,
278 .enable = isp_xclk_enable,
279 .disable = isp_xclk_disable,
280 .recalc_rate = isp_xclk_recalc_rate,
281 .round_rate = isp_xclk_round_rate,
282 .set_rate = isp_xclk_set_rate,
283 };
284
285 static const char *isp_xclk_parent_name = "cam_mclk";
286
287 static const struct clk_init_data isp_xclk_init_data = {
288 .name = "cam_xclk",
289 .ops = &isp_xclk_ops,
290 .parent_names = &isp_xclk_parent_name,
291 .num_parents = 1,
292 };
293
294 static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
295 {
296 unsigned int idx = clkspec->args[0];
297 struct isp_device *isp = data;
298
299 if (idx >= ARRAY_SIZE(isp->xclks))
300 return ERR_PTR(-ENOENT);
301
302 return isp->xclks[idx].clk;
303 }
304
305 static int isp_xclk_init(struct isp_device *isp)
306 {
307 struct device_node *np = isp->dev->of_node;
308 struct clk_init_data init;
309 unsigned int i;
310
311 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
312 isp->xclks[i].clk = ERR_PTR(-EINVAL);
313
314 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
315 struct isp_xclk *xclk = &isp->xclks[i];
316
317 xclk->isp = isp;
318 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
319 xclk->divider = 1;
320 spin_lock_init(&xclk->lock);
321
322 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
323 init.ops = &isp_xclk_ops;
324 init.parent_names = &isp_xclk_parent_name;
325 init.num_parents = 1;
326
327 xclk->hw.init = &init;
328 /*
329 * The first argument is NULL in order to avoid circular
330 * reference, as this driver takes reference on the
331 * sensor subdevice modules and the sensors would take
332 * reference on this module through clk_get().
333 */
334 xclk->clk = clk_register(NULL, &xclk->hw);
335 if (IS_ERR(xclk->clk))
336 return PTR_ERR(xclk->clk);
337 }
338
339 if (np)
340 of_clk_add_provider(np, isp_xclk_src_get, isp);
341
342 return 0;
343 }
344
345 static void isp_xclk_cleanup(struct isp_device *isp)
346 {
347 struct device_node *np = isp->dev->of_node;
348 unsigned int i;
349
350 if (np)
351 of_clk_del_provider(np);
352
353 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
354 struct isp_xclk *xclk = &isp->xclks[i];
355
356 if (!IS_ERR(xclk->clk))
357 clk_unregister(xclk->clk);
358 }
359 }
360
361 /* -----------------------------------------------------------------------------
362 * Interrupts
363 */
364
365 /*
366 * isp_enable_interrupts - Enable ISP interrupts.
367 * @isp: OMAP3 ISP device
368 */
369 static void isp_enable_interrupts(struct isp_device *isp)
370 {
371 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
372 | IRQ0ENABLE_CSIB_IRQ
373 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
374 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
375 | IRQ0ENABLE_CCDC_VD0_IRQ
376 | IRQ0ENABLE_CCDC_VD1_IRQ
377 | IRQ0ENABLE_HS_VS_IRQ
378 | IRQ0ENABLE_HIST_DONE_IRQ
379 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
380 | IRQ0ENABLE_H3A_AF_DONE_IRQ
381 | IRQ0ENABLE_PRV_DONE_IRQ
382 | IRQ0ENABLE_RSZ_DONE_IRQ;
383
384 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
385 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
386 }
387
388 /*
389 * isp_disable_interrupts - Disable ISP interrupts.
390 * @isp: OMAP3 ISP device
391 */
392 static void isp_disable_interrupts(struct isp_device *isp)
393 {
394 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
395 }
396
397 /*
398 * isp_core_init - ISP core settings
399 * @isp: OMAP3 ISP device
400 * @idle: Consider idle state.
401 *
402 * Set the power settings for the ISP and SBL bus and configure the HS/VS
403 * interrupt source.
404 *
405 * We need to configure the HS/VS interrupt source before interrupts get
406 * enabled, as the sensor might be free-running and the ISP default setting
407 * (HS edge) would put an unnecessary burden on the CPU.
408 */
409 static void isp_core_init(struct isp_device *isp, int idle)
410 {
411 isp_reg_writel(isp,
412 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
413 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
414 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
415 ((isp->revision == ISP_REVISION_15_0) ?
416 ISP_SYSCONFIG_AUTOIDLE : 0),
417 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
418
419 isp_reg_writel(isp,
420 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
421 ISPCTRL_SYNC_DETECT_VSRISE,
422 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
423 }
424
425 /*
426 * Configure the bridge and lane shifter. Valid inputs are
427 *
428 * CCDC_INPUT_PARALLEL: Parallel interface
429 * CCDC_INPUT_CSI2A: CSI2a receiver
430 * CCDC_INPUT_CCP2B: CCP2b receiver
431 * CCDC_INPUT_CSI2C: CSI2c receiver
432 *
433 * The bridge and lane shifter are configured according to the selected input
434 * and the ISP platform data.
435 */
436 void omap3isp_configure_bridge(struct isp_device *isp,
437 enum ccdc_input_entity input,
438 const struct isp_parallel_cfg *parcfg,
439 unsigned int shift, unsigned int bridge)
440 {
441 u32 ispctrl_val;
442
443 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
444 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
445 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
446 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
447 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
448 ispctrl_val |= bridge;
449
450 switch (input) {
451 case CCDC_INPUT_PARALLEL:
452 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
453 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
454 shift += parcfg->data_lane_shift;
455 break;
456
457 case CCDC_INPUT_CSI2A:
458 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
459 break;
460
461 case CCDC_INPUT_CCP2B:
462 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
463 break;
464
465 case CCDC_INPUT_CSI2C:
466 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
467 break;
468
469 default:
470 return;
471 }
472
473 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
474
475 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
476 }
477
478 void omap3isp_hist_dma_done(struct isp_device *isp)
479 {
480 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
481 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
482 /* Histogram cannot be enabled in this frame anymore */
483 atomic_set(&isp->isp_hist.buf_err, 1);
484 dev_dbg(isp->dev,
485 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
486 }
487 }
488
489 static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
490 {
491 static const char *name[] = {
492 "CSIA_IRQ",
493 "res1",
494 "res2",
495 "CSIB_LCM_IRQ",
496 "CSIB_IRQ",
497 "res5",
498 "res6",
499 "res7",
500 "CCDC_VD0_IRQ",
501 "CCDC_VD1_IRQ",
502 "CCDC_VD2_IRQ",
503 "CCDC_ERR_IRQ",
504 "H3A_AF_DONE_IRQ",
505 "H3A_AWB_DONE_IRQ",
506 "res14",
507 "res15",
508 "HIST_DONE_IRQ",
509 "CCDC_LSC_DONE",
510 "CCDC_LSC_PREFETCH_COMPLETED",
511 "CCDC_LSC_PREFETCH_ERROR",
512 "PRV_DONE_IRQ",
513 "CBUFF_IRQ",
514 "res22",
515 "res23",
516 "RSZ_DONE_IRQ",
517 "OVF_IRQ",
518 "res26",
519 "res27",
520 "MMU_ERR_IRQ",
521 "OCP_ERR_IRQ",
522 "SEC_ERR_IRQ",
523 "HS_VS_IRQ",
524 };
525 int i;
526
527 dev_dbg(isp->dev, "ISP IRQ: ");
528
529 for (i = 0; i < ARRAY_SIZE(name); i++) {
530 if ((1 << i) & irqstatus)
531 printk(KERN_CONT "%s ", name[i]);
532 }
533 printk(KERN_CONT "\n");
534 }
535
536 static void isp_isr_sbl(struct isp_device *isp)
537 {
538 struct device *dev = isp->dev;
539 struct isp_pipeline *pipe;
540 u32 sbl_pcr;
541
542 /*
543 * Handle shared buffer logic overflows for video buffers.
544 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
545 */
546 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
547 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
548 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
549
550 if (sbl_pcr)
551 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
552
553 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
554 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
555 if (pipe != NULL)
556 pipe->error = true;
557 }
558
559 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
560 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
561 if (pipe != NULL)
562 pipe->error = true;
563 }
564
565 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
566 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
567 if (pipe != NULL)
568 pipe->error = true;
569 }
570
571 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
572 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
573 if (pipe != NULL)
574 pipe->error = true;
575 }
576
577 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
578 | ISPSBL_PCR_RSZ2_WBL_OVF
579 | ISPSBL_PCR_RSZ3_WBL_OVF
580 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
581 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
582 if (pipe != NULL)
583 pipe->error = true;
584 }
585
586 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
587 omap3isp_stat_sbl_overflow(&isp->isp_af);
588
589 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
590 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
591 }
592
593 /*
594 * isp_isr - Interrupt Service Routine for Camera ISP module.
595 * @irq: Not used currently.
596 * @_isp: Pointer to the OMAP3 ISP device
597 *
598 * Handles the corresponding callback if plugged in.
599 */
600 static irqreturn_t isp_isr(int irq, void *_isp)
601 {
602 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
603 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
604 IRQ0STATUS_CCDC_VD0_IRQ |
605 IRQ0STATUS_CCDC_VD1_IRQ |
606 IRQ0STATUS_HS_VS_IRQ;
607 struct isp_device *isp = _isp;
608 u32 irqstatus;
609
610 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
611 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
612
613 isp_isr_sbl(isp);
614
615 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
616 omap3isp_csi2_isr(&isp->isp_csi2a);
617
618 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
619 omap3isp_ccp2_isr(&isp->isp_ccp2);
620
621 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
622 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
623 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
624 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
625 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
626 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
627 omap3isp_stat_isr_frame_sync(&isp->isp_af);
628 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
629 }
630
631 if (irqstatus & ccdc_events)
632 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
633
634 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
635 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
636 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
637 omap3isp_preview_isr(&isp->isp_prev);
638 }
639
640 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
641 omap3isp_resizer_isr(&isp->isp_res);
642
643 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
644 omap3isp_stat_isr(&isp->isp_aewb);
645
646 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
647 omap3isp_stat_isr(&isp->isp_af);
648
649 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
650 omap3isp_stat_isr(&isp->isp_hist);
651
652 omap3isp_flush(isp);
653
654 #if defined(DEBUG) && defined(ISP_ISR_DEBUG)
655 isp_isr_dbg(isp, irqstatus);
656 #endif
657
658 return IRQ_HANDLED;
659 }
660
661 static const struct media_device_ops isp_media_ops = {
662 .link_notify = v4l2_pipeline_link_notify,
663 };
664
665 /* -----------------------------------------------------------------------------
666 * Pipeline stream management
667 */
668
669 /*
670 * isp_pipeline_enable - Enable streaming on a pipeline
671 * @pipe: ISP pipeline
672 * @mode: Stream mode (single shot or continuous)
673 *
674 * Walk the entities chain starting at the pipeline output video node and start
675 * all modules in the chain in the given mode.
676 *
677 * Return 0 if successful, or the return value of the failed video::s_stream
678 * operation otherwise.
679 */
680 static int isp_pipeline_enable(struct isp_pipeline *pipe,
681 enum isp_pipeline_stream_state mode)
682 {
683 struct isp_device *isp = pipe->output->isp;
684 struct media_entity *entity;
685 struct media_pad *pad;
686 struct v4l2_subdev *subdev;
687 unsigned long flags;
688 int ret;
689
690 /* Refuse to start streaming if an entity included in the pipeline has
691 * crashed. This check must be performed before the loop below to avoid
692 * starting entities if the pipeline won't start anyway (those entities
693 * would then likely fail to stop, making the problem worse).
694 */
695 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
696 return -EIO;
697
698 spin_lock_irqsave(&pipe->lock, flags);
699 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
700 spin_unlock_irqrestore(&pipe->lock, flags);
701
702 pipe->do_propagation = false;
703
704 entity = &pipe->output->video.entity;
705 while (1) {
706 pad = &entity->pads[0];
707 if (!(pad->flags & MEDIA_PAD_FL_SINK))
708 break;
709
710 pad = media_entity_remote_pad(pad);
711 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
712 break;
713
714 entity = pad->entity;
715 subdev = media_entity_to_v4l2_subdev(entity);
716
717 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
718 if (ret < 0 && ret != -ENOIOCTLCMD)
719 return ret;
720
721 if (subdev == &isp->isp_ccdc.subdev) {
722 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
723 s_stream, mode);
724 v4l2_subdev_call(&isp->isp_af.subdev, video,
725 s_stream, mode);
726 v4l2_subdev_call(&isp->isp_hist.subdev, video,
727 s_stream, mode);
728 pipe->do_propagation = true;
729 }
730 }
731
732 return 0;
733 }
734
735 static int isp_pipeline_wait_resizer(struct isp_device *isp)
736 {
737 return omap3isp_resizer_busy(&isp->isp_res);
738 }
739
740 static int isp_pipeline_wait_preview(struct isp_device *isp)
741 {
742 return omap3isp_preview_busy(&isp->isp_prev);
743 }
744
745 static int isp_pipeline_wait_ccdc(struct isp_device *isp)
746 {
747 return omap3isp_stat_busy(&isp->isp_af)
748 || omap3isp_stat_busy(&isp->isp_aewb)
749 || omap3isp_stat_busy(&isp->isp_hist)
750 || omap3isp_ccdc_busy(&isp->isp_ccdc);
751 }
752
753 #define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
754
755 static int isp_pipeline_wait(struct isp_device *isp,
756 int(*busy)(struct isp_device *isp))
757 {
758 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
759
760 while (!time_after(jiffies, timeout)) {
761 if (!busy(isp))
762 return 0;
763 }
764
765 return 1;
766 }
767
768 /*
769 * isp_pipeline_disable - Disable streaming on a pipeline
770 * @pipe: ISP pipeline
771 *
772 * Walk the entities chain starting at the pipeline output video node and stop
773 * all modules in the chain. Wait synchronously for the modules to be stopped if
774 * necessary.
775 *
776 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
777 * can't be stopped (in which case a software reset of the ISP is probably
778 * necessary).
779 */
780 static int isp_pipeline_disable(struct isp_pipeline *pipe)
781 {
782 struct isp_device *isp = pipe->output->isp;
783 struct media_entity *entity;
784 struct media_pad *pad;
785 struct v4l2_subdev *subdev;
786 int failure = 0;
787 int ret;
788
789 /*
790 * We need to stop all the modules after CCDC first or they'll
791 * never stop since they may not get a full frame from CCDC.
792 */
793 entity = &pipe->output->video.entity;
794 while (1) {
795 pad = &entity->pads[0];
796 if (!(pad->flags & MEDIA_PAD_FL_SINK))
797 break;
798
799 pad = media_entity_remote_pad(pad);
800 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
801 break;
802
803 entity = pad->entity;
804 subdev = media_entity_to_v4l2_subdev(entity);
805
806 if (subdev == &isp->isp_ccdc.subdev) {
807 v4l2_subdev_call(&isp->isp_aewb.subdev,
808 video, s_stream, 0);
809 v4l2_subdev_call(&isp->isp_af.subdev,
810 video, s_stream, 0);
811 v4l2_subdev_call(&isp->isp_hist.subdev,
812 video, s_stream, 0);
813 }
814
815 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
816
817 if (subdev == &isp->isp_res.subdev)
818 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
819 else if (subdev == &isp->isp_prev.subdev)
820 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
821 else if (subdev == &isp->isp_ccdc.subdev)
822 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
823
824 /* Handle stop failures. An entity that fails to stop can
825 * usually just be restarted. Flag the stop failure nonetheless
826 * to trigger an ISP reset the next time the device is released,
827 * just in case.
828 *
829 * The preview engine is a special case. A failure to stop can
830 * mean a hardware crash. When that happens the preview engine
831 * won't respond to read/write operations on the L4 bus anymore,
832 * resulting in a bus fault and a kernel oops next time it gets
833 * accessed. Mark it as crashed to prevent pipelines including
834 * it from being started.
835 */
836 if (ret) {
837 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
838 isp->stop_failure = true;
839 if (subdev == &isp->isp_prev.subdev)
840 media_entity_enum_set(&isp->crashed,
841 &subdev->entity);
842 failure = -ETIMEDOUT;
843 }
844 }
845
846 return failure;
847 }
848
849 /*
850 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
851 * @pipe: ISP pipeline
852 * @state: Stream state (stopped, single shot or continuous)
853 *
854 * Set the pipeline to the given stream state. Pipelines can be started in
855 * single-shot or continuous mode.
856 *
857 * Return 0 if successful, or the return value of the failed video::s_stream
858 * operation otherwise. The pipeline state is not updated when the operation
859 * fails, except when stopping the pipeline.
860 */
861 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
862 enum isp_pipeline_stream_state state)
863 {
864 int ret;
865
866 if (state == ISP_PIPELINE_STREAM_STOPPED)
867 ret = isp_pipeline_disable(pipe);
868 else
869 ret = isp_pipeline_enable(pipe, state);
870
871 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
872 pipe->stream_state = state;
873
874 return ret;
875 }
876
877 /*
878 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
879 * @pipe: ISP pipeline
880 *
881 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
882 * erroneous and makes sure no new buffer can be queued. This function is called
883 * when a fatal error that prevents any further operation on the pipeline
884 * occurs.
885 */
886 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
887 {
888 if (pipe->input)
889 omap3isp_video_cancel_stream(pipe->input);
890 if (pipe->output)
891 omap3isp_video_cancel_stream(pipe->output);
892 }
893
894 /*
895 * isp_pipeline_resume - Resume streaming on a pipeline
896 * @pipe: ISP pipeline
897 *
898 * Resume video output and input and re-enable pipeline.
899 */
900 static void isp_pipeline_resume(struct isp_pipeline *pipe)
901 {
902 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
903
904 omap3isp_video_resume(pipe->output, !singleshot);
905 if (singleshot)
906 omap3isp_video_resume(pipe->input, 0);
907 isp_pipeline_enable(pipe, pipe->stream_state);
908 }
909
910 /*
911 * isp_pipeline_suspend - Suspend streaming on a pipeline
912 * @pipe: ISP pipeline
913 *
914 * Suspend pipeline.
915 */
916 static void isp_pipeline_suspend(struct isp_pipeline *pipe)
917 {
918 isp_pipeline_disable(pipe);
919 }
920
921 /*
922 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
923 * video node
924 * @me: ISP module's media entity
925 *
926 * Returns 1 if the entity has an enabled link to the output video node or 0
927 * otherwise. It's true only while pipeline can have no more than one output
928 * node.
929 */
930 static int isp_pipeline_is_last(struct media_entity *me)
931 {
932 struct isp_pipeline *pipe;
933 struct media_pad *pad;
934
935 if (!me->pipe)
936 return 0;
937 pipe = to_isp_pipeline(me);
938 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
939 return 0;
940 pad = media_entity_remote_pad(&pipe->output->pad);
941 return pad->entity == me;
942 }
943
944 /*
945 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
946 * @me: ISP module's media entity
947 *
948 * Suspend the whole pipeline if module's entity has an enabled link to the
949 * output video node. It works only while pipeline can have no more than one
950 * output node.
951 */
952 static void isp_suspend_module_pipeline(struct media_entity *me)
953 {
954 if (isp_pipeline_is_last(me))
955 isp_pipeline_suspend(to_isp_pipeline(me));
956 }
957
958 /*
959 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
960 * @me: ISP module's media entity
961 *
962 * Resume the whole pipeline if module's entity has an enabled link to the
963 * output video node. It works only while pipeline can have no more than one
964 * output node.
965 */
966 static void isp_resume_module_pipeline(struct media_entity *me)
967 {
968 if (isp_pipeline_is_last(me))
969 isp_pipeline_resume(to_isp_pipeline(me));
970 }
971
972 /*
973 * isp_suspend_modules - Suspend ISP submodules.
974 * @isp: OMAP3 ISP device
975 *
976 * Returns 0 if suspend left in idle state all the submodules properly,
977 * or returns 1 if a general Reset is required to suspend the submodules.
978 */
979 static int isp_suspend_modules(struct isp_device *isp)
980 {
981 unsigned long timeout;
982
983 omap3isp_stat_suspend(&isp->isp_aewb);
984 omap3isp_stat_suspend(&isp->isp_af);
985 omap3isp_stat_suspend(&isp->isp_hist);
986 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
987 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
988 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
989 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
990 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
991
992 timeout = jiffies + ISP_STOP_TIMEOUT;
993 while (omap3isp_stat_busy(&isp->isp_af)
994 || omap3isp_stat_busy(&isp->isp_aewb)
995 || omap3isp_stat_busy(&isp->isp_hist)
996 || omap3isp_preview_busy(&isp->isp_prev)
997 || omap3isp_resizer_busy(&isp->isp_res)
998 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
999 if (time_after(jiffies, timeout)) {
1000 dev_info(isp->dev, "can't stop modules.\n");
1001 return 1;
1002 }
1003 msleep(1);
1004 }
1005
1006 return 0;
1007 }
1008
1009 /*
1010 * isp_resume_modules - Resume ISP submodules.
1011 * @isp: OMAP3 ISP device
1012 */
1013 static void isp_resume_modules(struct isp_device *isp)
1014 {
1015 omap3isp_stat_resume(&isp->isp_aewb);
1016 omap3isp_stat_resume(&isp->isp_af);
1017 omap3isp_stat_resume(&isp->isp_hist);
1018 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1019 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1020 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1021 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1022 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1023 }
1024
1025 /*
1026 * isp_reset - Reset ISP with a timeout wait for idle.
1027 * @isp: OMAP3 ISP device
1028 */
1029 static int isp_reset(struct isp_device *isp)
1030 {
1031 unsigned long timeout = 0;
1032
1033 isp_reg_writel(isp,
1034 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1035 | ISP_SYSCONFIG_SOFTRESET,
1036 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1037 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1038 ISP_SYSSTATUS) & 0x1)) {
1039 if (timeout++ > 10000) {
1040 dev_alert(isp->dev, "cannot reset ISP\n");
1041 return -ETIMEDOUT;
1042 }
1043 udelay(1);
1044 }
1045
1046 isp->stop_failure = false;
1047 media_entity_enum_zero(&isp->crashed);
1048 return 0;
1049 }
1050
1051 /*
1052 * isp_save_context - Saves the values of the ISP module registers.
1053 * @isp: OMAP3 ISP device
1054 * @reg_list: Structure containing pairs of register address and value to
1055 * modify on OMAP.
1056 */
1057 static void
1058 isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1059 {
1060 struct isp_reg *next = reg_list;
1061
1062 for (; next->reg != ISP_TOK_TERM; next++)
1063 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1064 }
1065
1066 /*
1067 * isp_restore_context - Restores the values of the ISP module registers.
1068 * @isp: OMAP3 ISP device
1069 * @reg_list: Structure containing pairs of register address and value to
1070 * modify on OMAP.
1071 */
1072 static void
1073 isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1074 {
1075 struct isp_reg *next = reg_list;
1076
1077 for (; next->reg != ISP_TOK_TERM; next++)
1078 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1079 }
1080
1081 /*
1082 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1083 * @isp: OMAP3 ISP device
1084 *
1085 * Routine for saving the context of each module in the ISP.
1086 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1087 */
1088 static void isp_save_ctx(struct isp_device *isp)
1089 {
1090 isp_save_context(isp, isp_reg_list);
1091 omap_iommu_save_ctx(isp->dev);
1092 }
1093
1094 /*
1095 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1096 * @isp: OMAP3 ISP device
1097 *
1098 * Routine for restoring the context of each module in the ISP.
1099 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1100 */
1101 static void isp_restore_ctx(struct isp_device *isp)
1102 {
1103 isp_restore_context(isp, isp_reg_list);
1104 omap_iommu_restore_ctx(isp->dev);
1105 omap3isp_ccdc_restore_context(isp);
1106 omap3isp_preview_restore_context(isp);
1107 }
1108
1109 /* -----------------------------------------------------------------------------
1110 * SBL resources management
1111 */
1112 #define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1113 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1114 OMAP3_ISP_SBL_PREVIEW_READ | \
1115 OMAP3_ISP_SBL_RESIZER_READ)
1116 #define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1117 OMAP3_ISP_SBL_CSI2A_WRITE | \
1118 OMAP3_ISP_SBL_CSI2C_WRITE | \
1119 OMAP3_ISP_SBL_CCDC_WRITE | \
1120 OMAP3_ISP_SBL_PREVIEW_WRITE)
1121
1122 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1123 {
1124 u32 sbl = 0;
1125
1126 isp->sbl_resources |= res;
1127
1128 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1129 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1130
1131 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1132 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1133
1134 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1135 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1136
1137 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1138 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1139
1140 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1141 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1142
1143 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1144 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1145
1146 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1147 }
1148
1149 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1150 {
1151 u32 sbl = 0;
1152
1153 isp->sbl_resources &= ~res;
1154
1155 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1156 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1157
1158 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1159 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1160
1161 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1162 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1163
1164 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1165 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1166
1167 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1168 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1169
1170 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1171 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1172
1173 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1174 }
1175
1176 /*
1177 * isp_module_sync_idle - Helper to sync module with its idle state
1178 * @me: ISP submodule's media entity
1179 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1180 * @stopping: flag which tells module wants to stop
1181 *
1182 * This function checks if ISP submodule needs to wait for next interrupt. If
1183 * yes, makes the caller to sleep while waiting for such event.
1184 */
1185 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1186 atomic_t *stopping)
1187 {
1188 struct isp_pipeline *pipe = to_isp_pipeline(me);
1189
1190 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1191 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1192 !isp_pipeline_ready(pipe)))
1193 return 0;
1194
1195 /*
1196 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1197 * scenario. We'll call it here to avoid race conditions.
1198 */
1199 atomic_set(stopping, 1);
1200 smp_mb();
1201
1202 /*
1203 * If module is the last one, it's writing to memory. In this case,
1204 * it's necessary to check if the module is already paused due to
1205 * DMA queue underrun or if it has to wait for next interrupt to be
1206 * idle.
1207 * If it isn't the last one, the function won't sleep but *stopping
1208 * will still be set to warn next submodule caller's interrupt the
1209 * module wants to be idle.
1210 */
1211 if (isp_pipeline_is_last(me)) {
1212 struct isp_video *video = pipe->output;
1213 unsigned long flags;
1214 spin_lock_irqsave(&video->irqlock, flags);
1215 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1216 spin_unlock_irqrestore(&video->irqlock, flags);
1217 atomic_set(stopping, 0);
1218 smp_mb();
1219 return 0;
1220 }
1221 spin_unlock_irqrestore(&video->irqlock, flags);
1222 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1223 msecs_to_jiffies(1000))) {
1224 atomic_set(stopping, 0);
1225 smp_mb();
1226 return -ETIMEDOUT;
1227 }
1228 }
1229
1230 return 0;
1231 }
1232
1233 /*
1234 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
1235 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1236 * @stopping: flag which tells module wants to stop
1237 *
1238 * This function checks if ISP submodule was stopping. In case of yes, it
1239 * notices the caller by setting stopping to 0 and waking up the wait queue.
1240 * Returns 1 if it was stopping or 0 otherwise.
1241 */
1242 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1243 atomic_t *stopping)
1244 {
1245 if (atomic_cmpxchg(stopping, 1, 0)) {
1246 wake_up(wait);
1247 return 1;
1248 }
1249
1250 return 0;
1251 }
1252
1253 /* --------------------------------------------------------------------------
1254 * Clock management
1255 */
1256
1257 #define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1258 ISPCTRL_HIST_CLK_EN | \
1259 ISPCTRL_RSZ_CLK_EN | \
1260 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1261 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1262
1263 static void __isp_subclk_update(struct isp_device *isp)
1264 {
1265 u32 clk = 0;
1266
1267 /* AEWB and AF share the same clock. */
1268 if (isp->subclk_resources &
1269 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
1270 clk |= ISPCTRL_H3A_CLK_EN;
1271
1272 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1273 clk |= ISPCTRL_HIST_CLK_EN;
1274
1275 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1276 clk |= ISPCTRL_RSZ_CLK_EN;
1277
1278 /* NOTE: For CCDC & Preview submodules, we need to affect internal
1279 * RAM as well.
1280 */
1281 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1282 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1283
1284 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1285 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1286
1287 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1288 ISPCTRL_CLKS_MASK, clk);
1289 }
1290
1291 void omap3isp_subclk_enable(struct isp_device *isp,
1292 enum isp_subclk_resource res)
1293 {
1294 isp->subclk_resources |= res;
1295
1296 __isp_subclk_update(isp);
1297 }
1298
1299 void omap3isp_subclk_disable(struct isp_device *isp,
1300 enum isp_subclk_resource res)
1301 {
1302 isp->subclk_resources &= ~res;
1303
1304 __isp_subclk_update(isp);
1305 }
1306
1307 /*
1308 * isp_enable_clocks - Enable ISP clocks
1309 * @isp: OMAP3 ISP device
1310 *
1311 * Return 0 if successful, or clk_prepare_enable return value if any of them
1312 * fails.
1313 */
1314 static int isp_enable_clocks(struct isp_device *isp)
1315 {
1316 int r;
1317 unsigned long rate;
1318
1319 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
1320 if (r) {
1321 dev_err(isp->dev, "failed to enable cam_ick clock\n");
1322 goto out_clk_enable_ick;
1323 }
1324 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
1325 if (r) {
1326 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
1327 goto out_clk_enable_mclk;
1328 }
1329 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
1330 if (r) {
1331 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
1332 goto out_clk_enable_mclk;
1333 }
1334 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1335 if (rate != CM_CAM_MCLK_HZ)
1336 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1337 " expected : %d\n"
1338 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
1339 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
1340 if (r) {
1341 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
1342 goto out_clk_enable_csi2_fclk;
1343 }
1344 return 0;
1345
1346 out_clk_enable_csi2_fclk:
1347 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1348 out_clk_enable_mclk:
1349 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1350 out_clk_enable_ick:
1351 return r;
1352 }
1353
1354 /*
1355 * isp_disable_clocks - Disable ISP clocks
1356 * @isp: OMAP3 ISP device
1357 */
1358 static void isp_disable_clocks(struct isp_device *isp)
1359 {
1360 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1361 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1362 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
1363 }
1364
1365 static const char *isp_clocks[] = {
1366 "cam_ick",
1367 "cam_mclk",
1368 "csi2_96m_fck",
1369 "l3_ick",
1370 };
1371
1372 static int isp_get_clocks(struct isp_device *isp)
1373 {
1374 struct clk *clk;
1375 unsigned int i;
1376
1377 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1378 clk = devm_clk_get(isp->dev, isp_clocks[i]);
1379 if (IS_ERR(clk)) {
1380 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1381 return PTR_ERR(clk);
1382 }
1383
1384 isp->clock[i] = clk;
1385 }
1386
1387 return 0;
1388 }
1389
1390 /*
1391 * omap3isp_get - Acquire the ISP resource.
1392 *
1393 * Initializes the clocks for the first acquire.
1394 *
1395 * Increment the reference count on the ISP. If the first reference is taken,
1396 * enable clocks and power-up all submodules.
1397 *
1398 * Return a pointer to the ISP device structure, or NULL if an error occurred.
1399 */
1400 static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
1401 {
1402 struct isp_device *__isp = isp;
1403
1404 if (isp == NULL)
1405 return NULL;
1406
1407 mutex_lock(&isp->isp_mutex);
1408 if (isp->ref_count > 0)
1409 goto out;
1410
1411 if (isp_enable_clocks(isp) < 0) {
1412 __isp = NULL;
1413 goto out;
1414 }
1415
1416 /* We don't want to restore context before saving it! */
1417 if (isp->has_context)
1418 isp_restore_ctx(isp);
1419
1420 if (irq)
1421 isp_enable_interrupts(isp);
1422
1423 out:
1424 if (__isp != NULL)
1425 isp->ref_count++;
1426 mutex_unlock(&isp->isp_mutex);
1427
1428 return __isp;
1429 }
1430
1431 struct isp_device *omap3isp_get(struct isp_device *isp)
1432 {
1433 return __omap3isp_get(isp, true);
1434 }
1435
1436 /*
1437 * omap3isp_put - Release the ISP
1438 *
1439 * Decrement the reference count on the ISP. If the last reference is released,
1440 * power-down all submodules, disable clocks and free temporary buffers.
1441 */
1442 static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
1443 {
1444 if (isp == NULL)
1445 return;
1446
1447 mutex_lock(&isp->isp_mutex);
1448 BUG_ON(isp->ref_count == 0);
1449 if (--isp->ref_count == 0) {
1450 isp_disable_interrupts(isp);
1451 if (save_ctx) {
1452 isp_save_ctx(isp);
1453 isp->has_context = 1;
1454 }
1455 /* Reset the ISP if an entity has failed to stop. This is the
1456 * only way to recover from such conditions.
1457 */
1458 if (!media_entity_enum_empty(&isp->crashed) ||
1459 isp->stop_failure)
1460 isp_reset(isp);
1461 isp_disable_clocks(isp);
1462 }
1463 mutex_unlock(&isp->isp_mutex);
1464 }
1465
1466 void omap3isp_put(struct isp_device *isp)
1467 {
1468 __omap3isp_put(isp, true);
1469 }
1470
1471 /* --------------------------------------------------------------------------
1472 * Platform device driver
1473 */
1474
1475 /*
1476 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1477 * @isp: OMAP3 ISP device
1478 */
1479 #define ISP_PRINT_REGISTER(isp, name)\
1480 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1481 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1482 #define SBL_PRINT_REGISTER(isp, name)\
1483 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1484 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1485
1486 void omap3isp_print_status(struct isp_device *isp)
1487 {
1488 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1489
1490 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1491 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1492 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1493 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1494 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1495 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1496 ISP_PRINT_REGISTER(isp, CTRL);
1497 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1498 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1499 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1500 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1501 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1502 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1503 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1504 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1505
1506 SBL_PRINT_REGISTER(isp, PCR);
1507 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1508
1509 dev_dbg(isp->dev, "--------------------------------------------\n");
1510 }
1511
1512 #ifdef CONFIG_PM
1513
1514 /*
1515 * Power management support.
1516 *
1517 * As the ISP can't properly handle an input video stream interruption on a non
1518 * frame boundary, the ISP pipelines need to be stopped before sensors get
1519 * suspended. However, as suspending the sensors can require a running clock,
1520 * which can be provided by the ISP, the ISP can't be completely suspended
1521 * before the sensor.
1522 *
1523 * To solve this problem power management support is split into prepare/complete
1524 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1525 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1526 * resume(), and the the pipelines are restarted in complete().
1527 *
1528 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
1529 * yet.
1530 */
1531 static int isp_pm_prepare(struct device *dev)
1532 {
1533 struct isp_device *isp = dev_get_drvdata(dev);
1534 int reset;
1535
1536 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1537
1538 if (isp->ref_count == 0)
1539 return 0;
1540
1541 reset = isp_suspend_modules(isp);
1542 isp_disable_interrupts(isp);
1543 isp_save_ctx(isp);
1544 if (reset)
1545 isp_reset(isp);
1546
1547 return 0;
1548 }
1549
1550 static int isp_pm_suspend(struct device *dev)
1551 {
1552 struct isp_device *isp = dev_get_drvdata(dev);
1553
1554 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1555
1556 if (isp->ref_count)
1557 isp_disable_clocks(isp);
1558
1559 return 0;
1560 }
1561
1562 static int isp_pm_resume(struct device *dev)
1563 {
1564 struct isp_device *isp = dev_get_drvdata(dev);
1565
1566 if (isp->ref_count == 0)
1567 return 0;
1568
1569 return isp_enable_clocks(isp);
1570 }
1571
1572 static void isp_pm_complete(struct device *dev)
1573 {
1574 struct isp_device *isp = dev_get_drvdata(dev);
1575
1576 if (isp->ref_count == 0)
1577 return;
1578
1579 isp_restore_ctx(isp);
1580 isp_enable_interrupts(isp);
1581 isp_resume_modules(isp);
1582 }
1583
1584 #else
1585
1586 #define isp_pm_prepare NULL
1587 #define isp_pm_suspend NULL
1588 #define isp_pm_resume NULL
1589 #define isp_pm_complete NULL
1590
1591 #endif /* CONFIG_PM */
1592
1593 static void isp_unregister_entities(struct isp_device *isp)
1594 {
1595 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1596 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1597 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1598 omap3isp_preview_unregister_entities(&isp->isp_prev);
1599 omap3isp_resizer_unregister_entities(&isp->isp_res);
1600 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1601 omap3isp_stat_unregister_entities(&isp->isp_af);
1602 omap3isp_stat_unregister_entities(&isp->isp_hist);
1603
1604 v4l2_device_unregister(&isp->v4l2_dev);
1605 media_device_unregister(&isp->media_dev);
1606 media_device_cleanup(&isp->media_dev);
1607 }
1608
1609 static int isp_link_entity(
1610 struct isp_device *isp, struct media_entity *entity,
1611 enum isp_interface_type interface)
1612 {
1613 struct media_entity *input;
1614 unsigned int flags;
1615 unsigned int pad;
1616 unsigned int i;
1617
1618 /* Connect the sensor to the correct interface module.
1619 * Parallel sensors are connected directly to the CCDC, while
1620 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1621 * receiver through CSIPHY1 or CSIPHY2.
1622 */
1623 switch (interface) {
1624 case ISP_INTERFACE_PARALLEL:
1625 input = &isp->isp_ccdc.subdev.entity;
1626 pad = CCDC_PAD_SINK;
1627 flags = 0;
1628 break;
1629
1630 case ISP_INTERFACE_CSI2A_PHY2:
1631 input = &isp->isp_csi2a.subdev.entity;
1632 pad = CSI2_PAD_SINK;
1633 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1634 break;
1635
1636 case ISP_INTERFACE_CCP2B_PHY1:
1637 case ISP_INTERFACE_CCP2B_PHY2:
1638 input = &isp->isp_ccp2.subdev.entity;
1639 pad = CCP2_PAD_SINK;
1640 flags = 0;
1641 break;
1642
1643 case ISP_INTERFACE_CSI2C_PHY1:
1644 input = &isp->isp_csi2c.subdev.entity;
1645 pad = CSI2_PAD_SINK;
1646 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1647 break;
1648
1649 default:
1650 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1651 interface);
1652 return -EINVAL;
1653 }
1654
1655 /*
1656 * Not all interfaces are available on all revisions of the
1657 * ISP. The sub-devices of those interfaces aren't initialised
1658 * in such a case. Check this by ensuring the num_pads is
1659 * non-zero.
1660 */
1661 if (!input->num_pads) {
1662 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1663 interface);
1664 return -EINVAL;
1665 }
1666
1667 for (i = 0; i < entity->num_pads; i++) {
1668 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1669 break;
1670 }
1671 if (i == entity->num_pads) {
1672 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1673 __func__, entity->name);
1674 return -EINVAL;
1675 }
1676
1677 return media_create_pad_link(entity, i, input, pad, flags);
1678 }
1679
1680 static int isp_register_entities(struct isp_device *isp)
1681 {
1682 int ret;
1683
1684 isp->media_dev.dev = isp->dev;
1685 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1686 sizeof(isp->media_dev.model));
1687 isp->media_dev.hw_revision = isp->revision;
1688 isp->media_dev.ops = &isp_media_ops;
1689 media_device_init(&isp->media_dev);
1690
1691 isp->v4l2_dev.mdev = &isp->media_dev;
1692 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1693 if (ret < 0) {
1694 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1695 __func__, ret);
1696 goto done;
1697 }
1698
1699 /* Register internal entities */
1700 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1701 if (ret < 0)
1702 goto done;
1703
1704 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1705 if (ret < 0)
1706 goto done;
1707
1708 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1709 if (ret < 0)
1710 goto done;
1711
1712 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1713 &isp->v4l2_dev);
1714 if (ret < 0)
1715 goto done;
1716
1717 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1718 if (ret < 0)
1719 goto done;
1720
1721 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1722 if (ret < 0)
1723 goto done;
1724
1725 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1726 if (ret < 0)
1727 goto done;
1728
1729 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1730 if (ret < 0)
1731 goto done;
1732
1733 done:
1734 if (ret < 0)
1735 isp_unregister_entities(isp);
1736
1737 return ret;
1738 }
1739
1740 /*
1741 * isp_create_links() - Create links for internal and external ISP entities
1742 * @isp : Pointer to ISP device
1743 *
1744 * This function creates all links between ISP internal and external entities.
1745 *
1746 * Return: A negative error code on failure or zero on success. Possible error
1747 * codes are those returned by media_create_pad_link().
1748 */
1749 static int isp_create_links(struct isp_device *isp)
1750 {
1751 int ret;
1752
1753 /* Create links between entities and video nodes. */
1754 ret = media_create_pad_link(
1755 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1756 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1757 if (ret < 0)
1758 return ret;
1759
1760 ret = media_create_pad_link(
1761 &isp->isp_ccp2.video_in.video.entity, 0,
1762 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1763 if (ret < 0)
1764 return ret;
1765
1766 ret = media_create_pad_link(
1767 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1768 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1769 if (ret < 0)
1770 return ret;
1771
1772 ret = media_create_pad_link(
1773 &isp->isp_prev.video_in.video.entity, 0,
1774 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1775 if (ret < 0)
1776 return ret;
1777
1778 ret = media_create_pad_link(
1779 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1780 &isp->isp_prev.video_out.video.entity, 0, 0);
1781 if (ret < 0)
1782 return ret;
1783
1784 ret = media_create_pad_link(
1785 &isp->isp_res.video_in.video.entity, 0,
1786 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1787 if (ret < 0)
1788 return ret;
1789
1790 ret = media_create_pad_link(
1791 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1792 &isp->isp_res.video_out.video.entity, 0, 0);
1793
1794 if (ret < 0)
1795 return ret;
1796
1797 /* Create links between entities. */
1798 ret = media_create_pad_link(
1799 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1800 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1801 if (ret < 0)
1802 return ret;
1803
1804 ret = media_create_pad_link(
1805 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1806 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1807 if (ret < 0)
1808 return ret;
1809
1810 ret = media_create_pad_link(
1811 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1812 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1813 if (ret < 0)
1814 return ret;
1815
1816 ret = media_create_pad_link(
1817 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1818 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1819 if (ret < 0)
1820 return ret;
1821
1822 ret = media_create_pad_link(
1823 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1824 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1825 if (ret < 0)
1826 return ret;
1827
1828 ret = media_create_pad_link(
1829 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1830 &isp->isp_aewb.subdev.entity, 0,
1831 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1832 if (ret < 0)
1833 return ret;
1834
1835 ret = media_create_pad_link(
1836 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1837 &isp->isp_af.subdev.entity, 0,
1838 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1839 if (ret < 0)
1840 return ret;
1841
1842 ret = media_create_pad_link(
1843 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1844 &isp->isp_hist.subdev.entity, 0,
1845 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1846 if (ret < 0)
1847 return ret;
1848
1849 return 0;
1850 }
1851
1852 static void isp_cleanup_modules(struct isp_device *isp)
1853 {
1854 omap3isp_h3a_aewb_cleanup(isp);
1855 omap3isp_h3a_af_cleanup(isp);
1856 omap3isp_hist_cleanup(isp);
1857 omap3isp_resizer_cleanup(isp);
1858 omap3isp_preview_cleanup(isp);
1859 omap3isp_ccdc_cleanup(isp);
1860 omap3isp_ccp2_cleanup(isp);
1861 omap3isp_csi2_cleanup(isp);
1862 omap3isp_csiphy_cleanup(isp);
1863 }
1864
1865 static int isp_initialize_modules(struct isp_device *isp)
1866 {
1867 int ret;
1868
1869 ret = omap3isp_csiphy_init(isp);
1870 if (ret < 0) {
1871 dev_err(isp->dev, "CSI PHY initialization failed\n");
1872 return ret;
1873 }
1874
1875 ret = omap3isp_csi2_init(isp);
1876 if (ret < 0) {
1877 dev_err(isp->dev, "CSI2 initialization failed\n");
1878 goto error_csi2;
1879 }
1880
1881 ret = omap3isp_ccp2_init(isp);
1882 if (ret < 0) {
1883 if (ret != -EPROBE_DEFER)
1884 dev_err(isp->dev, "CCP2 initialization failed\n");
1885 goto error_ccp2;
1886 }
1887
1888 ret = omap3isp_ccdc_init(isp);
1889 if (ret < 0) {
1890 dev_err(isp->dev, "CCDC initialization failed\n");
1891 goto error_ccdc;
1892 }
1893
1894 ret = omap3isp_preview_init(isp);
1895 if (ret < 0) {
1896 dev_err(isp->dev, "Preview initialization failed\n");
1897 goto error_preview;
1898 }
1899
1900 ret = omap3isp_resizer_init(isp);
1901 if (ret < 0) {
1902 dev_err(isp->dev, "Resizer initialization failed\n");
1903 goto error_resizer;
1904 }
1905
1906 ret = omap3isp_hist_init(isp);
1907 if (ret < 0) {
1908 dev_err(isp->dev, "Histogram initialization failed\n");
1909 goto error_hist;
1910 }
1911
1912 ret = omap3isp_h3a_aewb_init(isp);
1913 if (ret < 0) {
1914 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1915 goto error_h3a_aewb;
1916 }
1917
1918 ret = omap3isp_h3a_af_init(isp);
1919 if (ret < 0) {
1920 dev_err(isp->dev, "H3A AF initialization failed\n");
1921 goto error_h3a_af;
1922 }
1923
1924 return 0;
1925
1926 error_h3a_af:
1927 omap3isp_h3a_aewb_cleanup(isp);
1928 error_h3a_aewb:
1929 omap3isp_hist_cleanup(isp);
1930 error_hist:
1931 omap3isp_resizer_cleanup(isp);
1932 error_resizer:
1933 omap3isp_preview_cleanup(isp);
1934 error_preview:
1935 omap3isp_ccdc_cleanup(isp);
1936 error_ccdc:
1937 omap3isp_ccp2_cleanup(isp);
1938 error_ccp2:
1939 omap3isp_csi2_cleanup(isp);
1940 error_csi2:
1941 omap3isp_csiphy_cleanup(isp);
1942
1943 return ret;
1944 }
1945
1946 static void isp_detach_iommu(struct isp_device *isp)
1947 {
1948 arm_iommu_release_mapping(isp->mapping);
1949 isp->mapping = NULL;
1950 }
1951
1952 static int isp_attach_iommu(struct isp_device *isp)
1953 {
1954 struct dma_iommu_mapping *mapping;
1955 int ret;
1956
1957 /*
1958 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1959 * VAs. This will allocate a corresponding IOMMU domain.
1960 */
1961 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1962 if (IS_ERR(mapping)) {
1963 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
1964 ret = PTR_ERR(mapping);
1965 goto error;
1966 }
1967
1968 isp->mapping = mapping;
1969
1970 /* Attach the ARM VA mapping to the device. */
1971 ret = arm_iommu_attach_device(isp->dev, mapping);
1972 if (ret < 0) {
1973 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1974 goto error;
1975 }
1976
1977 return 0;
1978
1979 error:
1980 isp_detach_iommu(isp);
1981 return ret;
1982 }
1983
1984 /*
1985 * isp_remove - Remove ISP platform device
1986 * @pdev: Pointer to ISP platform device
1987 *
1988 * Always returns 0.
1989 */
1990 static int isp_remove(struct platform_device *pdev)
1991 {
1992 struct isp_device *isp = platform_get_drvdata(pdev);
1993
1994 v4l2_async_notifier_unregister(&isp->notifier);
1995 isp_unregister_entities(isp);
1996 isp_cleanup_modules(isp);
1997 isp_xclk_cleanup(isp);
1998
1999 __omap3isp_get(isp, false);
2000 isp_detach_iommu(isp);
2001 __omap3isp_put(isp, false);
2002
2003 media_entity_enum_cleanup(&isp->crashed);
2004 v4l2_async_notifier_cleanup(&isp->notifier);
2005
2006 return 0;
2007 }
2008
2009 enum isp_of_phy {
2010 ISP_OF_PHY_PARALLEL = 0,
2011 ISP_OF_PHY_CSIPHY1,
2012 ISP_OF_PHY_CSIPHY2,
2013 };
2014
2015 static int isp_fwnode_parse(struct device *dev,
2016 struct v4l2_fwnode_endpoint *vep,
2017 struct v4l2_async_subdev *asd)
2018 {
2019 struct isp_async_subdev *isd =
2020 container_of(asd, struct isp_async_subdev, asd);
2021 struct isp_bus_cfg *buscfg = &isd->bus;
2022 bool csi1 = false;
2023 unsigned int i;
2024
2025 dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
2026 to_of_node(vep->base.local_fwnode), vep->base.port);
2027
2028 switch (vep->base.port) {
2029 case ISP_OF_PHY_PARALLEL:
2030 buscfg->interface = ISP_INTERFACE_PARALLEL;
2031 buscfg->bus.parallel.data_lane_shift =
2032 vep->bus.parallel.data_shift;
2033 buscfg->bus.parallel.clk_pol =
2034 !!(vep->bus.parallel.flags
2035 & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2036 buscfg->bus.parallel.hs_pol =
2037 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
2038 buscfg->bus.parallel.vs_pol =
2039 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
2040 buscfg->bus.parallel.fld_pol =
2041 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
2042 buscfg->bus.parallel.data_pol =
2043 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2044 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
2045 break;
2046
2047 case ISP_OF_PHY_CSIPHY1:
2048 case ISP_OF_PHY_CSIPHY2:
2049 switch (vep->bus_type) {
2050 case V4L2_MBUS_CCP2:
2051 case V4L2_MBUS_CSI1:
2052 dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
2053 csi1 = true;
2054 break;
2055 case V4L2_MBUS_CSI2:
2056 dev_dbg(dev, "CSI-2 configuration\n");
2057 csi1 = false;
2058 break;
2059 default:
2060 dev_err(dev, "unsupported bus type %u\n",
2061 vep->bus_type);
2062 return -EINVAL;
2063 }
2064
2065 switch (vep->base.port) {
2066 case ISP_OF_PHY_CSIPHY1:
2067 if (csi1)
2068 buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
2069 else
2070 buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
2071 break;
2072 case ISP_OF_PHY_CSIPHY2:
2073 if (csi1)
2074 buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
2075 else
2076 buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
2077 break;
2078 }
2079 if (csi1) {
2080 buscfg->bus.ccp2.lanecfg.clk.pos =
2081 vep->bus.mipi_csi1.clock_lane;
2082 buscfg->bus.ccp2.lanecfg.clk.pol =
2083 vep->bus.mipi_csi1.lane_polarity[0];
2084 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2085 buscfg->bus.ccp2.lanecfg.clk.pol,
2086 buscfg->bus.ccp2.lanecfg.clk.pos);
2087
2088 buscfg->bus.ccp2.lanecfg.data[0].pos =
2089 vep->bus.mipi_csi1.data_lane;
2090 buscfg->bus.ccp2.lanecfg.data[0].pol =
2091 vep->bus.mipi_csi1.lane_polarity[1];
2092
2093 dev_dbg(dev, "data lane polarity %u, pos %u\n",
2094 buscfg->bus.ccp2.lanecfg.data[0].pol,
2095 buscfg->bus.ccp2.lanecfg.data[0].pos);
2096
2097 buscfg->bus.ccp2.strobe_clk_pol =
2098 vep->bus.mipi_csi1.clock_inv;
2099 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
2100 buscfg->bus.ccp2.ccp2_mode =
2101 vep->bus_type == V4L2_MBUS_CCP2;
2102 buscfg->bus.ccp2.vp_clk_pol = 1;
2103
2104 buscfg->bus.ccp2.crc = 1;
2105 } else {
2106 buscfg->bus.csi2.lanecfg.clk.pos =
2107 vep->bus.mipi_csi2.clock_lane;
2108 buscfg->bus.csi2.lanecfg.clk.pol =
2109 vep->bus.mipi_csi2.lane_polarities[0];
2110 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2111 buscfg->bus.csi2.lanecfg.clk.pol,
2112 buscfg->bus.csi2.lanecfg.clk.pos);
2113
2114 buscfg->bus.csi2.num_data_lanes =
2115 vep->bus.mipi_csi2.num_data_lanes;
2116
2117 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2118 buscfg->bus.csi2.lanecfg.data[i].pos =
2119 vep->bus.mipi_csi2.data_lanes[i];
2120 buscfg->bus.csi2.lanecfg.data[i].pol =
2121 vep->bus.mipi_csi2.lane_polarities[i + 1];
2122 dev_dbg(dev,
2123 "data lane %u polarity %u, pos %u\n", i,
2124 buscfg->bus.csi2.lanecfg.data[i].pol,
2125 buscfg->bus.csi2.lanecfg.data[i].pos);
2126 }
2127 /*
2128 * FIXME: now we assume the CRC is always there.
2129 * Implement a way to obtain this information from the
2130 * sensor. Frame descriptors, perhaps?
2131 */
2132 buscfg->bus.csi2.crc = 1;
2133 }
2134 break;
2135
2136 default:
2137 dev_warn(dev, "%pOF: invalid interface %u\n",
2138 to_of_node(vep->base.local_fwnode), vep->base.port);
2139 return -EINVAL;
2140 }
2141
2142 return 0;
2143 }
2144
2145 static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2146 {
2147 struct isp_device *isp = container_of(async, struct isp_device,
2148 notifier);
2149 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2150 struct v4l2_subdev *sd;
2151 int ret;
2152
2153 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2154 if (ret)
2155 return ret;
2156
2157 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
2158 if (sd->notifier != &isp->notifier)
2159 continue;
2160
2161 ret = isp_link_entity(isp, &sd->entity,
2162 v4l2_subdev_to_bus_cfg(sd)->interface);
2163 if (ret < 0)
2164 return ret;
2165 }
2166
2167 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2168 if (ret < 0)
2169 return ret;
2170
2171 return media_device_register(&isp->media_dev);
2172 }
2173
2174 static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2175 .complete = isp_subdev_notifier_complete,
2176 };
2177
2178 /*
2179 * isp_probe - Probe ISP platform device
2180 * @pdev: Pointer to ISP platform device
2181 *
2182 * Returns 0 if successful,
2183 * -ENOMEM if no memory available,
2184 * -ENODEV if no platform device resources found
2185 * or no space for remapping registers,
2186 * -EINVAL if couldn't install ISR,
2187 * or clk_get return error value.
2188 */
2189 static int isp_probe(struct platform_device *pdev)
2190 {
2191 struct isp_device *isp;
2192 struct resource *mem;
2193 int ret;
2194 int i, m;
2195
2196 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
2197 if (!isp) {
2198 dev_err(&pdev->dev, "could not allocate memory\n");
2199 return -ENOMEM;
2200 }
2201
2202 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2203 "ti,phy-type", &isp->phy_type);
2204 if (ret)
2205 return ret;
2206
2207 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2208 "syscon");
2209 if (IS_ERR(isp->syscon))
2210 return PTR_ERR(isp->syscon);
2211
2212 ret = of_property_read_u32_index(pdev->dev.of_node,
2213 "syscon", 1, &isp->syscon_offset);
2214 if (ret)
2215 return ret;
2216
2217 isp->autoidle = autoidle;
2218
2219 mutex_init(&isp->isp_mutex);
2220 spin_lock_init(&isp->stat_lock);
2221
2222 ret = v4l2_async_notifier_parse_fwnode_endpoints(
2223 &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
2224 isp_fwnode_parse);
2225 if (ret < 0)
2226 goto error;
2227
2228 isp->dev = &pdev->dev;
2229 isp->ref_count = 0;
2230
2231 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2232 if (ret)
2233 goto error;
2234
2235 platform_set_drvdata(pdev, isp);
2236
2237 /* Regulators */
2238 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2239 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
2240
2241 /* Clocks
2242 *
2243 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2244 * manually to read the revision before calling __omap3isp_get().
2245 *
2246 * Start by mapping the ISP MMIO area, which is in two pieces.
2247 * The ISP IOMMU is in between. Map both now, and fill in the
2248 * ISP revision specific portions a little later in the
2249 * function.
2250 */
2251 for (i = 0; i < 2; i++) {
2252 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2253
2254 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2255 isp->mmio_base[map_idx] =
2256 devm_ioremap_resource(isp->dev, mem);
2257 if (IS_ERR(isp->mmio_base[map_idx]))
2258 return PTR_ERR(isp->mmio_base[map_idx]);
2259 }
2260
2261 ret = isp_get_clocks(isp);
2262 if (ret < 0)
2263 goto error;
2264
2265 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2266 if (ret < 0)
2267 goto error;
2268
2269 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2270 dev_info(isp->dev, "Revision %d.%d found\n",
2271 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2272
2273 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2274
2275 if (__omap3isp_get(isp, false) == NULL) {
2276 ret = -ENODEV;
2277 goto error;
2278 }
2279
2280 ret = isp_reset(isp);
2281 if (ret < 0)
2282 goto error_isp;
2283
2284 ret = isp_xclk_init(isp);
2285 if (ret < 0)
2286 goto error_isp;
2287
2288 /* Memory resources */
2289 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2290 if (isp->revision == isp_res_maps[m].isp_rev)
2291 break;
2292
2293 if (m == ARRAY_SIZE(isp_res_maps)) {
2294 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2295 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2296 ret = -ENODEV;
2297 goto error_isp;
2298 }
2299
2300 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2301 isp->mmio_base[i] =
2302 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2303
2304 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2305 isp->mmio_base[i] =
2306 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2307 + isp_res_maps[m].offset[i];
2308
2309 isp->mmio_hist_base_phys =
2310 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
2311
2312 /* IOMMU */
2313 ret = isp_attach_iommu(isp);
2314 if (ret < 0) {
2315 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
2316 goto error_isp;
2317 }
2318
2319 /* Interrupt */
2320 ret = platform_get_irq(pdev, 0);
2321 if (ret <= 0) {
2322 dev_err(isp->dev, "No IRQ resource\n");
2323 ret = -ENODEV;
2324 goto error_iommu;
2325 }
2326 isp->irq_num = ret;
2327
2328 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2329 "OMAP3 ISP", isp)) {
2330 dev_err(isp->dev, "Unable to request IRQ\n");
2331 ret = -EINVAL;
2332 goto error_iommu;
2333 }
2334
2335 /* Entities */
2336 ret = isp_initialize_modules(isp);
2337 if (ret < 0)
2338 goto error_iommu;
2339
2340 ret = isp_register_entities(isp);
2341 if (ret < 0)
2342 goto error_modules;
2343
2344 ret = isp_create_links(isp);
2345 if (ret < 0)
2346 goto error_register_entities;
2347
2348 isp->notifier.ops = &isp_subdev_notifier_ops;
2349
2350 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2351 if (ret)
2352 goto error_register_entities;
2353
2354 isp_core_init(isp, 1);
2355 omap3isp_put(isp);
2356
2357 return 0;
2358
2359 error_register_entities:
2360 isp_unregister_entities(isp);
2361 error_modules:
2362 isp_cleanup_modules(isp);
2363 error_iommu:
2364 isp_detach_iommu(isp);
2365 error_isp:
2366 isp_xclk_cleanup(isp);
2367 __omap3isp_put(isp, false);
2368 error:
2369 v4l2_async_notifier_cleanup(&isp->notifier);
2370 mutex_destroy(&isp->isp_mutex);
2371
2372 return ret;
2373 }
2374
2375 static const struct dev_pm_ops omap3isp_pm_ops = {
2376 .prepare = isp_pm_prepare,
2377 .suspend = isp_pm_suspend,
2378 .resume = isp_pm_resume,
2379 .complete = isp_pm_complete,
2380 };
2381
2382 static struct platform_device_id omap3isp_id_table[] = {
2383 { "omap3isp", 0 },
2384 { },
2385 };
2386 MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2387
2388 static const struct of_device_id omap3isp_of_table[] = {
2389 { .compatible = "ti,omap3-isp" },
2390 { },
2391 };
2392 MODULE_DEVICE_TABLE(of, omap3isp_of_table);
2393
2394 static struct platform_driver omap3isp_driver = {
2395 .probe = isp_probe,
2396 .remove = isp_remove,
2397 .id_table = omap3isp_id_table,
2398 .driver = {
2399 .name = "omap3isp",
2400 .pm = &omap3isp_pm_ops,
2401 .of_match_table = omap3isp_of_table,
2402 },
2403 };
2404
2405 module_platform_driver(omap3isp_driver);
2406
2407 MODULE_AUTHOR("Nokia Corporation");
2408 MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2409 MODULE_LICENSE("GPL");
2410 MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
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