drivers/media/platform/omap3isp/ispccp2.c

   1 /*
   2  * ispccp2.c
   3  *
   4  * TI OMAP3 ISP - CCP2 module
   5  *
   6  * Copyright (C) 2010 Nokia Corporation
   7  * Copyright (C) 2010 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 #include "isp.h"
  26 #include "ispreg.h"
  27 #include "ispccp2.h"
  28
  29 /* Number of LCX channels */
  30 #define CCP2_LCx_CHANS_NUM                      3
  31 /* Max/Min size for CCP2 video port */
  32 #define ISPCCP2_DAT_START_MIN                   0
  33 #define ISPCCP2_DAT_START_MAX                   4095
  34 #define ISPCCP2_DAT_SIZE_MIN                    0
  35 #define ISPCCP2_DAT_SIZE_MAX                    4095
  36 #define ISPCCP2_VPCLK_FRACDIV                   65536
  37 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP  0x12
  38 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP        0x16
  39 /* Max/Min size for CCP2 memory channel */
  40 #define ISPCCP2_LCM_HSIZE_COUNT_MIN             16
  41 #define ISPCCP2_LCM_HSIZE_COUNT_MAX             8191
  42 #define ISPCCP2_LCM_HSIZE_SKIP_MIN              0
  43 #define ISPCCP2_LCM_HSIZE_SKIP_MAX              8191
  44 #define ISPCCP2_LCM_VSIZE_MIN                   1
  45 #define ISPCCP2_LCM_VSIZE_MAX                   8191
  46 #define ISPCCP2_LCM_HWORDS_MIN                  1
  47 #define ISPCCP2_LCM_HWORDS_MAX                  4095
  48 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X         5
  49 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL     0
  50 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10     2
  51 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8        2
  52 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10       3
  53 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10       3
  54 #define ISPCCP2_LCM_CTRL_DST_PORT_VP            0
  55 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM           1
  56
  57 /* Set only the required bits */
  58 #define BIT_SET(var, shift, mask, val)                  \
  59         do {                                            \
  60                 var = ((var) & ~((mask) << (shift)))    \
  61                         | ((val) << (shift));           \
  62         } while (0)
  63
  64 /*
  65  * ccp2_print_status - Print current CCP2 module register values.
  66  */
  67 #define CCP2_PRINT_REGISTER(isp, name)\
  68         dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
  69                 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
  70
  71 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
  72 {
  73         struct isp_device *isp = to_isp_device(ccp2);
  74
  75         dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
  76
  77         CCP2_PRINT_REGISTER(isp, SYSCONFIG);
  78         CCP2_PRINT_REGISTER(isp, SYSSTATUS);
  79         CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
  80         CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
  81         CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
  82         CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
  83         CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
  84         CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
  85         CCP2_PRINT_REGISTER(isp, CTRL);
  86         CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
  87         CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
  88         CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
  89         CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
  90         CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
  91         CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
  92         CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
  93         CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
  94         CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
  95         CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
  96         CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
  97         CCP2_PRINT_REGISTER(isp, LCM_CTRL);
  98         CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
  99         CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
 100         CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
 101         CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
 102         CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
 103         CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
 104         CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
 105
 106         dev_dbg(isp->dev, "--------------------------------------------\n");
 107 }
 108
 109 /*
 110  * ccp2_reset - Reset the CCP2
 111  * @ccp2: pointer to ISP CCP2 device
 112  */
 113 static void ccp2_reset(struct isp_ccp2_device *ccp2)
 114 {
 115         struct isp_device *isp = to_isp_device(ccp2);
 116         int i = 0;
 117
 118         /* Reset the CSI1/CCP2B and wait for reset to complete */
 119         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
 120                     ISPCCP2_SYSCONFIG_SOFT_RESET);
 121         while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
 122                  ISPCCP2_SYSSTATUS_RESET_DONE)) {
 123                 udelay(10);
 124                 if (i++ > 10) {  /* try read 10 times */
 125                         dev_warn(isp->dev,
 126                                 "omap3_isp: timeout waiting for ccp2 reset\n");
 127                         break;
 128                 }
 129         }
 130 }
 131
 132 /*
 133  * ccp2_pwr_cfg - Configure the power mode settings
 134  * @ccp2: pointer to ISP CCP2 device
 135  */
 136 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
 137 {
 138         struct isp_device *isp = to_isp_device(ccp2);
 139
 140         isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
 141                         ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
 142                           ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
 143                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
 144 }
 145
 146 /*
 147  * ccp2_if_enable - Enable CCP2 interface.
 148  * @ccp2: pointer to ISP CCP2 device
 149  * @enable: enable/disable flag
 150  */
 151 static int ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
 152 {
 153         struct isp_device *isp = to_isp_device(ccp2);
 154         int ret;
 155         int i;
 156
 157         if (enable && ccp2->vdds_csib) {
 158                 ret = regulator_enable(ccp2->vdds_csib);
 159                 if (ret < 0)
 160                         return ret;
 161         }
 162
 163         /* Enable/Disable all the LCx channels */
 164         for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
 165                 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
 166                                 ISPCCP2_LCx_CTRL_CHAN_EN,
 167                                 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
 168
 169         /* Enable/Disable ccp2 interface in ccp2 mode */
 170         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 171                         ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
 172                         enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
 173
 174         if (!enable && ccp2->vdds_csib)
 175                 regulator_disable(ccp2->vdds_csib);
 176
 177         return 0;
 178 }
 179
 180 /*
 181  * ccp2_mem_enable - Enable CCP2 memory interface.
 182  * @ccp2: pointer to ISP CCP2 device
 183  * @enable: enable/disable flag
 184  */
 185 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
 186 {
 187         struct isp_device *isp = to_isp_device(ccp2);
 188
 189         if (enable)
 190                 ccp2_if_enable(ccp2, 0);
 191
 192         /* Enable/Disable ccp2 interface in ccp2 mode */
 193         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 194                         ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
 195
 196         isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
 197                         ISPCCP2_LCM_CTRL_CHAN_EN,
 198                         enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
 199 }
 200
 201 /*
 202  * ccp2_phyif_config - Initialize CCP2 phy interface config
 203  * @ccp2: Pointer to ISP CCP2 device
 204  * @buscfg: CCP2 platform data
 205  *
 206  * Configure the CCP2 physical interface module from platform data.
 207  *
 208  * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
 209  */
 210 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
 211                              const struct isp_ccp2_cfg *buscfg)
 212 {
 213         struct isp_device *isp = to_isp_device(ccp2);
 214         u32 val;
 215
 216         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
 217                             ISPCCP2_CTRL_MODE;
 218         /* Data/strobe physical layer */
 219         BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
 220                 buscfg->phy_layer);
 221         BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT,
 222                 ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode);
 223         BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
 224                 buscfg->strobe_clk_pol);
 225         BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT,
 226                 ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol);
 227         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 228
 229         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 230         if (!(val & ISPCCP2_CTRL_MODE)) {
 231                 if (buscfg->ccp2_mode == ISP_CCP2_MODE_CCP2)
 232                         dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
 233                 if (buscfg->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
 234                         /* Strobe mode requires CCP2 */
 235                         return -EIO;
 236         }
 237
 238         return 0;
 239 }
 240
 241 /*
 242  * ccp2_vp_config - Initialize CCP2 video port interface.
 243  * @ccp2: Pointer to ISP CCP2 device
 244  * @vpclk_div: Video port divisor
 245  *
 246  * Configure the CCP2 video port with the given clock divisor. The valid divisor
 247  * values depend on the ISP revision:
 248  *
 249  * - revision 1.0 and 2.0       1 to 4
 250  * - revision 15.0              1 to 65536
 251  *
 252  * The exact divisor value used might differ from the requested value, as ISP
 253  * revision 15.0 represent the divisor by 65536 divided by an integer.
 254  */
 255 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
 256                            unsigned int vpclk_div)
 257 {
 258         struct isp_device *isp = to_isp_device(ccp2);
 259         u32 val;
 260
 261         /* ISPCCP2_CTRL Video port */
 262         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 263         val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
 264
 265         if (isp->revision == ISP_REVISION_15_0) {
 266                 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
 267                 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
 268                 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
 269                         ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
 270         } else {
 271                 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
 272                 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
 273                         ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
 274         }
 275
 276         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
 277 }
 278
 279 /*
 280  * ccp2_lcx_config - Initialize CCP2 logical channel interface.
 281  * @ccp2: Pointer to ISP CCP2 device
 282  * @config: Pointer to ISP LCx config structure.
 283  *
 284  * This will analyze the parameters passed by the interface config
 285  * and configure CSI1/CCP2 logical channel
 286  *
 287  */
 288 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
 289                             struct isp_interface_lcx_config *config)
 290 {
 291         struct isp_device *isp = to_isp_device(ccp2);
 292         u32 val, format;
 293
 294         switch (config->format) {
 295         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 296                 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
 297                 break;
 298         case MEDIA_BUS_FMT_SGRBG10_1X10:
 299         default:
 300                 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP;      /* RAW10+VP */
 301                 break;
 302         }
 303         /* ISPCCP2_LCx_CTRL logical channel #0 */
 304         val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
 305                             | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
 306
 307         if (isp->revision == ISP_REVISION_15_0) {
 308                 /* CRC */
 309                 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
 310                         ISPCCP2_LCx_CTRL_CRC_MASK,
 311                         config->crc);
 312                 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
 313                 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
 314                         ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
 315         } else {
 316                 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
 317                         ISPCCP2_LCx_CTRL_CRC_MASK,
 318                         config->crc);
 319
 320                 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
 321                         ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
 322         }
 323         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
 324
 325         /* ISPCCP2_DAT_START for logical channel #0 */
 326         isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
 327                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
 328
 329         /* ISPCCP2_DAT_SIZE for logical channel #0 */
 330         isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
 331                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
 332
 333         /* Enable error IRQs for logical channel #0 */
 334         val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
 335               ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
 336               ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
 337               ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
 338               ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
 339               ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
 340
 341         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
 342         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
 343 }
 344
 345 /*
 346  * ccp2_if_configure - Configure ccp2 with data from sensor
 347  * @ccp2: Pointer to ISP CCP2 device
 348  *
 349  * Return 0 on success or a negative error code
 350  */
 351 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
 352 {
 353         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 354         const struct isp_bus_cfg *buscfg;
 355         struct v4l2_mbus_framefmt *format;
 356         struct media_pad *pad;
 357         struct v4l2_subdev *sensor;
 358         u32 lines = 0;
 359         int ret;
 360
 361         ccp2_pwr_cfg(ccp2);
 362
 363         pad = media_entity_remote_pad(&ccp2->pads[CCP2_PAD_SINK]);
 364         sensor = media_entity_to_v4l2_subdev(pad->entity);
 365         buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
 366
 367         ret = ccp2_phyif_config(ccp2, &buscfg->bus.ccp2);
 368         if (ret < 0)
 369                 return ret;
 370
 371         ccp2_vp_config(ccp2, buscfg->bus.ccp2.vpclk_div + 1);
 372
 373         v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
 374
 375         format = &ccp2->formats[CCP2_PAD_SINK];
 376
 377         ccp2->if_cfg.data_start = lines;
 378         ccp2->if_cfg.crc = buscfg->bus.ccp2.crc;
 379         ccp2->if_cfg.format = format->code;
 380         ccp2->if_cfg.data_size = format->height;
 381
 382         ccp2_lcx_config(ccp2, &ccp2->if_cfg);
 383
 384         return 0;
 385 }
 386
 387 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
 388 {
 389         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 390         struct isp_device *isp = to_isp_device(ccp2);
 391         const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
 392         unsigned long l3_ick = pipe->l3_ick;
 393         struct v4l2_fract *timeperframe;
 394         unsigned int vpclk_div = 2;
 395         unsigned int value;
 396         u64 bound;
 397         u64 area;
 398
 399         /* Compute the minimum clock divisor, based on the pipeline maximum
 400          * data rate. This is an absolute lower bound if we don't want SBL
 401          * overflows, so round the value up.
 402          */
 403         vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
 404                           vpclk_div);
 405
 406         /* Compute the maximum clock divisor, based on the requested frame rate.
 407          * This is a soft lower bound to achieve a frame rate equal or higher
 408          * than the requested value, so round the value down.
 409          */
 410         timeperframe = &pipe->max_timeperframe;
 411
 412         if (timeperframe->numerator) {
 413                 area = ofmt->width * ofmt->height;
 414                 bound = div_u64(area * timeperframe->denominator,
 415                                 timeperframe->numerator);
 416                 value = min_t(u64, bound, l3_ick);
 417                 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
 418         }
 419
 420         dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
 421                 vpclk_div);
 422
 423         return vpclk_div;
 424 }
 425
 426 /*
 427  * ccp2_mem_configure - Initialize CCP2 memory input/output interface
 428  * @ccp2: Pointer to ISP CCP2 device
 429  * @config: Pointer to ISP mem interface config structure
 430  *
 431  * This will analyze the parameters passed by the interface config
 432  * structure, and configure the respective registers for proper
 433  * CSI1/CCP2 memory input.
 434  */
 435 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
 436                                struct isp_interface_mem_config *config)
 437 {
 438         struct isp_device *isp = to_isp_device(ccp2);
 439         u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
 440         u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
 441         unsigned int dpcm_decompress = 0;
 442         u32 val, hwords;
 443
 444         if (sink_pixcode != source_pixcode &&
 445             sink_pixcode == MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
 446                 dpcm_decompress = 1;
 447
 448         ccp2_pwr_cfg(ccp2);
 449
 450         /* Hsize, Skip */
 451         isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
 452                        (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
 453                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
 454
 455         /* Vsize, no. of lines */
 456         isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
 457                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
 458
 459         if (ccp2->video_in.bpl_padding == 0)
 460                 config->src_ofst = 0;
 461         else
 462                 config->src_ofst = ccp2->video_in.bpl_value;
 463
 464         isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
 465                        ISPCCP2_LCM_SRC_OFST);
 466
 467         /* Source and Destination formats */
 468         val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
 469               ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
 470
 471         if (dpcm_decompress) {
 472                 /* source format is RAW8 */
 473                 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
 474                        ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
 475
 476                 /* RAW8 + DPCM10 - simple predictor */
 477                 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
 478
 479                 /* enable source DPCM decompression */
 480                 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
 481                        ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
 482         } else {
 483                 /* source format is RAW10 */
 484                 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
 485                        ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
 486         }
 487
 488         /* Burst size to 32x64 */
 489         val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
 490                ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
 491
 492         isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
 493
 494         /* Prefetch setup */
 495         if (dpcm_decompress)
 496                 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
 497                           config->hsize_count) >> 3;
 498         else
 499                 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
 500                           config->hsize_count) >> 2;
 501
 502         isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
 503                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
 504
 505         /* Video port */
 506         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
 507                     ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
 508         ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
 509
 510         /* Clear LCM interrupts */
 511         isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
 512                        ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
 513                        OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
 514
 515         /* Enable LCM interrupts */
 516         isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
 517                     ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
 518                     ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
 519 }
 520
 521 /*
 522  * ccp2_set_inaddr - Sets memory address of input frame.
 523  * @ccp2: Pointer to ISP CCP2 device
 524  * @addr: 32bit memory address aligned on 32byte boundary.
 525  *
 526  * Configures the memory address from which the input frame is to be read.
 527  */
 528 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
 529 {
 530         struct isp_device *isp = to_isp_device(ccp2);
 531
 532         isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
 533 }
 534
 535 /* -----------------------------------------------------------------------------
 536  * Interrupt handling
 537  */
 538
 539 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
 540 {
 541         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 542         struct isp_buffer *buffer;
 543
 544         buffer = omap3isp_video_buffer_next(&ccp2->video_in);
 545         if (buffer != NULL)
 546                 ccp2_set_inaddr(ccp2, buffer->dma);
 547
 548         pipe->state |= ISP_PIPELINE_IDLE_INPUT;
 549
 550         if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
 551                 if (isp_pipeline_ready(pipe))
 552                         omap3isp_pipeline_set_stream(pipe,
 553                                                 ISP_PIPELINE_STREAM_SINGLESHOT);
 554         }
 555 }
 556
 557 /*
 558  * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
 559  * @ccp2: Pointer to ISP CCP2 device
 560  *
 561  * This will handle the CCP2 interrupts
 562  */
 563 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
 564 {
 565         struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
 566         struct isp_device *isp = to_isp_device(ccp2);
 567         static const u32 ISPCCP2_LC01_ERROR =
 568                 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
 569                 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
 570                 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
 571                 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
 572                 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
 573                 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
 574         u32 lcx_irqstatus, lcm_irqstatus;
 575
 576         /* First clear the interrupts */
 577         lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
 578                                       ISPCCP2_LC01_IRQSTATUS);
 579         isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
 580                        ISPCCP2_LC01_IRQSTATUS);
 581
 582         lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
 583                                       ISPCCP2_LCM_IRQSTATUS);
 584         isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
 585                        ISPCCP2_LCM_IRQSTATUS);
 586         /* Errors */
 587         if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
 588                 pipe->error = true;
 589                 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
 590                 return;
 591         }
 592
 593         if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
 594                 pipe->error = true;
 595                 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
 596         }
 597
 598         if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
 599                 return;
 600
 601         /* Handle queued buffers on frame end interrupts */
 602         if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
 603                 ccp2_isr_buffer(ccp2);
 604 }
 605
 606 /* -----------------------------------------------------------------------------
 607  * V4L2 subdev operations
 608  */
 609
 610 static const unsigned int ccp2_fmts[] = {
 611         MEDIA_BUS_FMT_SGRBG10_1X10,
 612         MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
 613 };
 614
 615 /*
 616  * __ccp2_get_format - helper function for getting ccp2 format
 617  * @ccp2  : Pointer to ISP CCP2 device
 618  * @cfg: V4L2 subdev pad configuration
 619  * @pad   : pad number
 620  * @which : wanted subdev format
 621  * return format structure or NULL on error
 622  */
 623 static struct v4l2_mbus_framefmt *
 624 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_pad_config *cfg,
 625                      unsigned int pad, enum v4l2_subdev_format_whence which)
 626 {
 627         if (which == V4L2_SUBDEV_FORMAT_TRY)
 628                 return v4l2_subdev_get_try_format(&ccp2->subdev, cfg, pad);
 629         else
 630                 return &ccp2->formats[pad];
 631 }
 632
 633 /*
 634  * ccp2_try_format - Handle try format by pad subdev method
 635  * @ccp2  : Pointer to ISP CCP2 device
 636  * @cfg: V4L2 subdev pad configuration
 637  * @pad   : pad num
 638  * @fmt   : pointer to v4l2 mbus format structure
 639  * @which : wanted subdev format
 640  */
 641 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
 642                                struct v4l2_subdev_pad_config *cfg, unsigned int pad,
 643                                struct v4l2_mbus_framefmt *fmt,
 644                                enum v4l2_subdev_format_whence which)
 645 {
 646         struct v4l2_mbus_framefmt *format;
 647
 648         switch (pad) {
 649         case CCP2_PAD_SINK:
 650                 if (fmt->code != MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
 651                         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 652
 653                 if (ccp2->input == CCP2_INPUT_SENSOR) {
 654                         fmt->width = clamp_t(u32, fmt->width,
 655                                              ISPCCP2_DAT_START_MIN,
 656                                              ISPCCP2_DAT_START_MAX);
 657                         fmt->height = clamp_t(u32, fmt->height,
 658                                               ISPCCP2_DAT_SIZE_MIN,
 659                                               ISPCCP2_DAT_SIZE_MAX);
 660                 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
 661                         fmt->width = clamp_t(u32, fmt->width,
 662                                              ISPCCP2_LCM_HSIZE_COUNT_MIN,
 663                                              ISPCCP2_LCM_HSIZE_COUNT_MAX);
 664                         fmt->height = clamp_t(u32, fmt->height,
 665                                               ISPCCP2_LCM_VSIZE_MIN,
 666                                               ISPCCP2_LCM_VSIZE_MAX);
 667                 }
 668                 break;
 669
 670         case CCP2_PAD_SOURCE:
 671                 /* Source format - copy sink format and change pixel code
 672                  * to SGRBG10_1X10 as we don't support CCP2 write to memory.
 673                  * When CCP2 write to memory feature will be added this
 674                  * should be changed properly.
 675                  */
 676                 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK, which);
 677                 memcpy(fmt, format, sizeof(*fmt));
 678                 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 679                 break;
 680         }
 681
 682         fmt->field = V4L2_FIELD_NONE;
 683         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 684 }
 685
 686 /*
 687  * ccp2_enum_mbus_code - Handle pixel format enumeration
 688  * @sd     : pointer to v4l2 subdev structure
 689  * @cfg: V4L2 subdev pad configuration
 690  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 691  * return -EINVAL or zero on success
 692  */
 693 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
 694                                   struct v4l2_subdev_pad_config *cfg,
 695                                   struct v4l2_subdev_mbus_code_enum *code)
 696 {
 697         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 698         struct v4l2_mbus_framefmt *format;
 699
 700         if (code->pad == CCP2_PAD_SINK) {
 701                 if (code->index >= ARRAY_SIZE(ccp2_fmts))
 702                         return -EINVAL;
 703
 704                 code->code = ccp2_fmts[code->index];
 705         } else {
 706                 if (code->index != 0)
 707                         return -EINVAL;
 708
 709                 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK,
 710                                               code->which);
 711                 code->code = format->code;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
 718                                    struct v4l2_subdev_pad_config *cfg,
 719                                    struct v4l2_subdev_frame_size_enum *fse)
 720 {
 721         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 722         struct v4l2_mbus_framefmt format;
 723
 724         if (fse->index != 0)
 725                 return -EINVAL;
 726
 727         format.code = fse->code;
 728         format.width = 1;
 729         format.height = 1;
 730         ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
 731         fse->min_width = format.width;
 732         fse->min_height = format.height;
 733
 734         if (format.code != fse->code)
 735                 return -EINVAL;
 736
 737         format.code = fse->code;
 738         format.width = -1;
 739         format.height = -1;
 740         ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
 741         fse->max_width = format.width;
 742         fse->max_height = format.height;
 743
 744         return 0;
 745 }
 746
 747 /*
 748  * ccp2_get_format - Handle get format by pads subdev method
 749  * @sd    : pointer to v4l2 subdev structure
 750  * @cfg: V4L2 subdev pad configuration
 751  * @fmt   : pointer to v4l2 subdev format structure
 752  * return -EINVAL or zero on success
 753  */
 754 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 755                               struct v4l2_subdev_format *fmt)
 756 {
 757         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 758         struct v4l2_mbus_framefmt *format;
 759
 760         format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
 761         if (format == NULL)
 762                 return -EINVAL;
 763
 764         fmt->format = *format;
 765         return 0;
 766 }
 767
 768 /*
 769  * ccp2_set_format - Handle set format by pads subdev method
 770  * @sd    : pointer to v4l2 subdev structure
 771  * @cfg: V4L2 subdev pad configuration
 772  * @fmt   : pointer to v4l2 subdev format structure
 773  * returns zero
 774  */
 775 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 776                               struct v4l2_subdev_format *fmt)
 777 {
 778         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 779         struct v4l2_mbus_framefmt *format;
 780
 781         format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
 782         if (format == NULL)
 783                 return -EINVAL;
 784
 785         ccp2_try_format(ccp2, cfg, fmt->pad, &fmt->format, fmt->which);
 786         *format = fmt->format;
 787
 788         /* Propagate the format from sink to source */
 789         if (fmt->pad == CCP2_PAD_SINK) {
 790                 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SOURCE,
 791                                            fmt->which);
 792                 *format = fmt->format;
 793                 ccp2_try_format(ccp2, cfg, CCP2_PAD_SOURCE, format, fmt->which);
 794         }
 795
 796         return 0;
 797 }
 798
 799 /*
 800  * ccp2_init_formats - Initialize formats on all pads
 801  * @sd: ISP CCP2 V4L2 subdevice
 802  * @fh: V4L2 subdev file handle
 803  *
 804  * Initialize all pad formats with default values. If fh is not NULL, try
 805  * formats are initialized on the file handle. Otherwise active formats are
 806  * initialized on the device.
 807  */
 808 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 809 {
 810         struct v4l2_subdev_format format;
 811
 812         memset(&format, 0, sizeof(format));
 813         format.pad = CCP2_PAD_SINK;
 814         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
 815         format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
 816         format.format.width = 4096;
 817         format.format.height = 4096;
 818         ccp2_set_format(sd, fh ? fh->pad : NULL, &format);
 819
 820         return 0;
 821 }
 822
 823 /*
 824  * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
 825  * @sd    : pointer to v4l2 subdev structure
 826  * @enable: 1 == Enable, 0 == Disable
 827  * return zero
 828  */
 829 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
 830 {
 831         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 832         struct isp_device *isp = to_isp_device(ccp2);
 833         struct device *dev = to_device(ccp2);
 834         int ret;
 835
 836         if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
 837                 if (enable == ISP_PIPELINE_STREAM_STOPPED)
 838                         return 0;
 839                 atomic_set(&ccp2->stopping, 0);
 840         }
 841
 842         switch (enable) {
 843         case ISP_PIPELINE_STREAM_CONTINUOUS:
 844                 if (ccp2->phy) {
 845                         ret = omap3isp_csiphy_acquire(ccp2->phy, &sd->entity);
 846                         if (ret < 0)
 847                                 return ret;
 848                 }
 849
 850                 ccp2_if_configure(ccp2);
 851                 ccp2_print_status(ccp2);
 852
 853                 /* Enable CSI1/CCP2 interface */
 854                 ret = ccp2_if_enable(ccp2, 1);
 855                 if (ret < 0) {
 856                         if (ccp2->phy)
 857                                 omap3isp_csiphy_release(ccp2->phy);
 858                         return ret;
 859                 }
 860                 break;
 861
 862         case ISP_PIPELINE_STREAM_SINGLESHOT:
 863                 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
 864                         struct v4l2_mbus_framefmt *format;
 865
 866                         format = &ccp2->formats[CCP2_PAD_SINK];
 867
 868                         ccp2->mem_cfg.hsize_count = format->width;
 869                         ccp2->mem_cfg.vsize_count = format->height;
 870                         ccp2->mem_cfg.src_ofst = 0;
 871
 872                         ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
 873                         omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
 874                         ccp2_print_status(ccp2);
 875                 }
 876                 ccp2_mem_enable(ccp2, 1);
 877                 break;
 878
 879         case ISP_PIPELINE_STREAM_STOPPED:
 880                 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
 881                                               &ccp2->stopping))
 882                         dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
 883                 if (ccp2->input == CCP2_INPUT_MEMORY) {
 884                         ccp2_mem_enable(ccp2, 0);
 885                         omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
 886                 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
 887                         /* Disable CSI1/CCP2 interface */
 888                         ccp2_if_enable(ccp2, 0);
 889                         if (ccp2->phy)
 890                                 omap3isp_csiphy_release(ccp2->phy);
 891                 }
 892                 break;
 893         }
 894
 895         ccp2->state = enable;
 896         return 0;
 897 }
 898
 899 /* subdev video operations */
 900 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
 901         .s_stream = ccp2_s_stream,
 902 };
 903
 904 /* subdev pad operations */
 905 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
 906         .enum_mbus_code = ccp2_enum_mbus_code,
 907         .enum_frame_size = ccp2_enum_frame_size,
 908         .get_fmt = ccp2_get_format,
 909         .set_fmt = ccp2_set_format,
 910 };
 911
 912 /* subdev operations */
 913 static const struct v4l2_subdev_ops ccp2_sd_ops = {
 914         .video = &ccp2_sd_video_ops,
 915         .pad = &ccp2_sd_pad_ops,
 916 };
 917
 918 /* subdev internal operations */
 919 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
 920         .open = ccp2_init_formats,
 921 };
 922
 923 /* --------------------------------------------------------------------------
 924  * ISP ccp2 video device node
 925  */
 926
 927 /*
 928  * ccp2_video_queue - Queue video buffer.
 929  * @video : Pointer to isp video structure
 930  * @buffer: Pointer to isp_buffer structure
 931  * return -EIO or zero on success
 932  */
 933 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
 934 {
 935         struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
 936
 937         ccp2_set_inaddr(ccp2, buffer->dma);
 938         return 0;
 939 }
 940
 941 static const struct isp_video_operations ccp2_video_ops = {
 942         .queue = ccp2_video_queue,
 943 };
 944
 945 /* -----------------------------------------------------------------------------
 946  * Media entity operations
 947  */
 948
 949 /*
 950  * ccp2_link_setup - Setup ccp2 connections.
 951  * @entity : Pointer to media entity structure
 952  * @local  : Pointer to local pad array
 953  * @remote : Pointer to remote pad array
 954  * @flags  : Link flags
 955  * return -EINVAL on error or zero on success
 956  */
 957 static int ccp2_link_setup(struct media_entity *entity,
 958                            const struct media_pad *local,
 959                            const struct media_pad *remote, u32 flags)
 960 {
 961         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 962         struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
 963         unsigned int index = local->index;
 964
 965         /* FIXME: this is actually a hack! */
 966         if (is_media_entity_v4l2_subdev(remote->entity))
 967                 index |= 2 << 16;
 968
 969         switch (index) {
 970         case CCP2_PAD_SINK:
 971                 /* read from memory */
 972                 if (flags & MEDIA_LNK_FL_ENABLED) {
 973                         if (ccp2->input == CCP2_INPUT_SENSOR)
 974                                 return -EBUSY;
 975                         ccp2->input = CCP2_INPUT_MEMORY;
 976                 } else {
 977                         if (ccp2->input == CCP2_INPUT_MEMORY)
 978                                 ccp2->input = CCP2_INPUT_NONE;
 979                 }
 980                 break;
 981
 982         case CCP2_PAD_SINK | 2 << 16:
 983                 /* read from sensor/phy */
 984                 if (flags & MEDIA_LNK_FL_ENABLED) {
 985                         if (ccp2->input == CCP2_INPUT_MEMORY)
 986                                 return -EBUSY;
 987                         ccp2->input = CCP2_INPUT_SENSOR;
 988                 } else {
 989                         if (ccp2->input == CCP2_INPUT_SENSOR)
 990                                 ccp2->input = CCP2_INPUT_NONE;
 991                 } break;
 992
 993         case CCP2_PAD_SOURCE | 2 << 16:
 994                 /* write to video port/ccdc */
 995                 if (flags & MEDIA_LNK_FL_ENABLED)
 996                         ccp2->output = CCP2_OUTPUT_CCDC;
 997                 else
 998                         ccp2->output = CCP2_OUTPUT_NONE;
 999                 break;
1000
1001         default:
1002                 return -EINVAL;
1003         }
1004
1005         return 0;
1006 }
1007
1008 /* media operations */
1009 static const struct media_entity_operations ccp2_media_ops = {
1010         .link_setup = ccp2_link_setup,
1011         .link_validate = v4l2_subdev_link_validate,
1012 };
1013
1014 /*
1015  * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1016  * @ccp2: Pointer to ISP CCP2 device
1017  */
1018 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1019 {
1020         v4l2_device_unregister_subdev(&ccp2->subdev);
1021         omap3isp_video_unregister(&ccp2->video_in);
1022 }
1023
1024 /*
1025  * omap3isp_ccp2_register_entities - Register the subdev media entity
1026  * @ccp2: Pointer to ISP CCP2 device
1027  * @vdev: Pointer to v4l device
1028  * return negative error code or zero on success
1029  */
1030
1031 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1032                                     struct v4l2_device *vdev)
1033 {
1034         int ret;
1035
1036         /* Register the subdev and video nodes. */
1037         ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1038         if (ret < 0)
1039                 goto error;
1040
1041         ret = omap3isp_video_register(&ccp2->video_in, vdev);
1042         if (ret < 0)
1043                 goto error;
1044
1045         return 0;
1046
1047 error:
1048         omap3isp_ccp2_unregister_entities(ccp2);
1049         return ret;
1050 }
1051
1052 /* -----------------------------------------------------------------------------
1053  * ISP ccp2 initialisation and cleanup
1054  */
1055
1056 /*
1057  * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1058  * @ccp2: Pointer to ISP CCP2 device
1059  * return negative error code or zero on success
1060  */
1061 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1062 {
1063         struct v4l2_subdev *sd = &ccp2->subdev;
1064         struct media_pad *pads = ccp2->pads;
1065         struct media_entity *me = &sd->entity;
1066         int ret;
1067
1068         ccp2->input = CCP2_INPUT_NONE;
1069         ccp2->output = CCP2_OUTPUT_NONE;
1070
1071         v4l2_subdev_init(sd, &ccp2_sd_ops);
1072         sd->internal_ops = &ccp2_sd_internal_ops;
1073         strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1074         sd->grp_id = 1 << 16;   /* group ID for isp subdevs */
1075         v4l2_set_subdevdata(sd, ccp2);
1076         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1077
1078         pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1079                                     | MEDIA_PAD_FL_MUST_CONNECT;
1080         pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1081
1082         me->ops = &ccp2_media_ops;
1083         ret = media_entity_pads_init(me, CCP2_PADS_NUM, pads);
1084         if (ret < 0)
1085                 return ret;
1086
1087         ccp2_init_formats(sd, NULL);
1088
1089         /*
1090          * The CCP2 has weird line alignment requirements, possibly caused by
1091          * DPCM8 decompression. Line length for data read from memory must be a
1092          * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1093          * is present at end of lines). Additionally, if padding is used, the
1094          * padded line length must be a multiple of 32 bytes. To simplify the
1095          * implementation we use a fixed 32 bytes alignment regardless of the
1096          * input format and width. If strict 128 bits alignment support is
1097          * required ispvideo will need to be made aware of this special dual
1098          * alignment requirements.
1099          */
1100         ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1101         ccp2->video_in.bpl_alignment = 32;
1102         ccp2->video_in.bpl_max = 0xffffffe0;
1103         ccp2->video_in.isp = to_isp_device(ccp2);
1104         ccp2->video_in.ops = &ccp2_video_ops;
1105         ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1106
1107         ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1108         if (ret < 0)
1109                 goto error;
1110
1111         return 0;
1112
1113 error:
1114         media_entity_cleanup(&ccp2->subdev.entity);
1115         return ret;
1116 }
1117
1118 /*
1119  * omap3isp_ccp2_init - CCP2 initialization.
1120  * @isp : Pointer to ISP device
1121  * return negative error code or zero on success
1122  */
1123 int omap3isp_ccp2_init(struct isp_device *isp)
1124 {
1125         struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1126         int ret;
1127
1128         init_waitqueue_head(&ccp2->wait);
1129
1130         /*
1131          * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1132          * complex, which is powered by vdds_csib power rail. Hence the
1133          * request for the regulator.
1134          *
1135          * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1136          * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1137          * configured.
1138          *
1139          * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1140          */
1141         if (isp->revision == ISP_REVISION_2_0) {
1142                 ccp2->vdds_csib = devm_regulator_get(isp->dev, "vdds_csib");
1143                 if (IS_ERR(ccp2->vdds_csib)) {
1144                         if (PTR_ERR(ccp2->vdds_csib) == -EPROBE_DEFER) {
1145                                 dev_dbg(isp->dev,
1146                                         "Can't get regulator vdds_csib, deferring probing\n");
1147                                 return -EPROBE_DEFER;
1148                         }
1149                         dev_dbg(isp->dev,
1150                                 "Could not get regulator vdds_csib\n");
1151                         ccp2->vdds_csib = NULL;
1152                 }
1153                 ccp2->phy = &isp->isp_csiphy2;
1154         } else if (isp->revision == ISP_REVISION_15_0) {
1155                 ccp2->phy = &isp->isp_csiphy1;
1156         }
1157
1158         ret = ccp2_init_entities(ccp2);
1159         if (ret < 0)
1160                 return ret;
1161
1162         ccp2_reset(ccp2);
1163         return 0;
1164 }
1165
1166 /*
1167  * omap3isp_ccp2_cleanup - CCP2 un-initialization
1168  * @isp : Pointer to ISP device
1169  */
1170 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1171 {
1172         struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1173
1174         omap3isp_video_cleanup(&ccp2->video_in);
1175         media_entity_cleanup(&ccp2->subdev.entity);
1176 }