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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / mtd / nand / cafe_nand.c
blob567ff972d5fcef110b71fa45a25d5b630c42136c
1 /*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * The data sheet for this device can be found at:
5 * http://wiki.laptop.org/go/Datasheets
6 *
7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
11 #define DEBUG
12
13 #include <linux/device.h>
14 #undef DEBUG
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/rslib.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <asm/io.h>
26
27 #define CAFE_NAND_CTRL1 0x00
28 #define CAFE_NAND_CTRL2 0x04
29 #define CAFE_NAND_CTRL3 0x08
30 #define CAFE_NAND_STATUS 0x0c
31 #define CAFE_NAND_IRQ 0x10
32 #define CAFE_NAND_IRQ_MASK 0x14
33 #define CAFE_NAND_DATA_LEN 0x18
34 #define CAFE_NAND_ADDR1 0x1c
35 #define CAFE_NAND_ADDR2 0x20
36 #define CAFE_NAND_TIMING1 0x24
37 #define CAFE_NAND_TIMING2 0x28
38 #define CAFE_NAND_TIMING3 0x2c
39 #define CAFE_NAND_NONMEM 0x30
40 #define CAFE_NAND_ECC_RESULT 0x3C
41 #define CAFE_NAND_DMA_CTRL 0x40
42 #define CAFE_NAND_DMA_ADDR0 0x44
43 #define CAFE_NAND_DMA_ADDR1 0x48
44 #define CAFE_NAND_ECC_SYN01 0x50
45 #define CAFE_NAND_ECC_SYN23 0x54
46 #define CAFE_NAND_ECC_SYN45 0x58
47 #define CAFE_NAND_ECC_SYN67 0x5c
48 #define CAFE_NAND_READ_DATA 0x1000
49 #define CAFE_NAND_WRITE_DATA 0x2000
50
51 #define CAFE_GLOBAL_CTRL 0x3004
52 #define CAFE_GLOBAL_IRQ 0x3008
53 #define CAFE_GLOBAL_IRQ_MASK 0x300c
54 #define CAFE_NAND_RESET 0x3034
55
56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57 #define CTRL1_CHIPSELECT (1<<19)
58
59 struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
63 struct rs_control *rs;
64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 dma_addr_t dmaaddr;
71 unsigned char *dmabuf;
72 };
73
74 static int usedma = 1;
75 module_param(usedma, int, 0644);
76
77 static int skipbbt = 0;
78 module_param(skipbbt, int, 0644);
79
80 static int debug = 0;
81 module_param(debug, int, 0644);
82
83 static int regdebug = 0;
84 module_param(regdebug, int, 0644);
85
86 static int checkecc = 1;
87 module_param(checkecc, int, 0644);
88
89 static unsigned int numtimings;
90 static int timing[3];
91 module_param_array(timing, int, &numtimings, 0644);
92
93 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
94
95 /* Hrm. Why isn't this already conditional on something in the struct device? */
96 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
97
98 /* Make it easier to switch to PIO if we need to */
99 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
101
102 static int cafe_device_ready(struct mtd_info *mtd)
103 {
104 struct nand_chip *chip = mtd_to_nand(mtd);
105 struct cafe_priv *cafe = nand_get_controller_data(chip);
106 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
108
109 cafe_writel(cafe, irqs, NAND_IRQ);
110
111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
114
115 return result;
116 }
117
118
119 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
120 {
121 struct nand_chip *chip = mtd_to_nand(mtd);
122 struct cafe_priv *cafe = nand_get_controller_data(chip);
123
124 if (usedma)
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
126 else
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
128
129 cafe->datalen += len;
130
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
132 len, cafe->datalen);
133 }
134
135 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
136 {
137 struct nand_chip *chip = mtd_to_nand(mtd);
138 struct cafe_priv *cafe = nand_get_controller_data(chip);
139
140 if (usedma)
141 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 else
143 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144
145 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
146 len, cafe->datalen);
147 cafe->datalen += len;
148 }
149
150 static uint8_t cafe_read_byte(struct mtd_info *mtd)
151 {
152 struct nand_chip *chip = mtd_to_nand(mtd);
153 struct cafe_priv *cafe = nand_get_controller_data(chip);
154 uint8_t d;
155
156 cafe_read_buf(mtd, &d, 1);
157 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
158
159 return d;
160 }
161
162 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
163 int column, int page_addr)
164 {
165 struct nand_chip *chip = mtd_to_nand(mtd);
166 struct cafe_priv *cafe = nand_get_controller_data(chip);
167 int adrbytes = 0;
168 uint32_t ctl1;
169 uint32_t doneint = 0x80000000;
170
171 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
172 command, column, page_addr);
173
174 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
175 /* Second half of a command we already calculated */
176 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
177 ctl1 = cafe->ctl1;
178 cafe->ctl2 &= ~(1<<30);
179 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
180 cafe->ctl1, cafe->nr_data);
181 goto do_command;
182 }
183 /* Reset ECC engine */
184 cafe_writel(cafe, 0, NAND_CTRL2);
185
186 /* Emulate NAND_CMD_READOOB on large-page chips */
187 if (mtd->writesize > 512 &&
188 command == NAND_CMD_READOOB) {
189 column += mtd->writesize;
190 command = NAND_CMD_READ0;
191 }
192
193 /* FIXME: Do we need to send read command before sending data
194 for small-page chips, to position the buffer correctly? */
195
196 if (column != -1) {
197 cafe_writel(cafe, column, NAND_ADDR1);
198 adrbytes = 2;
199 if (page_addr != -1)
200 goto write_adr2;
201 } else if (page_addr != -1) {
202 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
203 page_addr >>= 16;
204 write_adr2:
205 cafe_writel(cafe, page_addr, NAND_ADDR2);
206 adrbytes += 2;
207 if (mtd->size > mtd->writesize << 16)
208 adrbytes++;
209 }
210
211 cafe->data_pos = cafe->datalen = 0;
212
213 /* Set command valid bit, mask in the chip select bit */
214 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
215
216 /* Set RD or WR bits as appropriate */
217 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
218 ctl1 |= (1<<26); /* rd */
219 /* Always 5 bytes, for now */
220 cafe->datalen = 4;
221 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
222 adrbytes = 1;
223 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
224 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
225 ctl1 |= 1<<26; /* rd */
226 /* For now, assume just read to end of page */
227 cafe->datalen = mtd->writesize + mtd->oobsize - column;
228 } else if (command == NAND_CMD_SEQIN)
229 ctl1 |= 1<<25; /* wr */
230
231 /* Set number of address bytes */
232 if (adrbytes)
233 ctl1 |= ((adrbytes-1)|8) << 27;
234
235 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
236 /* Ignore the first command of a pair; the hardware
237 deals with them both at once, later */
238 cafe->ctl1 = ctl1;
239 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
240 cafe->ctl1, cafe->datalen);
241 return;
242 }
243 /* RNDOUT and READ0 commands need a following byte */
244 if (command == NAND_CMD_RNDOUT)
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
246 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
247 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
248
249 do_command:
250 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
251 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
252
253 /* NB: The datasheet lies -- we really should be subtracting 1 here */
254 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
255 cafe_writel(cafe, 0x90000000, NAND_IRQ);
256 if (usedma && (ctl1 & (3<<25))) {
257 uint32_t dmactl = 0xc0000000 + cafe->datalen;
258 /* If WR or RD bits set, set up DMA */
259 if (ctl1 & (1<<26)) {
260 /* It's a read */
261 dmactl |= (1<<29);
262 /* ... so it's done when the DMA is done, not just
263 the command. */
264 doneint = 0x10000000;
265 }
266 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
267 }
268 cafe->datalen = 0;
269
270 if (unlikely(regdebug)) {
271 int i;
272 printk("About to write command %08x to register 0\n", ctl1);
273 for (i=4; i< 0x5c; i+=4)
274 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
275 }
276
277 cafe_writel(cafe, ctl1, NAND_CTRL1);
278 /* Apply this short delay always to ensure that we do wait tWB in
279 * any case on any machine. */
280 ndelay(100);
281
282 if (1) {
283 int c;
284 uint32_t irqs;
285
286 for (c = 500000; c != 0; c--) {
287 irqs = cafe_readl(cafe, NAND_IRQ);
288 if (irqs & doneint)
289 break;
290 udelay(1);
291 if (!(c % 100000))
292 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
293 cpu_relax();
294 }
295 cafe_writel(cafe, doneint, NAND_IRQ);
296 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
297 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
298 }
299
300 WARN_ON(cafe->ctl2 & (1<<30));
301
302 switch (command) {
303
304 case NAND_CMD_CACHEDPROG:
305 case NAND_CMD_PAGEPROG:
306 case NAND_CMD_ERASE1:
307 case NAND_CMD_ERASE2:
308 case NAND_CMD_SEQIN:
309 case NAND_CMD_RNDIN:
310 case NAND_CMD_STATUS:
311 case NAND_CMD_RNDOUT:
312 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
313 return;
314 }
315 nand_wait_ready(mtd);
316 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
317 }
318
319 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
320 {
321 struct nand_chip *chip = mtd_to_nand(mtd);
322 struct cafe_priv *cafe = nand_get_controller_data(chip);
323
324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
325
326 /* Mask the appropriate bit into the stored value of ctl1
327 which will be used by cafe_nand_cmdfunc() */
328 if (chipnr)
329 cafe->ctl1 |= CTRL1_CHIPSELECT;
330 else
331 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
332 }
333
334 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
335 {
336 struct mtd_info *mtd = id;
337 struct nand_chip *chip = mtd_to_nand(mtd);
338 struct cafe_priv *cafe = nand_get_controller_data(chip);
339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
341 if (!irqs)
342 return IRQ_NONE;
343
344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
345 return IRQ_HANDLED;
346 }
347
348 static void cafe_nand_bug(struct mtd_info *mtd)
349 {
350 BUG();
351 }
352
353 static int cafe_nand_write_oob(struct mtd_info *mtd,
354 struct nand_chip *chip, int page)
355 {
356 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
357 mtd->oobsize);
358 }
359
360 /* Don't use -- use nand_read_oob_std for now */
361 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
362 int page)
363 {
364 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
365 }
366 /**
367 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
368 * @mtd: mtd info structure
369 * @chip: nand chip info structure
370 * @buf: buffer to store read data
371 * @oob_required: caller expects OOB data read to chip->oob_poi
372 *
373 * The hw generator calculates the error syndrome automatically. Therefore
374 * we need a special oob layout and handling.
375 */
376 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
377 uint8_t *buf, int oob_required, int page)
378 {
379 struct cafe_priv *cafe = nand_get_controller_data(chip);
380 unsigned int max_bitflips = 0;
381
382 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
383 cafe_readl(cafe, NAND_ECC_RESULT),
384 cafe_readl(cafe, NAND_ECC_SYN01));
385
386 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
387 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
388
389 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
390 unsigned short syn[8], pat[4];
391 int pos[4];
392 u8 *oob = chip->oob_poi;
393 int i, n;
394
395 for (i=0; i<8; i+=2) {
396 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
397 syn[i] = cafe->rs->index_of[tmp & 0xfff];
398 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
399 }
400
401 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
402 pat);
403
404 for (i = 0; i < n; i++) {
405 int p = pos[i];
406
407 /* The 12-bit symbols are mapped to bytes here */
408
409 if (p > 1374) {
410 /* out of range */
411 n = -1374;
412 } else if (p == 0) {
413 /* high four bits do not correspond to data */
414 if (pat[i] > 0xff)
415 n = -2048;
416 else
417 buf[0] ^= pat[i];
418 } else if (p == 1365) {
419 buf[2047] ^= pat[i] >> 4;
420 oob[0] ^= pat[i] << 4;
421 } else if (p > 1365) {
422 if ((p & 1) == 1) {
423 oob[3*p/2 - 2048] ^= pat[i] >> 4;
424 oob[3*p/2 - 2047] ^= pat[i] << 4;
425 } else {
426 oob[3*p/2 - 2049] ^= pat[i] >> 8;
427 oob[3*p/2 - 2048] ^= pat[i];
428 }
429 } else if ((p & 1) == 1) {
430 buf[3*p/2] ^= pat[i] >> 4;
431 buf[3*p/2 + 1] ^= pat[i] << 4;
432 } else {
433 buf[3*p/2 - 1] ^= pat[i] >> 8;
434 buf[3*p/2] ^= pat[i];
435 }
436 }
437
438 if (n < 0) {
439 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
440 cafe_readl(cafe, NAND_ADDR2) * 2048);
441 for (i = 0; i < 0x5c; i += 4)
442 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
443 mtd->ecc_stats.failed++;
444 } else {
445 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
446 mtd->ecc_stats.corrected += n;
447 max_bitflips = max_t(unsigned int, max_bitflips, n);
448 }
449 }
450
451 return max_bitflips;
452 }
453
454 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section,
455 struct mtd_oob_region *oobregion)
456 {
457 struct nand_chip *chip = mtd_to_nand(mtd);
458
459 if (section)
460 return -ERANGE;
461
462 oobregion->offset = 0;
463 oobregion->length = chip->ecc.total;
464
465 return 0;
466 }
467
468 static int cafe_ooblayout_free(struct mtd_info *mtd, int section,
469 struct mtd_oob_region *oobregion)
470 {
471 struct nand_chip *chip = mtd_to_nand(mtd);
472
473 if (section)
474 return -ERANGE;
475
476 oobregion->offset = chip->ecc.total;
477 oobregion->length = mtd->oobsize - chip->ecc.total;
478
479 return 0;
480 }
481
482 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = {
483 .ecc = cafe_ooblayout_ecc,
484 .free = cafe_ooblayout_free,
485 };
486
487 /* Ick. The BBT code really ought to be able to work this bit out
488 for itself from the above, at least for the 2KiB case */
489 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
490 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
491
492 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
493 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
494
495
496 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
497 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
498 | NAND_BBT_2BIT | NAND_BBT_VERSION,
499 .offs = 14,
500 .len = 4,
501 .veroffs = 18,
502 .maxblocks = 4,
503 .pattern = cafe_bbt_pattern_2048
504 };
505
506 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
507 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
508 | NAND_BBT_2BIT | NAND_BBT_VERSION,
509 .offs = 14,
510 .len = 4,
511 .veroffs = 18,
512 .maxblocks = 4,
513 .pattern = cafe_mirror_pattern_2048
514 };
515
516 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
517 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
518 | NAND_BBT_2BIT | NAND_BBT_VERSION,
519 .offs = 14,
520 .len = 1,
521 .veroffs = 15,
522 .maxblocks = 4,
523 .pattern = cafe_bbt_pattern_512
524 };
525
526 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
527 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
528 | NAND_BBT_2BIT | NAND_BBT_VERSION,
529 .offs = 14,
530 .len = 1,
531 .veroffs = 15,
532 .maxblocks = 4,
533 .pattern = cafe_mirror_pattern_512
534 };
535
536
537 static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
538 struct nand_chip *chip,
539 const uint8_t *buf, int oob_required,
540 int page)
541 {
542 struct cafe_priv *cafe = nand_get_controller_data(chip);
543
544 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
545 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
546
547 /* Set up ECC autogeneration */
548 cafe->ctl2 |= (1<<30);
549
550 return nand_prog_page_end_op(chip);
551 }
552
553 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
554 {
555 return 0;
556 }
557
558 /* F_2[X]/(X**6+X+1) */
559 static unsigned short gf64_mul(u8 a, u8 b)
560 {
561 u8 c;
562 unsigned int i;
563
564 c = 0;
565 for (i = 0; i < 6; i++) {
566 if (a & 1)
567 c ^= b;
568 a >>= 1;
569 b <<= 1;
570 if ((b & 0x40) != 0)
571 b ^= 0x43;
572 }
573
574 return c;
575 }
576
577 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
578 static u16 gf4096_mul(u16 a, u16 b)
579 {
580 u8 ah, al, bh, bl, ch, cl;
581
582 ah = a >> 6;
583 al = a & 0x3f;
584 bh = b >> 6;
585 bl = b & 0x3f;
586
587 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
588 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
589
590 return (ch << 6) ^ cl;
591 }
592
593 static int cafe_mul(int x)
594 {
595 if (x == 0)
596 return 1;
597 return gf4096_mul(x, 0xe01);
598 }
599
600 static int cafe_nand_probe(struct pci_dev *pdev,
601 const struct pci_device_id *ent)
602 {
603 struct mtd_info *mtd;
604 struct cafe_priv *cafe;
605 uint32_t ctrl;
606 int err = 0;
607 int old_dma;
608
609 /* Very old versions shared the same PCI ident for all three
610 functions on the chip. Verify the class too... */
611 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
612 return -ENODEV;
613
614 err = pci_enable_device(pdev);
615 if (err)
616 return err;
617
618 pci_set_master(pdev);
619
620 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
621 if (!cafe)
622 return -ENOMEM;
623
624 mtd = nand_to_mtd(&cafe->nand);
625 mtd->dev.parent = &pdev->dev;
626 nand_set_controller_data(&cafe->nand, cafe);
627
628 cafe->pdev = pdev;
629 cafe->mmio = pci_iomap(pdev, 0, 0);
630 if (!cafe->mmio) {
631 dev_warn(&pdev->dev, "failed to iomap\n");
632 err = -ENOMEM;
633 goto out_free_mtd;
634 }
635
636 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
637 if (!cafe->rs) {
638 err = -ENOMEM;
639 goto out_ior;
640 }
641
642 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
643 cafe->nand.dev_ready = cafe_device_ready;
644 cafe->nand.read_byte = cafe_read_byte;
645 cafe->nand.read_buf = cafe_read_buf;
646 cafe->nand.write_buf = cafe_write_buf;
647 cafe->nand.select_chip = cafe_select_chip;
648 cafe->nand.onfi_set_features = nand_onfi_get_set_features_notsupp;
649 cafe->nand.onfi_get_features = nand_onfi_get_set_features_notsupp;
650
651 cafe->nand.chip_delay = 0;
652
653 /* Enable the following for a flash based bad block table */
654 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
655
656 if (skipbbt) {
657 cafe->nand.options |= NAND_SKIP_BBTSCAN;
658 cafe->nand.block_bad = cafe_nand_block_bad;
659 }
660
661 if (numtimings && numtimings != 3) {
662 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
663 }
664
665 if (numtimings == 3) {
666 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
667 timing[0], timing[1], timing[2]);
668 } else {
669 timing[0] = cafe_readl(cafe, NAND_TIMING1);
670 timing[1] = cafe_readl(cafe, NAND_TIMING2);
671 timing[2] = cafe_readl(cafe, NAND_TIMING3);
672
673 if (timing[0] | timing[1] | timing[2]) {
674 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
675 timing[0], timing[1], timing[2]);
676 } else {
677 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
678 timing[0] = timing[1] = timing[2] = 0xffffffff;
679 }
680 }
681
682 /* Start off by resetting the NAND controller completely */
683 cafe_writel(cafe, 1, NAND_RESET);
684 cafe_writel(cafe, 0, NAND_RESET);
685
686 cafe_writel(cafe, timing[0], NAND_TIMING1);
687 cafe_writel(cafe, timing[1], NAND_TIMING2);
688 cafe_writel(cafe, timing[2], NAND_TIMING3);
689
690 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
691 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
692 "CAFE NAND", mtd);
693 if (err) {
694 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
695 goto out_ior;
696 }
697
698 /* Disable master reset, enable NAND clock */
699 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
700 ctrl &= 0xffffeff0;
701 ctrl |= 0x00007000;
702 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
703 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
704 cafe_writel(cafe, 0, NAND_DMA_CTRL);
705
706 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
707 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
708
709 /* Enable NAND IRQ in global IRQ mask register */
710 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
711 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
712 cafe_readl(cafe, GLOBAL_CTRL),
713 cafe_readl(cafe, GLOBAL_IRQ_MASK));
714
715 /* Do not use the DMA for the nand_scan_ident() */
716 old_dma = usedma;
717 usedma = 0;
718
719 /* Scan to find existence of the device */
720 err = nand_scan_ident(mtd, 2, NULL);
721 if (err)
722 goto out_irq;
723
724 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112,
725 &cafe->dmaaddr, GFP_KERNEL);
726 if (!cafe->dmabuf) {
727 err = -ENOMEM;
728 goto out_irq;
729 }
730
731 /* Set up DMA address */
732 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0);
733 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1);
734
735 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
736 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
737
738 /* Restore the DMA flag */
739 usedma = old_dma;
740
741 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
742 if (mtd->writesize == 2048)
743 cafe->ctl2 |= 1<<29; /* 2KiB page size */
744
745 /* Set up ECC according to the type of chip we found */
746 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops);
747 if (mtd->writesize == 2048) {
748 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
749 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
750 } else if (mtd->writesize == 512) {
751 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
752 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
753 } else {
754 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
755 mtd->writesize);
756 goto out_free_dma;
757 }
758 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
759 cafe->nand.ecc.size = mtd->writesize;
760 cafe->nand.ecc.bytes = 14;
761 cafe->nand.ecc.strength = 4;
762 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
763 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
764 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
765 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
766 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
767 cafe->nand.ecc.read_page = cafe_nand_read_page;
768 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
769
770 err = nand_scan_tail(mtd);
771 if (err)
772 goto out_free_dma;
773
774 pci_set_drvdata(pdev, mtd);
775
776 mtd->name = "cafe_nand";
777 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
778
779 goto out;
780
781 out_free_dma:
782 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
783 out_irq:
784 /* Disable NAND IRQ in global IRQ mask register */
785 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
786 free_irq(pdev->irq, mtd);
787 out_ior:
788 pci_iounmap(pdev, cafe->mmio);
789 out_free_mtd:
790 kfree(cafe);
791 out:
792 return err;
793 }
794
795 static void cafe_nand_remove(struct pci_dev *pdev)
796 {
797 struct mtd_info *mtd = pci_get_drvdata(pdev);
798 struct nand_chip *chip = mtd_to_nand(mtd);
799 struct cafe_priv *cafe = nand_get_controller_data(chip);
800
801 /* Disable NAND IRQ in global IRQ mask register */
802 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
803 free_irq(pdev->irq, mtd);
804 nand_release(mtd);
805 free_rs(cafe->rs);
806 pci_iounmap(pdev, cafe->mmio);
807 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
808 kfree(cafe);
809 }
810
811 static const struct pci_device_id cafe_nand_tbl[] = {
812 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
813 PCI_ANY_ID, PCI_ANY_ID },
814 { }
815 };
816
817 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
818
819 static int cafe_nand_resume(struct pci_dev *pdev)
820 {
821 uint32_t ctrl;
822 struct mtd_info *mtd = pci_get_drvdata(pdev);
823 struct nand_chip *chip = mtd_to_nand(mtd);
824 struct cafe_priv *cafe = nand_get_controller_data(chip);
825
826 /* Start off by resetting the NAND controller completely */
827 cafe_writel(cafe, 1, NAND_RESET);
828 cafe_writel(cafe, 0, NAND_RESET);
829 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
830
831 /* Restore timing configuration */
832 cafe_writel(cafe, timing[0], NAND_TIMING1);
833 cafe_writel(cafe, timing[1], NAND_TIMING2);
834 cafe_writel(cafe, timing[2], NAND_TIMING3);
835
836 /* Disable master reset, enable NAND clock */
837 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
838 ctrl &= 0xffffeff0;
839 ctrl |= 0x00007000;
840 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
841 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
842 cafe_writel(cafe, 0, NAND_DMA_CTRL);
843 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
844 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
845
846 /* Set up DMA address */
847 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
848 if (sizeof(cafe->dmaaddr) > 4)
849 /* Shift in two parts to shut the compiler up */
850 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
851 else
852 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
853
854 /* Enable NAND IRQ in global IRQ mask register */
855 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
856 return 0;
857 }
858
859 static struct pci_driver cafe_nand_pci_driver = {
860 .name = "CAFÉ NAND",
861 .id_table = cafe_nand_tbl,
862 .probe = cafe_nand_probe,
863 .remove = cafe_nand_remove,
864 .resume = cafe_nand_resume,
865 };
866
867 module_pci_driver(cafe_nand_pci_driver);
868
869 MODULE_LICENSE("GPL");
870 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
871 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
CRIS linux kernel tree