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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / mtd / nand / marvell_nand.c
blob2196f2a233d6bc935d31fc3f794ea5f5aa76d621
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Marvell NAND flash controller driver
4 *
5 * Copyright (C) 2017 Marvell
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
7 *
8 */
9
10 #include <linux/module.h>
11 #include <linux/clk.h>
12 #include <linux/mtd/rawnand.h>
13 #include <linux/of_platform.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
19 #include <asm/unaligned.h>
20
21 #include <linux/dmaengine.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dma/pxa-dma.h>
24 #include <linux/platform_data/mtd-nand-pxa3xx.h>
25
26 /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */
27 #define FIFO_DEPTH 8
28 #define FIFO_REP(x) (x / sizeof(u32))
29 #define BCH_SEQ_READS (32 / FIFO_DEPTH)
30 /* NFC does not support transfers of larger chunks at a time */
31 #define MAX_CHUNK_SIZE 2112
32 /* NFCv1 cannot read more that 7 bytes of ID */
33 #define NFCV1_READID_LEN 7
34 /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */
35 #define POLL_PERIOD 0
36 #define POLL_TIMEOUT 100000
37 /* Interrupt maximum wait period in ms */
38 #define IRQ_TIMEOUT 1000
39 /* Latency in clock cycles between SoC pins and NFC logic */
40 #define MIN_RD_DEL_CNT 3
41 /* Maximum number of contiguous address cycles */
42 #define MAX_ADDRESS_CYC_NFCV1 5
43 #define MAX_ADDRESS_CYC_NFCV2 7
44 /* System control registers/bits to enable the NAND controller on some SoCs */
45 #define GENCONF_SOC_DEVICE_MUX 0x208
46 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
47 #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20)
48 #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21)
49 #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25)
50 #define GENCONF_CLK_GATING_CTRL 0x220
51 #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2)
52 #define GENCONF_ND_CLK_CTRL 0x700
53 #define GENCONF_ND_CLK_CTRL_EN BIT(0)
54
55 /* NAND controller data flash control register */
56 #define NDCR 0x00
57 #define NDCR_ALL_INT GENMASK(11, 0)
58 #define NDCR_CS1_CMDDM BIT(7)
59 #define NDCR_CS0_CMDDM BIT(8)
60 #define NDCR_RDYM BIT(11)
61 #define NDCR_ND_ARB_EN BIT(12)
62 #define NDCR_RA_START BIT(15)
63 #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16)
64 #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0)
65 #define NDCR_DWIDTH_M BIT(26)
66 #define NDCR_DWIDTH_C BIT(27)
67 #define NDCR_ND_RUN BIT(28)
68 #define NDCR_DMA_EN BIT(29)
69 #define NDCR_ECC_EN BIT(30)
70 #define NDCR_SPARE_EN BIT(31)
71 #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \
72 NDCR_DWIDTH_M | NDCR_DWIDTH_C))
73
74 /* NAND interface timing parameter 0 register */
75 #define NDTR0 0x04
76 #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0)
77 #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3)
78 #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3)
79 #define NDTR0_SEL_NRE_EDGE BIT(7)
80 #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8)
81 #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11)
82 #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16)
83 #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19)
84 #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22)
85 #define NDTR0_SELCNTR BIT(26)
86 #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27)
87
88 /* NAND interface timing parameter 1 register */
89 #define NDTR1 0x0C
90 #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0)
91 #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4)
92 #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8)
93 #define NDTR1_PRESCALE BIT(14)
94 #define NDTR1_WAIT_MODE BIT(15)
95 #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16)
96
97 /* NAND controller status register */
98 #define NDSR 0x14
99 #define NDSR_WRCMDREQ BIT(0)
100 #define NDSR_RDDREQ BIT(1)
101 #define NDSR_WRDREQ BIT(2)
102 #define NDSR_CORERR BIT(3)
103 #define NDSR_UNCERR BIT(4)
104 #define NDSR_CMDD(cs) BIT(8 - cs)
105 #define NDSR_RDY(rb) BIT(11 + rb)
106 #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F)
107
108 /* NAND ECC control register */
109 #define NDECCCTRL 0x28
110 #define NDECCCTRL_BCH_EN BIT(0)
111
112 /* NAND controller data buffer register */
113 #define NDDB 0x40
114
115 /* NAND controller command buffer 0 register */
116 #define NDCB0 0x48
117 #define NDCB0_CMD1(x) ((x & 0xFF) << 0)
118 #define NDCB0_CMD2(x) ((x & 0xFF) << 8)
119 #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16)
120 #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7)
121 #define NDCB0_DBC BIT(19)
122 #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21)
123 #define NDCB0_CSEL BIT(24)
124 #define NDCB0_RDY_BYP BIT(27)
125 #define NDCB0_LEN_OVRD BIT(28)
126 #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29)
127
128 /* NAND controller command buffer 1 register */
129 #define NDCB1 0x4C
130 #define NDCB1_COLS(x) ((x & 0xFFFF) << 0)
131 #define NDCB1_ADDRS_PAGE(x) (x << 16)
132
133 /* NAND controller command buffer 2 register */
134 #define NDCB2 0x50
135 #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0)
136 #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0)
137
138 /* NAND controller command buffer 3 register */
139 #define NDCB3 0x54
140 #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16)
141 #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24)
142
143 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
144 #define TYPE_READ 0
145 #define TYPE_WRITE 1
146 #define TYPE_ERASE 2
147 #define TYPE_READ_ID 3
148 #define TYPE_STATUS 4
149 #define TYPE_RESET 5
150 #define TYPE_NAKED_CMD 6
151 #define TYPE_NAKED_ADDR 7
152 #define TYPE_MASK 7
153 #define XTYPE_MONOLITHIC_RW 0
154 #define XTYPE_LAST_NAKED_RW 1
155 #define XTYPE_FINAL_COMMAND 3
156 #define XTYPE_READ 4
157 #define XTYPE_WRITE_DISPATCH 4
158 #define XTYPE_NAKED_RW 5
159 #define XTYPE_COMMAND_DISPATCH 6
160 #define XTYPE_MASK 7
161
162 /**
163 * Marvell ECC engine works differently than the others, in order to limit the
164 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
165 * per subpage, and depending on a the desired strength needed by the NAND chip,
166 * a particular layout mixing data/spare/ecc is defined, with a possible last
167 * chunk smaller that the others.
168 *
169 * @writesize: Full page size on which the layout applies
170 * @chunk: Desired ECC chunk size on which the layout applies
171 * @strength: Desired ECC strength (per chunk size bytes) on which the
172 * layout applies
173 * @nchunks: Total number of chunks
174 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
175 * repetitions of the pattern:
176 * (data_bytes + spare_bytes + ecc_bytes).
177 * @data_bytes: Number of data bytes per chunk
178 * @spare_bytes: Number of spare bytes per chunk
179 * @ecc_bytes: Number of ecc bytes per chunk
180 * @last_data_bytes: Number of data bytes in the last chunk
181 * @last_spare_bytes: Number of spare bytes in the last chunk
182 * @last_ecc_bytes: Number of ecc bytes in the last chunk
183 */
184 struct marvell_hw_ecc_layout {
185 /* Constraints */
186 int writesize;
187 int chunk;
188 int strength;
189 /* Corresponding layout */
190 int nchunks;
191 int full_chunk_cnt;
192 int data_bytes;
193 int spare_bytes;
194 int ecc_bytes;
195 int last_data_bytes;
196 int last_spare_bytes;
197 int last_ecc_bytes;
198 };
199
200 #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \
201 { \
202 .writesize = ws, \
203 .chunk = dc, \
204 .strength = ds, \
205 .nchunks = nc, \
206 .full_chunk_cnt = fcc, \
207 .data_bytes = db, \
208 .spare_bytes = sb, \
209 .ecc_bytes = eb, \
210 .last_data_bytes = ldb, \
211 .last_spare_bytes = lsb, \
212 .last_ecc_bytes = leb, \
213 }
214
215 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
216 static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
217 MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
218 MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
219 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
220 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
221 MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30),
222 };
223
224 /**
225 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
226 * is made by a field in NDCB0 register, and in another field in NDCB2 register.
227 * The datasheet describes the logic with an error: ADDR5 field is once
228 * declared at the beginning of NDCB2, and another time at its end. Because the
229 * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical
230 * to use the last bit of this field instead of the first ones.
231 *
232 * @cs: Wanted CE lane.
233 * @ndcb0_csel: Value of the NDCB0 register with or without the flag
234 * selecting the wanted CE lane. This is set once when
235 * the Device Tree is probed.
236 * @rb: Ready/Busy pin for the flash chip
237 */
238 struct marvell_nand_chip_sel {
239 unsigned int cs;
240 u32 ndcb0_csel;
241 unsigned int rb;
242 };
243
244 /**
245 * NAND chip structure: stores NAND chip device related information
246 *
247 * @chip: Base NAND chip structure
248 * @node: Used to store NAND chips into a list
249 * @layout NAND layout when using hardware ECC
250 * @ndcr: Controller register value for this NAND chip
251 * @ndtr0: Timing registers 0 value for this NAND chip
252 * @ndtr1: Timing registers 1 value for this NAND chip
253 * @selected_die: Current active CS
254 * @nsels: Number of CS lines required by the NAND chip
255 * @sels: Array of CS lines descriptions
256 */
257 struct marvell_nand_chip {
258 struct nand_chip chip;
259 struct list_head node;
260 const struct marvell_hw_ecc_layout *layout;
261 u32 ndcr;
262 u32 ndtr0;
263 u32 ndtr1;
264 int addr_cyc;
265 int selected_die;
266 unsigned int nsels;
267 struct marvell_nand_chip_sel sels[0];
268 };
269
270 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
271 {
272 return container_of(chip, struct marvell_nand_chip, chip);
273 }
274
275 static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
276 *nand)
277 {
278 return &nand->sels[nand->selected_die];
279 }
280
281 /**
282 * NAND controller capabilities for distinction between compatible strings
283 *
284 * @max_cs_nb: Number of Chip Select lines available
285 * @max_rb_nb: Number of Ready/Busy lines available
286 * @need_system_controller: Indicates if the SoC needs to have access to the
287 * system controller (ie. to enable the NAND controller)
288 * @legacy_of_bindings: Indicates if DT parsing must be done using the old
289 * fashion way
290 * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie.
291 * BCH error detection and correction algorithm,
292 * NDCB3 register has been added
293 * @use_dma: Use dma for data transfers
294 */
295 struct marvell_nfc_caps {
296 unsigned int max_cs_nb;
297 unsigned int max_rb_nb;
298 bool need_system_controller;
299 bool legacy_of_bindings;
300 bool is_nfcv2;
301 bool use_dma;
302 };
303
304 /**
305 * NAND controller structure: stores Marvell NAND controller information
306 *
307 * @controller: Base controller structure
308 * @dev: Parent device (used to print error messages)
309 * @regs: NAND controller registers
310 * @ecc_clk: ECC block clock, two times the NAND controller clock
311 * @complete: Completion object to wait for NAND controller events
312 * @assigned_cs: Bitmask describing already assigned CS lines
313 * @chips: List containing all the NAND chips attached to
314 * this NAND controller
315 * @caps: NAND controller capabilities for each compatible string
316 * @dma_chan: DMA channel (NFCv1 only)
317 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
318 */
319 struct marvell_nfc {
320 struct nand_hw_control controller;
321 struct device *dev;
322 void __iomem *regs;
323 struct clk *ecc_clk;
324 struct completion complete;
325 unsigned long assigned_cs;
326 struct list_head chips;
327 struct nand_chip *selected_chip;
328 const struct marvell_nfc_caps *caps;
329
330 /* DMA (NFCv1 only) */
331 bool use_dma;
332 struct dma_chan *dma_chan;
333 u8 *dma_buf;
334 };
335
336 static inline struct marvell_nfc *to_marvell_nfc(struct nand_hw_control *ctrl)
337 {
338 return container_of(ctrl, struct marvell_nfc, controller);
339 }
340
341 /**
342 * NAND controller timings expressed in NAND Controller clock cycles
343 *
344 * @tRP: ND_nRE pulse width
345 * @tRH: ND_nRE high duration
346 * @tWP: ND_nWE pulse time
347 * @tWH: ND_nWE high duration
348 * @tCS: Enable signal setup time
349 * @tCH: Enable signal hold time
350 * @tADL: Address to write data delay
351 * @tAR: ND_ALE low to ND_nRE low delay
352 * @tWHR: ND_nWE high to ND_nRE low for status read
353 * @tRHW: ND_nRE high duration, read to write delay
354 * @tR: ND_nWE high to ND_nRE low for read
355 */
356 struct marvell_nfc_timings {
357 /* NDTR0 fields */
358 unsigned int tRP;
359 unsigned int tRH;
360 unsigned int tWP;
361 unsigned int tWH;
362 unsigned int tCS;
363 unsigned int tCH;
364 unsigned int tADL;
365 /* NDTR1 fields */
366 unsigned int tAR;
367 unsigned int tWHR;
368 unsigned int tRHW;
369 unsigned int tR;
370 };
371
372 /**
373 * Derives a duration in numbers of clock cycles.
374 *
375 * @ps: Duration in pico-seconds
376 * @period_ns: Clock period in nano-seconds
377 *
378 * Convert the duration in nano-seconds, then divide by the period and
379 * return the number of clock periods.
380 */
381 #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
382
383 /**
384 * NAND driver structure filled during the parsing of the ->exec_op() subop
385 * subset of instructions.
386 *
387 * @ndcb: Array of values written to NDCBx registers
388 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle
389 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
390 * @rdy_delay_ns: Optional delay after waiting for the RB pin
391 * @data_delay_ns: Optional delay after the data xfer
392 * @data_instr_idx: Index of the data instruction in the subop
393 * @data_instr: Pointer to the data instruction in the subop
394 */
395 struct marvell_nfc_op {
396 u32 ndcb[4];
397 unsigned int cle_ale_delay_ns;
398 unsigned int rdy_timeout_ms;
399 unsigned int rdy_delay_ns;
400 unsigned int data_delay_ns;
401 unsigned int data_instr_idx;
402 const struct nand_op_instr *data_instr;
403 };
404
405 /*
406 * Internal helper to conditionnally apply a delay (from the above structure,
407 * most of the time).
408 */
409 static void cond_delay(unsigned int ns)
410 {
411 if (!ns)
412 return;
413
414 if (ns < 10000)
415 ndelay(ns);
416 else
417 udelay(DIV_ROUND_UP(ns, 1000));
418 }
419
420 /*
421 * The controller has many flags that could generate interrupts, most of them
422 * are disabled and polling is used. For the very slow signals, using interrupts
423 * may relax the CPU charge.
424 */
425 static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask)
426 {
427 u32 reg;
428
429 /* Writing 1 disables the interrupt */
430 reg = readl_relaxed(nfc->regs + NDCR);
431 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
432 }
433
434 static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask)
435 {
436 u32 reg;
437
438 /* Writing 0 enables the interrupt */
439 reg = readl_relaxed(nfc->regs + NDCR);
440 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
441 }
442
443 static void marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask)
444 {
445 writel_relaxed(int_mask, nfc->regs + NDSR);
446 }
447
448 static void marvell_nfc_force_byte_access(struct nand_chip *chip,
449 bool force_8bit)
450 {
451 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
452 u32 ndcr;
453
454 /*
455 * Callers of this function do not verify if the NAND is using a 16-bit
456 * an 8-bit bus for normal operations, so we need to take care of that
457 * here by leaving the configuration unchanged if the NAND does not have
458 * the NAND_BUSWIDTH_16 flag set.
459 */
460 if (!(chip->options & NAND_BUSWIDTH_16))
461 return;
462
463 ndcr = readl_relaxed(nfc->regs + NDCR);
464
465 if (force_8bit)
466 ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C);
467 else
468 ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
469
470 writel_relaxed(ndcr, nfc->regs + NDCR);
471 }
472
473 static int marvell_nfc_wait_ndrun(struct nand_chip *chip)
474 {
475 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
476 u32 val;
477 int ret;
478
479 /*
480 * The command is being processed, wait for the ND_RUN bit to be
481 * cleared by the NFC. If not, we must clear it by hand.
482 */
483 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
484 (val & NDCR_ND_RUN) == 0,
485 POLL_PERIOD, POLL_TIMEOUT);
486 if (ret) {
487 dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
488 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
489 nfc->regs + NDCR);
490 return ret;
491 }
492
493 return 0;
494 }
495
496 /*
497 * Any time a command has to be sent to the controller, the following sequence
498 * has to be followed:
499 * - call marvell_nfc_prepare_cmd()
500 * -> activate the ND_RUN bit that will kind of 'start a job'
501 * -> wait the signal indicating the NFC is waiting for a command
502 * - send the command (cmd and address cycles)
503 * - enventually send or receive the data
504 * - call marvell_nfc_end_cmd() with the corresponding flag
505 * -> wait the flag to be triggered or cancel the job with a timeout
506 *
507 * The following helpers are here to factorize the code a bit so that
508 * specialized functions responsible for executing the actual NAND
509 * operations do not have to replicate the same code blocks.
510 */
511 static int marvell_nfc_prepare_cmd(struct nand_chip *chip)
512 {
513 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
514 u32 ndcr, val;
515 int ret;
516
517 /* Poll ND_RUN and clear NDSR before issuing any command */
518 ret = marvell_nfc_wait_ndrun(chip);
519 if (ret) {
520 dev_err(nfc->dev, "Last operation did not succeed\n");
521 return ret;
522 }
523
524 ndcr = readl_relaxed(nfc->regs + NDCR);
525 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
526
527 /* Assert ND_RUN bit and wait the NFC to be ready */
528 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
529 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
530 val & NDSR_WRCMDREQ,
531 POLL_PERIOD, POLL_TIMEOUT);
532 if (ret) {
533 dev_err(nfc->dev, "Timeout on WRCMDRE\n");
534 return -ETIMEDOUT;
535 }
536
537 /* Command may be written, clear WRCMDREQ status bit */
538 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
539
540 return 0;
541 }
542
543 static void marvell_nfc_send_cmd(struct nand_chip *chip,
544 struct marvell_nfc_op *nfc_op)
545 {
546 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
547 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
548
549 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n"
550 "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n",
551 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
552 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]);
553
554 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
555 nfc->regs + NDCB0);
556 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
557 writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
558
559 /*
560 * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7
561 * fields are used (only available on NFCv2).
562 */
563 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD ||
564 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) {
565 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2))
566 writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
567 }
568 }
569
570 static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag,
571 const char *label)
572 {
573 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
574 u32 val;
575 int ret;
576
577 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
578 val & flag,
579 POLL_PERIOD, POLL_TIMEOUT);
580
581 if (ret) {
582 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n",
583 label, val);
584 if (nfc->dma_chan)
585 dmaengine_terminate_all(nfc->dma_chan);
586 return ret;
587 }
588
589 /*
590 * DMA function uses this helper to poll on CMDD bits without wanting
591 * them to be cleared.
592 */
593 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
594 return 0;
595
596 writel_relaxed(flag, nfc->regs + NDSR);
597
598 return 0;
599 }
600
601 static int marvell_nfc_wait_cmdd(struct nand_chip *chip)
602 {
603 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
604 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel);
605
606 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
607 }
608
609 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
610 {
611 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
612 int ret;
613
614 /* Timeout is expressed in ms */
615 if (!timeout_ms)
616 timeout_ms = IRQ_TIMEOUT;
617
618 init_completion(&nfc->complete);
619
620 marvell_nfc_enable_int(nfc, NDCR_RDYM);
621 ret = wait_for_completion_timeout(&nfc->complete,
622 msecs_to_jiffies(timeout_ms));
623 marvell_nfc_disable_int(nfc, NDCR_RDYM);
624 marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
625 if (!ret) {
626 dev_err(nfc->dev, "Timeout waiting for RB signal\n");
627 return -ETIMEDOUT;
628 }
629
630 return 0;
631 }
632
633 static void marvell_nfc_select_chip(struct mtd_info *mtd, int die_nr)
634 {
635 struct nand_chip *chip = mtd_to_nand(mtd);
636 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
637 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
638 u32 ndcr_generic;
639
640 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
641 return;
642
643 if (die_nr < 0 || die_nr >= marvell_nand->nsels) {
644 nfc->selected_chip = NULL;
645 marvell_nand->selected_die = -1;
646 return;
647 }
648
649 /*
650 * Do not change the timing registers when using the DT property
651 * marvell,nand-keep-config; in that case ->ndtr0 and ->ndtr1 from the
652 * marvell_nand structure are supposedly empty.
653 */
654 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
655 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
656
657 /*
658 * Reset the NDCR register to a clean state for this particular chip,
659 * also clear ND_RUN bit.
660 */
661 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
662 NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN;
663 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
664
665 /* Also reset the interrupt status register */
666 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
667
668 nfc->selected_chip = chip;
669 marvell_nand->selected_die = die_nr;
670 }
671
672 static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
673 {
674 struct marvell_nfc *nfc = dev_id;
675 u32 st = readl_relaxed(nfc->regs + NDSR);
676 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
677
678 /*
679 * RDY interrupt mask is one bit in NDCR while there are two status
680 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
681 */
682 if (st & NDSR_RDY(1))
683 st |= NDSR_RDY(0);
684
685 if (!(st & ien))
686 return IRQ_NONE;
687
688 marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
689
690 if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ)))
691 complete(&nfc->complete);
692
693 return IRQ_HANDLED;
694 }
695
696 /* HW ECC related functions */
697 static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
698 {
699 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
700 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
701
702 if (!(ndcr & NDCR_ECC_EN)) {
703 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
704
705 /*
706 * When enabling BCH, set threshold to 0 to always know the
707 * number of corrected bitflips.
708 */
709 if (chip->ecc.algo == NAND_ECC_BCH)
710 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
711 }
712 }
713
714 static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
715 {
716 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
717 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
718
719 if (ndcr & NDCR_ECC_EN) {
720 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
721 if (chip->ecc.algo == NAND_ECC_BCH)
722 writel_relaxed(0, nfc->regs + NDECCCTRL);
723 }
724 }
725
726 /* DMA related helpers */
727 static void marvell_nfc_enable_dma(struct marvell_nfc *nfc)
728 {
729 u32 reg;
730
731 reg = readl_relaxed(nfc->regs + NDCR);
732 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
733 }
734
735 static void marvell_nfc_disable_dma(struct marvell_nfc *nfc)
736 {
737 u32 reg;
738
739 reg = readl_relaxed(nfc->regs + NDCR);
740 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
741 }
742
743 /* Read/write PIO/DMA accessors */
744 static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc,
745 enum dma_data_direction direction,
746 unsigned int len)
747 {
748 unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE);
749 struct dma_async_tx_descriptor *tx;
750 struct scatterlist sg;
751 dma_cookie_t cookie;
752 int ret;
753
754 marvell_nfc_enable_dma(nfc);
755 /* Prepare the DMA transfer */
756 sg_init_one(&sg, nfc->dma_buf, dma_len);
757 dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
758 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1,
759 direction == DMA_FROM_DEVICE ?
760 DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
761 DMA_PREP_INTERRUPT);
762 if (!tx) {
763 dev_err(nfc->dev, "Could not prepare DMA S/G list\n");
764 return -ENXIO;
765 }
766
767 /* Do the task and wait for it to finish */
768 cookie = dmaengine_submit(tx);
769 ret = dma_submit_error(cookie);
770 if (ret)
771 return -EIO;
772
773 dma_async_issue_pending(nfc->dma_chan);
774 ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
775 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
776 marvell_nfc_disable_dma(nfc);
777 if (ret) {
778 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n",
779 dmaengine_tx_status(nfc->dma_chan, cookie, NULL));
780 dmaengine_terminate_all(nfc->dma_chan);
781 return -ETIMEDOUT;
782 }
783
784 return 0;
785 }
786
787 static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
788 unsigned int len)
789 {
790 unsigned int last_len = len % FIFO_DEPTH;
791 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
792 int i;
793
794 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
795 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
796
797 if (last_len) {
798 u8 tmp_buf[FIFO_DEPTH];
799
800 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
801 memcpy(in + last_full_offset, tmp_buf, last_len);
802 }
803
804 return 0;
805 }
806
807 static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out,
808 unsigned int len)
809 {
810 unsigned int last_len = len % FIFO_DEPTH;
811 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
812 int i;
813
814 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
815 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH));
816
817 if (last_len) {
818 u8 tmp_buf[FIFO_DEPTH];
819
820 memcpy(tmp_buf, out + last_full_offset, last_len);
821 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
822 }
823
824 return 0;
825 }
826
827 static void marvell_nfc_check_empty_chunk(struct nand_chip *chip,
828 u8 *data, int data_len,
829 u8 *spare, int spare_len,
830 u8 *ecc, int ecc_len,
831 unsigned int *max_bitflips)
832 {
833 struct mtd_info *mtd = nand_to_mtd(chip);
834 int bf;
835
836 /*
837 * Blank pages (all 0xFF) that have not been written may be recognized
838 * as bad if bitflips occur, so whenever an uncorrectable error occurs,
839 * check if the entire page (with ECC bytes) is actually blank or not.
840 */
841 if (!data)
842 data_len = 0;
843 if (!spare)
844 spare_len = 0;
845 if (!ecc)
846 ecc_len = 0;
847
848 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
849 spare, spare_len, chip->ecc.strength);
850 if (bf < 0) {
851 mtd->ecc_stats.failed++;
852 return;
853 }
854
855 /* Update the stats and max_bitflips */
856 mtd->ecc_stats.corrected += bf;
857 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
858 }
859
860 /*
861 * Check a chunk is correct or not according to hardware ECC engine.
862 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
863 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
864 * value indicating that a check on the emptyness of the subpage must be
865 * performed before declaring the subpage corrupted.
866 */
867 static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip,
868 unsigned int *max_bitflips)
869 {
870 struct mtd_info *mtd = nand_to_mtd(chip);
871 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
872 int bf = 0;
873 u32 ndsr;
874
875 ndsr = readl_relaxed(nfc->regs + NDSR);
876
877 /* Check uncorrectable error flag */
878 if (ndsr & NDSR_UNCERR) {
879 writel_relaxed(ndsr, nfc->regs + NDSR);
880
881 /*
882 * Do not increment ->ecc_stats.failed now, instead, return a
883 * non-zero value to indicate that this chunk was apparently
884 * bad, and it should be check to see if it empty or not. If
885 * the chunk (with ECC bytes) is not declared empty, the calling
886 * function must increment the failure count.
887 */
888 return -EBADMSG;
889 }
890
891 /* Check correctable error flag */
892 if (ndsr & NDSR_CORERR) {
893 writel_relaxed(ndsr, nfc->regs + NDSR);
894
895 if (chip->ecc.algo == NAND_ECC_BCH)
896 bf = NDSR_ERRCNT(ndsr);
897 else
898 bf = 1;
899 }
900
901 /* Update the stats and max_bitflips */
902 mtd->ecc_stats.corrected += bf;
903 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
904
905 return 0;
906 }
907
908 /* Hamming read helpers */
909 static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip,
910 u8 *data_buf, u8 *oob_buf,
911 bool raw, int page)
912 {
913 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
914 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
915 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
916 struct marvell_nfc_op nfc_op = {
917 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
918 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
919 NDCB0_DBC |
920 NDCB0_CMD1(NAND_CMD_READ0) |
921 NDCB0_CMD2(NAND_CMD_READSTART),
922 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
923 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
924 };
925 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
926 int ret;
927
928 /* NFCv2 needs more information about the operation being executed */
929 if (nfc->caps->is_nfcv2)
930 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
931
932 ret = marvell_nfc_prepare_cmd(chip);
933 if (ret)
934 return ret;
935
936 marvell_nfc_send_cmd(chip, &nfc_op);
937 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
938 "RDDREQ while draining FIFO (data/oob)");
939 if (ret)
940 return ret;
941
942 /*
943 * Read the page then the OOB area. Unlike what is shown in current
944 * documentation, spare bytes are protected by the ECC engine, and must
945 * be at the beginning of the OOB area or running this driver on legacy
946 * systems will prevent the discovery of the BBM/BBT.
947 */
948 if (nfc->use_dma) {
949 marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE,
950 lt->data_bytes + oob_bytes);
951 memcpy(data_buf, nfc->dma_buf, lt->data_bytes);
952 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes);
953 } else {
954 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes);
955 marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes);
956 }
957
958 ret = marvell_nfc_wait_cmdd(chip);
959
960 return ret;
961 }
962
963 static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct mtd_info *mtd,
964 struct nand_chip *chip, u8 *buf,
965 int oob_required, int page)
966 {
967 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
968 true, page);
969 }
970
971 static int marvell_nfc_hw_ecc_hmg_read_page(struct mtd_info *mtd,
972 struct nand_chip *chip,
973 u8 *buf, int oob_required,
974 int page)
975 {
976 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
977 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
978 int max_bitflips = 0, ret;
979 u8 *raw_buf;
980
981 marvell_nfc_enable_hw_ecc(chip);
982 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
983 page);
984 ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
985 marvell_nfc_disable_hw_ecc(chip);
986
987 if (!ret)
988 return max_bitflips;
989
990 /*
991 * When ECC failures are detected, check if the full page has been
992 * written or not. Ignore the failure if it is actually empty.
993 */
994 raw_buf = kmalloc(full_sz, GFP_KERNEL);
995 if (!raw_buf)
996 return -ENOMEM;
997
998 marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf +
999 lt->data_bytes, true, page);
1000 marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0,
1001 &max_bitflips);
1002 kfree(raw_buf);
1003
1004 return max_bitflips;
1005 }
1006
1007 /*
1008 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1009 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1010 * also stands for ->read_oob().
1011 */
1012 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct mtd_info *mtd,
1013 struct nand_chip *chip, int page)
1014 {
1015 /* Invalidate page cache */
1016 chip->pagebuf = -1;
1017
1018 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf,
1019 chip->oob_poi, true, page);
1020 }
1021
1022 /* Hamming write helpers */
1023 static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
1024 const u8 *data_buf,
1025 const u8 *oob_buf, bool raw,
1026 int page)
1027 {
1028 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1029 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1030 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1031 struct marvell_nfc_op nfc_op = {
1032 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) |
1033 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1034 NDCB0_CMD1(NAND_CMD_SEQIN) |
1035 NDCB0_CMD2(NAND_CMD_PAGEPROG) |
1036 NDCB0_DBC,
1037 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1038 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1039 };
1040 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1041 int ret;
1042
1043 /* NFCv2 needs more information about the operation being executed */
1044 if (nfc->caps->is_nfcv2)
1045 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1046
1047 ret = marvell_nfc_prepare_cmd(chip);
1048 if (ret)
1049 return ret;
1050
1051 marvell_nfc_send_cmd(chip, &nfc_op);
1052 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1053 "WRDREQ while loading FIFO (data)");
1054 if (ret)
1055 return ret;
1056
1057 /* Write the page then the OOB area */
1058 if (nfc->use_dma) {
1059 memcpy(nfc->dma_buf, data_buf, lt->data_bytes);
1060 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes);
1061 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes +
1062 lt->ecc_bytes + lt->spare_bytes);
1063 } else {
1064 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes);
1065 marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes);
1066 }
1067
1068 ret = marvell_nfc_wait_cmdd(chip);
1069 if (ret)
1070 return ret;
1071
1072 ret = marvell_nfc_wait_op(chip,
1073 chip->data_interface.timings.sdr.tPROG_max);
1074 return ret;
1075 }
1076
1077 static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct mtd_info *mtd,
1078 struct nand_chip *chip,
1079 const u8 *buf,
1080 int oob_required, int page)
1081 {
1082 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1083 true, page);
1084 }
1085
1086 static int marvell_nfc_hw_ecc_hmg_write_page(struct mtd_info *mtd,
1087 struct nand_chip *chip,
1088 const u8 *buf,
1089 int oob_required, int page)
1090 {
1091 int ret;
1092
1093 marvell_nfc_enable_hw_ecc(chip);
1094 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1095 false, page);
1096 marvell_nfc_disable_hw_ecc(chip);
1097
1098 return ret;
1099 }
1100
1101 /*
1102 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1103 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1104 * also stands for ->write_oob().
1105 */
1106 static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct mtd_info *mtd,
1107 struct nand_chip *chip,
1108 int page)
1109 {
1110 /* Invalidate page cache */
1111 chip->pagebuf = -1;
1112
1113 memset(chip->data_buf, 0xFF, mtd->writesize);
1114
1115 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf,
1116 chip->oob_poi, true, page);
1117 }
1118
1119 /* BCH read helpers */
1120 static int marvell_nfc_hw_ecc_bch_read_page_raw(struct mtd_info *mtd,
1121 struct nand_chip *chip, u8 *buf,
1122 int oob_required, int page)
1123 {
1124 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1125 u8 *oob = chip->oob_poi;
1126 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1127 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1128 lt->last_spare_bytes;
1129 int data_len = lt->data_bytes;
1130 int spare_len = lt->spare_bytes;
1131 int ecc_len = lt->ecc_bytes;
1132 int chunk;
1133
1134 if (oob_required)
1135 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1136
1137 nand_read_page_op(chip, page, 0, NULL, 0);
1138
1139 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1140 /* Update last chunk length */
1141 if (chunk >= lt->full_chunk_cnt) {
1142 data_len = lt->last_data_bytes;
1143 spare_len = lt->last_spare_bytes;
1144 ecc_len = lt->last_ecc_bytes;
1145 }
1146
1147 /* Read data bytes*/
1148 nand_change_read_column_op(chip, chunk * chunk_size,
1149 buf + (lt->data_bytes * chunk),
1150 data_len, false);
1151
1152 /* Read spare bytes */
1153 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
1154 spare_len, false);
1155
1156 /* Read ECC bytes */
1157 nand_read_data_op(chip, oob + ecc_offset +
1158 (ALIGN(lt->ecc_bytes, 32) * chunk),
1159 ecc_len, false);
1160 }
1161
1162 return 0;
1163 }
1164
1165 static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk,
1166 u8 *data, unsigned int data_len,
1167 u8 *spare, unsigned int spare_len,
1168 int page)
1169 {
1170 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1171 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1172 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1173 int i, ret;
1174 struct marvell_nfc_op nfc_op = {
1175 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1176 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1177 NDCB0_LEN_OVRD,
1178 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1179 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1180 .ndcb[3] = data_len + spare_len,
1181 };
1182
1183 ret = marvell_nfc_prepare_cmd(chip);
1184 if (ret)
1185 return;
1186
1187 if (chunk == 0)
1188 nfc_op.ndcb[0] |= NDCB0_DBC |
1189 NDCB0_CMD1(NAND_CMD_READ0) |
1190 NDCB0_CMD2(NAND_CMD_READSTART);
1191
1192 /*
1193 * Trigger the naked read operation only on the last chunk.
1194 * Otherwise, use monolithic read.
1195 */
1196 if (lt->nchunks == 1 || (chunk < lt->nchunks - 1))
1197 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1198 else
1199 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1200
1201 marvell_nfc_send_cmd(chip, &nfc_op);
1202
1203 /*
1204 * According to the datasheet, when reading from NDDB
1205 * with BCH enabled, after each 32 bytes reads, we
1206 * have to make sure that the NDSR.RDDREQ bit is set.
1207 *
1208 * Drain the FIFO, 8 32-bit reads at a time, and skip
1209 * the polling on the last read.
1210 *
1211 * Length is a multiple of 32 bytes, hence it is a multiple of 8 too.
1212 */
1213 for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1214 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1215 "RDDREQ while draining FIFO (data)");
1216 marvell_nfc_xfer_data_in_pio(nfc, data,
1217 FIFO_DEPTH * BCH_SEQ_READS);
1218 data += FIFO_DEPTH * BCH_SEQ_READS;
1219 }
1220
1221 for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1222 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1223 "RDDREQ while draining FIFO (OOB)");
1224 marvell_nfc_xfer_data_in_pio(nfc, spare,
1225 FIFO_DEPTH * BCH_SEQ_READS);
1226 spare += FIFO_DEPTH * BCH_SEQ_READS;
1227 }
1228 }
1229
1230 static int marvell_nfc_hw_ecc_bch_read_page(struct mtd_info *mtd,
1231 struct nand_chip *chip,
1232 u8 *buf, int oob_required,
1233 int page)
1234 {
1235 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1236 int data_len = lt->data_bytes, spare_len = lt->spare_bytes, ecc_len;
1237 u8 *data = buf, *spare = chip->oob_poi, *ecc;
1238 int max_bitflips = 0;
1239 u32 failure_mask = 0;
1240 int chunk, ecc_offset_in_page, ret;
1241
1242 /*
1243 * With BCH, OOB is not fully used (and thus not read entirely), not
1244 * expected bytes could show up at the end of the OOB buffer if not
1245 * explicitly erased.
1246 */
1247 if (oob_required)
1248 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1249
1250 marvell_nfc_enable_hw_ecc(chip);
1251
1252 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1253 /* Update length for the last chunk */
1254 if (chunk >= lt->full_chunk_cnt) {
1255 data_len = lt->last_data_bytes;
1256 spare_len = lt->last_spare_bytes;
1257 }
1258
1259 /* Read the chunk and detect number of bitflips */
1260 marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
1261 spare, spare_len, page);
1262 ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
1263 if (ret)
1264 failure_mask |= BIT(chunk);
1265
1266 data += data_len;
1267 spare += spare_len;
1268 }
1269
1270 marvell_nfc_disable_hw_ecc(chip);
1271
1272 if (!failure_mask)
1273 return max_bitflips;
1274
1275 /*
1276 * Please note that dumping the ECC bytes during a normal read with OOB
1277 * area would add a significant overhead as ECC bytes are "consumed" by
1278 * the controller in normal mode and must be re-read in raw mode. To
1279 * avoid dropping the performances, we prefer not to include them. The
1280 * user should re-read the page in raw mode if ECC bytes are required.
1281 *
1282 * However, for any subpage read error reported by ->correct(), the ECC
1283 * bytes must be read in raw mode and the full subpage must be checked
1284 * to see if it is entirely empty of if there was an actual error.
1285 */
1286 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1287 /* No failure reported for this chunk, move to the next one */
1288 if (!(failure_mask & BIT(chunk)))
1289 continue;
1290
1291 /* Derive ECC bytes positions (in page/buffer) and length */
1292 ecc = chip->oob_poi +
1293 (lt->full_chunk_cnt * lt->spare_bytes) +
1294 lt->last_spare_bytes +
1295 (chunk * ALIGN(lt->ecc_bytes, 32));
1296 ecc_offset_in_page =
1297 (chunk * (lt->data_bytes + lt->spare_bytes +
1298 lt->ecc_bytes)) +
1299 (chunk < lt->full_chunk_cnt ?
1300 lt->data_bytes + lt->spare_bytes :
1301 lt->last_data_bytes + lt->last_spare_bytes);
1302 ecc_len = chunk < lt->full_chunk_cnt ?
1303 lt->ecc_bytes : lt->last_ecc_bytes;
1304
1305 /* Do the actual raw read of the ECC bytes */
1306 nand_change_read_column_op(chip, ecc_offset_in_page,
1307 ecc, ecc_len, false);
1308
1309 /* Derive data/spare bytes positions (in buffer) and length */
1310 data = buf + (chunk * lt->data_bytes);
1311 data_len = chunk < lt->full_chunk_cnt ?
1312 lt->data_bytes : lt->last_data_bytes;
1313 spare = chip->oob_poi + (chunk * (lt->spare_bytes +
1314 lt->ecc_bytes));
1315 spare_len = chunk < lt->full_chunk_cnt ?
1316 lt->spare_bytes : lt->last_spare_bytes;
1317
1318 /* Check the entire chunk (data + spare + ecc) for emptyness */
1319 marvell_nfc_check_empty_chunk(chip, data, data_len, spare,
1320 spare_len, ecc, ecc_len,
1321 &max_bitflips);
1322 }
1323
1324 return max_bitflips;
1325 }
1326
1327 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct mtd_info *mtd,
1328 struct nand_chip *chip, int page)
1329 {
1330 /* Invalidate page cache */
1331 chip->pagebuf = -1;
1332
1333 return chip->ecc.read_page_raw(mtd, chip, chip->data_buf, true, page);
1334 }
1335
1336 static int marvell_nfc_hw_ecc_bch_read_oob(struct mtd_info *mtd,
1337 struct nand_chip *chip, int page)
1338 {
1339 /* Invalidate page cache */
1340 chip->pagebuf = -1;
1341
1342 return chip->ecc.read_page(mtd, chip, chip->data_buf, true, page);
1343 }
1344
1345 /* BCH write helpers */
1346 static int marvell_nfc_hw_ecc_bch_write_page_raw(struct mtd_info *mtd,
1347 struct nand_chip *chip,
1348 const u8 *buf,
1349 int oob_required, int page)
1350 {
1351 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1352 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1353 int data_len = lt->data_bytes;
1354 int spare_len = lt->spare_bytes;
1355 int ecc_len = lt->ecc_bytes;
1356 int spare_offset = 0;
1357 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1358 lt->last_spare_bytes;
1359 int chunk;
1360
1361 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1362
1363 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1364 if (chunk >= lt->full_chunk_cnt) {
1365 data_len = lt->last_data_bytes;
1366 spare_len = lt->last_spare_bytes;
1367 ecc_len = lt->last_ecc_bytes;
1368 }
1369
1370 /* Point to the column of the next chunk */
1371 nand_change_write_column_op(chip, chunk * full_chunk_size,
1372 NULL, 0, false);
1373
1374 /* Write the data */
1375 nand_write_data_op(chip, buf + (chunk * lt->data_bytes),
1376 data_len, false);
1377
1378 if (!oob_required)
1379 continue;
1380
1381 /* Write the spare bytes */
1382 if (spare_len)
1383 nand_write_data_op(chip, chip->oob_poi + spare_offset,
1384 spare_len, false);
1385
1386 /* Write the ECC bytes */
1387 if (ecc_len)
1388 nand_write_data_op(chip, chip->oob_poi + ecc_offset,
1389 ecc_len, false);
1390
1391 spare_offset += spare_len;
1392 ecc_offset += ALIGN(ecc_len, 32);
1393 }
1394
1395 return nand_prog_page_end_op(chip);
1396 }
1397
1398 static int
1399 marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
1400 const u8 *data, unsigned int data_len,
1401 const u8 *spare, unsigned int spare_len,
1402 int page)
1403 {
1404 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1405 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1406 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1407 int ret;
1408 struct marvell_nfc_op nfc_op = {
1409 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
1410 .ndcb[3] = data_len + spare_len,
1411 };
1412
1413 /*
1414 * First operation dispatches the CMD_SEQIN command, issue the address
1415 * cycles and asks for the first chunk of data.
1416 * All operations in the middle (if any) will issue a naked write and
1417 * also ask for data.
1418 * Last operation (if any) asks for the last chunk of data through a
1419 * last naked write.
1420 */
1421 if (chunk == 0) {
1422 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) |
1423 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1424 NDCB0_CMD1(NAND_CMD_SEQIN);
1425 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1426 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1427 } else if (chunk < lt->nchunks - 1) {
1428 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1429 } else {
1430 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1431 }
1432
1433 /* Always dispatch the PAGEPROG command on the last chunk */
1434 if (chunk == lt->nchunks - 1)
1435 nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
1436
1437 ret = marvell_nfc_prepare_cmd(chip);
1438 if (ret)
1439 return ret;
1440
1441 marvell_nfc_send_cmd(chip, &nfc_op);
1442 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1443 "WRDREQ while loading FIFO (data)");
1444 if (ret)
1445 return ret;
1446
1447 /* Transfer the contents */
1448 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len));
1449 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len));
1450
1451 return 0;
1452 }
1453
1454 static int marvell_nfc_hw_ecc_bch_write_page(struct mtd_info *mtd,
1455 struct nand_chip *chip,
1456 const u8 *buf,
1457 int oob_required, int page)
1458 {
1459 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1460 const u8 *data = buf;
1461 const u8 *spare = chip->oob_poi;
1462 int data_len = lt->data_bytes;
1463 int spare_len = lt->spare_bytes;
1464 int chunk, ret;
1465
1466 /* Spare data will be written anyway, so clear it to avoid garbage */
1467 if (!oob_required)
1468 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1469
1470 marvell_nfc_enable_hw_ecc(chip);
1471
1472 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1473 if (chunk >= lt->full_chunk_cnt) {
1474 data_len = lt->last_data_bytes;
1475 spare_len = lt->last_spare_bytes;
1476 }
1477
1478 marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len,
1479 spare, spare_len, page);
1480 data += data_len;
1481 spare += spare_len;
1482
1483 /*
1484 * Waiting only for CMDD or PAGED is not enough, ECC are
1485 * partially written. No flag is set once the operation is
1486 * really finished but the ND_RUN bit is cleared, so wait for it
1487 * before stepping into the next command.
1488 */
1489 marvell_nfc_wait_ndrun(chip);
1490 }
1491
1492 ret = marvell_nfc_wait_op(chip,
1493 chip->data_interface.timings.sdr.tPROG_max);
1494
1495 marvell_nfc_disable_hw_ecc(chip);
1496
1497 if (ret)
1498 return ret;
1499
1500 return 0;
1501 }
1502
1503 static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct mtd_info *mtd,
1504 struct nand_chip *chip,
1505 int page)
1506 {
1507 /* Invalidate page cache */
1508 chip->pagebuf = -1;
1509
1510 memset(chip->data_buf, 0xFF, mtd->writesize);
1511
1512 return chip->ecc.write_page_raw(mtd, chip, chip->data_buf, true, page);
1513 }
1514
1515 static int marvell_nfc_hw_ecc_bch_write_oob(struct mtd_info *mtd,
1516 struct nand_chip *chip, int page)
1517 {
1518 /* Invalidate page cache */
1519 chip->pagebuf = -1;
1520
1521 memset(chip->data_buf, 0xFF, mtd->writesize);
1522
1523 return chip->ecc.write_page(mtd, chip, chip->data_buf, true, page);
1524 }
1525
1526 /* NAND framework ->exec_op() hooks and related helpers */
1527 static void marvell_nfc_parse_instructions(struct nand_chip *chip,
1528 const struct nand_subop *subop,
1529 struct marvell_nfc_op *nfc_op)
1530 {
1531 const struct nand_op_instr *instr = NULL;
1532 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1533 bool first_cmd = true;
1534 unsigned int op_id;
1535 int i;
1536
1537 /* Reset the input structure as most of its fields will be OR'ed */
1538 memset(nfc_op, 0, sizeof(struct marvell_nfc_op));
1539
1540 for (op_id = 0; op_id < subop->ninstrs; op_id++) {
1541 unsigned int offset, naddrs;
1542 const u8 *addrs;
1543 int len = nand_subop_get_data_len(subop, op_id);
1544
1545 instr = &subop->instrs[op_id];
1546
1547 switch (instr->type) {
1548 case NAND_OP_CMD_INSTR:
1549 if (first_cmd)
1550 nfc_op->ndcb[0] |=
1551 NDCB0_CMD1(instr->ctx.cmd.opcode);
1552 else
1553 nfc_op->ndcb[0] |=
1554 NDCB0_CMD2(instr->ctx.cmd.opcode) |
1555 NDCB0_DBC;
1556
1557 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1558 first_cmd = false;
1559 break;
1560
1561 case NAND_OP_ADDR_INSTR:
1562 offset = nand_subop_get_addr_start_off(subop, op_id);
1563 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
1564 addrs = &instr->ctx.addr.addrs[offset];
1565
1566 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs);
1567
1568 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
1569 nfc_op->ndcb[1] |= addrs[i] << (8 * i);
1570
1571 if (naddrs >= 5)
1572 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]);
1573 if (naddrs >= 6)
1574 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]);
1575 if (naddrs == 7)
1576 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]);
1577
1578 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1579 break;
1580
1581 case NAND_OP_DATA_IN_INSTR:
1582 nfc_op->data_instr = instr;
1583 nfc_op->data_instr_idx = op_id;
1584 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ);
1585 if (nfc->caps->is_nfcv2) {
1586 nfc_op->ndcb[0] |=
1587 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1588 NDCB0_LEN_OVRD;
1589 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1590 }
1591 nfc_op->data_delay_ns = instr->delay_ns;
1592 break;
1593
1594 case NAND_OP_DATA_OUT_INSTR:
1595 nfc_op->data_instr = instr;
1596 nfc_op->data_instr_idx = op_id;
1597 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE);
1598 if (nfc->caps->is_nfcv2) {
1599 nfc_op->ndcb[0] |=
1600 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1601 NDCB0_LEN_OVRD;
1602 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1603 }
1604 nfc_op->data_delay_ns = instr->delay_ns;
1605 break;
1606
1607 case NAND_OP_WAITRDY_INSTR:
1608 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
1609 nfc_op->rdy_delay_ns = instr->delay_ns;
1610 break;
1611 }
1612 }
1613 }
1614
1615 static int marvell_nfc_xfer_data_pio(struct nand_chip *chip,
1616 const struct nand_subop *subop,
1617 struct marvell_nfc_op *nfc_op)
1618 {
1619 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1620 const struct nand_op_instr *instr = nfc_op->data_instr;
1621 unsigned int op_id = nfc_op->data_instr_idx;
1622 unsigned int len = nand_subop_get_data_len(subop, op_id);
1623 unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
1624 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
1625 int ret;
1626
1627 if (instr->ctx.data.force_8bit)
1628 marvell_nfc_force_byte_access(chip, true);
1629
1630 if (reading) {
1631 u8 *in = instr->ctx.data.buf.in + offset;
1632
1633 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1634 } else {
1635 const u8 *out = instr->ctx.data.buf.out + offset;
1636
1637 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
1638 }
1639
1640 if (instr->ctx.data.force_8bit)
1641 marvell_nfc_force_byte_access(chip, false);
1642
1643 return ret;
1644 }
1645
1646 static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip,
1647 const struct nand_subop *subop)
1648 {
1649 struct marvell_nfc_op nfc_op;
1650 bool reading;
1651 int ret;
1652
1653 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1654 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
1655
1656 ret = marvell_nfc_prepare_cmd(chip);
1657 if (ret)
1658 return ret;
1659
1660 marvell_nfc_send_cmd(chip, &nfc_op);
1661 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1662 "RDDREQ/WRDREQ while draining raw data");
1663 if (ret)
1664 return ret;
1665
1666 cond_delay(nfc_op.cle_ale_delay_ns);
1667
1668 if (reading) {
1669 if (nfc_op.rdy_timeout_ms) {
1670 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1671 if (ret)
1672 return ret;
1673 }
1674
1675 cond_delay(nfc_op.rdy_delay_ns);
1676 }
1677
1678 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1679 ret = marvell_nfc_wait_cmdd(chip);
1680 if (ret)
1681 return ret;
1682
1683 cond_delay(nfc_op.data_delay_ns);
1684
1685 if (!reading) {
1686 if (nfc_op.rdy_timeout_ms) {
1687 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1688 if (ret)
1689 return ret;
1690 }
1691
1692 cond_delay(nfc_op.rdy_delay_ns);
1693 }
1694
1695 /*
1696 * NDCR ND_RUN bit should be cleared automatically at the end of each
1697 * operation but experience shows that the behavior is buggy when it
1698 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1699 */
1700 if (!reading) {
1701 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1702
1703 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1704 nfc->regs + NDCR);
1705 }
1706
1707 return 0;
1708 }
1709
1710 static int marvell_nfc_naked_access_exec(struct nand_chip *chip,
1711 const struct nand_subop *subop)
1712 {
1713 struct marvell_nfc_op nfc_op;
1714 int ret;
1715
1716 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1717
1718 /*
1719 * Naked access are different in that they need to be flagged as naked
1720 * by the controller. Reset the controller registers fields that inform
1721 * on the type and refill them according to the ongoing operation.
1722 */
1723 nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) |
1724 NDCB0_CMD_XTYPE(XTYPE_MASK));
1725 switch (subop->instrs[0].type) {
1726 case NAND_OP_CMD_INSTR:
1727 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD);
1728 break;
1729 case NAND_OP_ADDR_INSTR:
1730 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR);
1731 break;
1732 case NAND_OP_DATA_IN_INSTR:
1733 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) |
1734 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1735 break;
1736 case NAND_OP_DATA_OUT_INSTR:
1737 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) |
1738 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1739 break;
1740 default:
1741 /* This should never happen */
1742 break;
1743 }
1744
1745 ret = marvell_nfc_prepare_cmd(chip);
1746 if (ret)
1747 return ret;
1748
1749 marvell_nfc_send_cmd(chip, &nfc_op);
1750
1751 if (!nfc_op.data_instr) {
1752 ret = marvell_nfc_wait_cmdd(chip);
1753 cond_delay(nfc_op.cle_ale_delay_ns);
1754 return ret;
1755 }
1756
1757 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1758 "RDDREQ/WRDREQ while draining raw data");
1759 if (ret)
1760 return ret;
1761
1762 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1763 ret = marvell_nfc_wait_cmdd(chip);
1764 if (ret)
1765 return ret;
1766
1767 /*
1768 * NDCR ND_RUN bit should be cleared automatically at the end of each
1769 * operation but experience shows that the behavior is buggy when it
1770 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1771 */
1772 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) {
1773 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1774
1775 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1776 nfc->regs + NDCR);
1777 }
1778
1779 return 0;
1780 }
1781
1782 static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip,
1783 const struct nand_subop *subop)
1784 {
1785 struct marvell_nfc_op nfc_op;
1786 int ret;
1787
1788 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1789
1790 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1791 cond_delay(nfc_op.rdy_delay_ns);
1792
1793 return ret;
1794 }
1795
1796 static int marvell_nfc_read_id_type_exec(struct nand_chip *chip,
1797 const struct nand_subop *subop)
1798 {
1799 struct marvell_nfc_op nfc_op;
1800 int ret;
1801
1802 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1803 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1804 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID);
1805
1806 ret = marvell_nfc_prepare_cmd(chip);
1807 if (ret)
1808 return ret;
1809
1810 marvell_nfc_send_cmd(chip, &nfc_op);
1811 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1812 "RDDREQ while reading ID");
1813 if (ret)
1814 return ret;
1815
1816 cond_delay(nfc_op.cle_ale_delay_ns);
1817
1818 if (nfc_op.rdy_timeout_ms) {
1819 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1820 if (ret)
1821 return ret;
1822 }
1823
1824 cond_delay(nfc_op.rdy_delay_ns);
1825
1826 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1827 ret = marvell_nfc_wait_cmdd(chip);
1828 if (ret)
1829 return ret;
1830
1831 cond_delay(nfc_op.data_delay_ns);
1832
1833 return 0;
1834 }
1835
1836 static int marvell_nfc_read_status_exec(struct nand_chip *chip,
1837 const struct nand_subop *subop)
1838 {
1839 struct marvell_nfc_op nfc_op;
1840 int ret;
1841
1842 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1843 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1844 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS);
1845
1846 ret = marvell_nfc_prepare_cmd(chip);
1847 if (ret)
1848 return ret;
1849
1850 marvell_nfc_send_cmd(chip, &nfc_op);
1851 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1852 "RDDREQ while reading status");
1853 if (ret)
1854 return ret;
1855
1856 cond_delay(nfc_op.cle_ale_delay_ns);
1857
1858 if (nfc_op.rdy_timeout_ms) {
1859 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1860 if (ret)
1861 return ret;
1862 }
1863
1864 cond_delay(nfc_op.rdy_delay_ns);
1865
1866 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1867 ret = marvell_nfc_wait_cmdd(chip);
1868 if (ret)
1869 return ret;
1870
1871 cond_delay(nfc_op.data_delay_ns);
1872
1873 return 0;
1874 }
1875
1876 static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip,
1877 const struct nand_subop *subop)
1878 {
1879 struct marvell_nfc_op nfc_op;
1880 int ret;
1881
1882 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1883 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET);
1884
1885 ret = marvell_nfc_prepare_cmd(chip);
1886 if (ret)
1887 return ret;
1888
1889 marvell_nfc_send_cmd(chip, &nfc_op);
1890 ret = marvell_nfc_wait_cmdd(chip);
1891 if (ret)
1892 return ret;
1893
1894 cond_delay(nfc_op.cle_ale_delay_ns);
1895
1896 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1897 if (ret)
1898 return ret;
1899
1900 cond_delay(nfc_op.rdy_delay_ns);
1901
1902 return 0;
1903 }
1904
1905 static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip,
1906 const struct nand_subop *subop)
1907 {
1908 struct marvell_nfc_op nfc_op;
1909 int ret;
1910
1911 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1912 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE);
1913
1914 ret = marvell_nfc_prepare_cmd(chip);
1915 if (ret)
1916 return ret;
1917
1918 marvell_nfc_send_cmd(chip, &nfc_op);
1919 ret = marvell_nfc_wait_cmdd(chip);
1920 if (ret)
1921 return ret;
1922
1923 cond_delay(nfc_op.cle_ale_delay_ns);
1924
1925 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1926 if (ret)
1927 return ret;
1928
1929 cond_delay(nfc_op.rdy_delay_ns);
1930
1931 return 0;
1932 }
1933
1934 static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER(
1935 /* Monolithic reads/writes */
1936 NAND_OP_PARSER_PATTERN(
1937 marvell_nfc_monolithic_access_exec,
1938 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1939 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2),
1940 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1941 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
1942 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
1943 NAND_OP_PARSER_PATTERN(
1944 marvell_nfc_monolithic_access_exec,
1945 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1946 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2),
1947 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE),
1948 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1949 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1950 /* Naked commands */
1951 NAND_OP_PARSER_PATTERN(
1952 marvell_nfc_naked_access_exec,
1953 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
1954 NAND_OP_PARSER_PATTERN(
1955 marvell_nfc_naked_access_exec,
1956 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)),
1957 NAND_OP_PARSER_PATTERN(
1958 marvell_nfc_naked_access_exec,
1959 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
1960 NAND_OP_PARSER_PATTERN(
1961 marvell_nfc_naked_access_exec,
1962 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)),
1963 NAND_OP_PARSER_PATTERN(
1964 marvell_nfc_naked_waitrdy_exec,
1965 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1966 );
1967
1968 static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
1969 /* Naked commands not supported, use a function for each pattern */
1970 NAND_OP_PARSER_PATTERN(
1971 marvell_nfc_read_id_type_exec,
1972 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1973 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
1974 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
1975 NAND_OP_PARSER_PATTERN(
1976 marvell_nfc_erase_cmd_type_exec,
1977 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1978 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
1979 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1980 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1981 NAND_OP_PARSER_PATTERN(
1982 marvell_nfc_read_status_exec,
1983 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1984 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
1985 NAND_OP_PARSER_PATTERN(
1986 marvell_nfc_reset_cmd_type_exec,
1987 NAND_OP_PARSER_PAT_CMD_ELEM(false),
1988 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1989 NAND_OP_PARSER_PATTERN(
1990 marvell_nfc_naked_waitrdy_exec,
1991 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1992 );
1993
1994 static int marvell_nfc_exec_op(struct nand_chip *chip,
1995 const struct nand_operation *op,
1996 bool check_only)
1997 {
1998 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1999
2000 if (nfc->caps->is_nfcv2)
2001 return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
2002 op, check_only);
2003 else
2004 return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser,
2005 op, check_only);
2006 }
2007
2008 /*
2009 * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
2010 * usable.
2011 */
2012 static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2013 struct mtd_oob_region *oobregion)
2014 {
2015 struct nand_chip *chip = mtd_to_nand(mtd);
2016 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2017
2018 if (section)
2019 return -ERANGE;
2020
2021 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) +
2022 lt->last_ecc_bytes;
2023 oobregion->offset = mtd->oobsize - oobregion->length;
2024
2025 return 0;
2026 }
2027
2028 static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section,
2029 struct mtd_oob_region *oobregion)
2030 {
2031 struct nand_chip *chip = mtd_to_nand(mtd);
2032 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2033
2034 if (section)
2035 return -ERANGE;
2036
2037 /*
2038 * Bootrom looks in bytes 0 & 5 for bad blocks for the
2039 * 4KB page / 4bit BCH combination.
2040 */
2041 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)
2042 oobregion->offset = 6;
2043 else
2044 oobregion->offset = 2;
2045
2046 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) +
2047 lt->last_spare_bytes - oobregion->offset;
2048
2049 return 0;
2050 }
2051
2052 static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = {
2053 .ecc = marvell_nand_ooblayout_ecc,
2054 .free = marvell_nand_ooblayout_free,
2055 };
2056
2057 static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
2058 struct nand_ecc_ctrl *ecc)
2059 {
2060 struct nand_chip *chip = mtd_to_nand(mtd);
2061 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2062 const struct marvell_hw_ecc_layout *l;
2063 int i;
2064
2065 if (!nfc->caps->is_nfcv2 &&
2066 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) {
2067 dev_err(nfc->dev,
2068 "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n",
2069 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize);
2070 return -ENOTSUPP;
2071 }
2072
2073 to_marvell_nand(chip)->layout = NULL;
2074 for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) {
2075 l = &marvell_nfc_layouts[i];
2076 if (mtd->writesize == l->writesize &&
2077 ecc->size == l->chunk && ecc->strength == l->strength) {
2078 to_marvell_nand(chip)->layout = l;
2079 break;
2080 }
2081 }
2082
2083 if (!to_marvell_nand(chip)->layout ||
2084 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2085 dev_err(nfc->dev,
2086 "ECC strength %d at page size %d is not supported\n",
2087 ecc->strength, mtd->writesize);
2088 return -ENOTSUPP;
2089 }
2090
2091 mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
2092 ecc->steps = l->nchunks;
2093 ecc->size = l->data_bytes;
2094
2095 if (ecc->strength == 1) {
2096 chip->ecc.algo = NAND_ECC_HAMMING;
2097 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2098 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2099 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2100 ecc->read_oob = ecc->read_oob_raw;
2101 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2102 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2103 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2104 ecc->write_oob = ecc->write_oob_raw;
2105 } else {
2106 chip->ecc.algo = NAND_ECC_BCH;
2107 ecc->strength = 16;
2108 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2109 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2110 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2111 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2112 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2113 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2114 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2115 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2116 }
2117
2118 return 0;
2119 }
2120
2121 static int marvell_nand_ecc_init(struct mtd_info *mtd,
2122 struct nand_ecc_ctrl *ecc)
2123 {
2124 struct nand_chip *chip = mtd_to_nand(mtd);
2125 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2126 int ret;
2127
2128 if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) {
2129 if (chip->ecc_step_ds && chip->ecc_strength_ds) {
2130 ecc->size = chip->ecc_step_ds;
2131 ecc->strength = chip->ecc_strength_ds;
2132 } else {
2133 dev_info(nfc->dev,
2134 "No minimum ECC strength, using 1b/512B\n");
2135 ecc->size = 512;
2136 ecc->strength = 1;
2137 }
2138 }
2139
2140 switch (ecc->mode) {
2141 case NAND_ECC_HW:
2142 ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc);
2143 if (ret)
2144 return ret;
2145 break;
2146 case NAND_ECC_NONE:
2147 case NAND_ECC_SOFT:
2148 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
2149 mtd->writesize != SZ_2K) {
2150 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
2151 mtd->writesize);
2152 return -EINVAL;
2153 }
2154 break;
2155 default:
2156 return -EINVAL;
2157 }
2158
2159 return 0;
2160 }
2161
2162 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
2163 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
2164
2165 static struct nand_bbt_descr bbt_main_descr = {
2166 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2167 NAND_BBT_2BIT | NAND_BBT_VERSION,
2168 .offs = 8,
2169 .len = 6,
2170 .veroffs = 14,
2171 .maxblocks = 8, /* Last 8 blocks in each chip */
2172 .pattern = bbt_pattern
2173 };
2174
2175 static struct nand_bbt_descr bbt_mirror_descr = {
2176 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2177 NAND_BBT_2BIT | NAND_BBT_VERSION,
2178 .offs = 8,
2179 .len = 6,
2180 .veroffs = 14,
2181 .maxblocks = 8, /* Last 8 blocks in each chip */
2182 .pattern = bbt_mirror_pattern
2183 };
2184
2185 static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
2186 const struct nand_data_interface
2187 *conf)
2188 {
2189 struct nand_chip *chip = mtd_to_nand(mtd);
2190 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2191 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2192 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->ecc_clk) * 2;
2193 const struct nand_sdr_timings *sdr;
2194 struct marvell_nfc_timings nfc_tmg;
2195 int read_delay;
2196
2197 sdr = nand_get_sdr_timings(conf);
2198 if (IS_ERR(sdr))
2199 return PTR_ERR(sdr);
2200
2201 /*
2202 * SDR timings are given in pico-seconds while NFC timings must be
2203 * expressed in NAND controller clock cycles, which is half of the
2204 * frequency of the accessible ECC clock retrieved by clk_get_rate().
2205 * This is not written anywhere in the datasheet but was observed
2206 * with an oscilloscope.
2207 *
2208 * NFC datasheet gives equations from which thoses calculations
2209 * are derived, they tend to be slightly more restrictives than the
2210 * given core timings and may improve the overall speed.
2211 */
2212 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2213 nfc_tmg.tRH = nfc_tmg.tRP;
2214 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2215 nfc_tmg.tWH = nfc_tmg.tWP;
2216 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2217 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2218 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2219 /*
2220 * Read delay is the time of propagation from SoC pins to NFC internal
2221 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In
2222 * EDO mode, an additional delay of tRH must be taken into account so
2223 * the data is sampled on the falling edge instead of the rising edge.
2224 */
2225 read_delay = sdr->tRC_min >= 30000 ?
2226 MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
2227
2228 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2229 /*
2230 * tWHR and tRHW are supposed to be read to write delays (and vice
2231 * versa) but in some cases, ie. when doing a change column, they must
2232 * be greater than that to be sure tCCS delay is respected.
2233 */
2234 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2235 period_ns) - 2,
2236 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2237 period_ns);
2238
2239 /* Use WAIT_MODE (wait for RB line) instead of only relying on delays */
2240 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2241
2242 if (chipnr < 0)
2243 return 0;
2244
2245 marvell_nand->ndtr0 =
2246 NDTR0_TRP(nfc_tmg.tRP) |
2247 NDTR0_TRH(nfc_tmg.tRH) |
2248 NDTR0_ETRP(nfc_tmg.tRP) |
2249 NDTR0_TWP(nfc_tmg.tWP) |
2250 NDTR0_TWH(nfc_tmg.tWH) |
2251 NDTR0_TCS(nfc_tmg.tCS) |
2252 NDTR0_TCH(nfc_tmg.tCH) |
2253 NDTR0_RD_CNT_DEL(read_delay) |
2254 NDTR0_SELCNTR |
2255 NDTR0_TADL(nfc_tmg.tADL);
2256
2257 marvell_nand->ndtr1 =
2258 NDTR1_TAR(nfc_tmg.tAR) |
2259 NDTR1_TWHR(nfc_tmg.tWHR) |
2260 NDTR1_TRHW(nfc_tmg.tRHW) |
2261 NDTR1_WAIT_MODE |
2262 NDTR1_TR(nfc_tmg.tR);
2263
2264 return 0;
2265 }
2266
2267 static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
2268 struct device_node *np)
2269 {
2270 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev);
2271 struct marvell_nand_chip *marvell_nand;
2272 struct mtd_info *mtd;
2273 struct nand_chip *chip;
2274 int nsels, ret, i;
2275 u32 cs, rb;
2276
2277 /*
2278 * The legacy "num-cs" property indicates the number of CS on the only
2279 * chip connected to the controller (legacy bindings does not support
2280 * more than one chip). CS are only incremented one by one while the RB
2281 * pin is always the #0.
2282 *
2283 * When not using legacy bindings, a couple of "reg" and "nand-rb"
2284 * properties must be filled. For each chip, expressed as a subnode,
2285 * "reg" points to the CS lines and "nand-rb" to the RB line.
2286 */
2287 if (pdata) {
2288 nsels = 1;
2289 } else if (nfc->caps->legacy_of_bindings &&
2290 !of_get_property(np, "num-cs", &nsels)) {
2291 dev_err(dev, "missing num-cs property\n");
2292 return -EINVAL;
2293 } else if (!of_get_property(np, "reg", &nsels)) {
2294 dev_err(dev, "missing reg property\n");
2295 return -EINVAL;
2296 }
2297
2298 if (!pdata)
2299 nsels /= sizeof(u32);
2300 if (!nsels) {
2301 dev_err(dev, "invalid reg property size\n");
2302 return -EINVAL;
2303 }
2304
2305 /* Alloc the nand chip structure */
2306 marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) +
2307 (nsels *
2308 sizeof(struct marvell_nand_chip_sel)),
2309 GFP_KERNEL);
2310 if (!marvell_nand) {
2311 dev_err(dev, "could not allocate chip structure\n");
2312 return -ENOMEM;
2313 }
2314
2315 marvell_nand->nsels = nsels;
2316 marvell_nand->selected_die = -1;
2317
2318 for (i = 0; i < nsels; i++) {
2319 if (pdata || nfc->caps->legacy_of_bindings) {
2320 /*
2321 * Legacy bindings use the CS lines in natural
2322 * order (0, 1, ...)
2323 */
2324 cs = i;
2325 } else {
2326 /* Retrieve CS id */
2327 ret = of_property_read_u32_index(np, "reg", i, &cs);
2328 if (ret) {
2329 dev_err(dev, "could not retrieve reg property: %d\n",
2330 ret);
2331 return ret;
2332 }
2333 }
2334
2335 if (cs >= nfc->caps->max_cs_nb) {
2336 dev_err(dev, "invalid reg value: %u (max CS = %d)\n",
2337 cs, nfc->caps->max_cs_nb);
2338 return -EINVAL;
2339 }
2340
2341 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
2342 dev_err(dev, "CS %d already assigned\n", cs);
2343 return -EINVAL;
2344 }
2345
2346 /*
2347 * The cs variable represents the chip select id, which must be
2348 * converted in bit fields for NDCB0 and NDCB2 to select the
2349 * right chip. Unfortunately, due to a lack of information on
2350 * the subject and incoherent documentation, the user should not
2351 * use CS1 and CS3 at all as asserting them is not supported in
2352 * a reliable way (due to multiplexing inside ADDR5 field).
2353 */
2354 marvell_nand->sels[i].cs = cs;
2355 switch (cs) {
2356 case 0:
2357 case 2:
2358 marvell_nand->sels[i].ndcb0_csel = 0;
2359 break;
2360 case 1:
2361 case 3:
2362 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL;
2363 break;
2364 default:
2365 return -EINVAL;
2366 }
2367
2368 /* Retrieve RB id */
2369 if (pdata || nfc->caps->legacy_of_bindings) {
2370 /* Legacy bindings always use RB #0 */
2371 rb = 0;
2372 } else {
2373 ret = of_property_read_u32_index(np, "nand-rb", i,
2374 &rb);
2375 if (ret) {
2376 dev_err(dev,
2377 "could not retrieve RB property: %d\n",
2378 ret);
2379 return ret;
2380 }
2381 }
2382
2383 if (rb >= nfc->caps->max_rb_nb) {
2384 dev_err(dev, "invalid reg value: %u (max RB = %d)\n",
2385 rb, nfc->caps->max_rb_nb);
2386 return -EINVAL;
2387 }
2388
2389 marvell_nand->sels[i].rb = rb;
2390 }
2391
2392 chip = &marvell_nand->chip;
2393 chip->controller = &nfc->controller;
2394 nand_set_flash_node(chip, np);
2395
2396 chip->exec_op = marvell_nfc_exec_op;
2397 chip->select_chip = marvell_nfc_select_chip;
2398 if (nfc->caps->is_nfcv2 &&
2399 !of_property_read_bool(np, "marvell,nand-keep-config"))
2400 chip->setup_data_interface = marvell_nfc_setup_data_interface;
2401
2402 mtd = nand_to_mtd(chip);
2403 mtd->dev.parent = dev;
2404
2405 /*
2406 * Default to HW ECC engine mode. If the nand-ecc-mode property is given
2407 * in the DT node, this entry will be overwritten in nand_scan_ident().
2408 */
2409 chip->ecc.mode = NAND_ECC_HW;
2410
2411 /*
2412 * Save a reference value for timing registers before
2413 * ->setup_data_interface() is called.
2414 */
2415 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
2416 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
2417
2418 chip->options |= NAND_BUSWIDTH_AUTO;
2419 ret = nand_scan_ident(mtd, marvell_nand->nsels, NULL);
2420 if (ret) {
2421 dev_err(dev, "could not identify the nand chip\n");
2422 return ret;
2423 }
2424
2425 if (pdata && pdata->flash_bbt)
2426 chip->bbt_options |= NAND_BBT_USE_FLASH;
2427
2428 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
2429 /*
2430 * We'll use a bad block table stored in-flash and don't
2431 * allow writing the bad block marker to the flash.
2432 */
2433 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2434 chip->bbt_td = &bbt_main_descr;
2435 chip->bbt_md = &bbt_mirror_descr;
2436 }
2437
2438 /* Save the chip-specific fields of NDCR */
2439 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
2440 if (chip->options & NAND_BUSWIDTH_16)
2441 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
2442
2443 /*
2444 * On small page NANDs, only one cycle is needed to pass the
2445 * column address.
2446 */
2447 if (mtd->writesize <= 512) {
2448 marvell_nand->addr_cyc = 1;
2449 } else {
2450 marvell_nand->addr_cyc = 2;
2451 marvell_nand->ndcr |= NDCR_RA_START;
2452 }
2453
2454 /*
2455 * Now add the number of cycles needed to pass the row
2456 * address.
2457 *
2458 * Addressing a chip using CS 2 or 3 should also need the third row
2459 * cycle but due to inconsistance in the documentation and lack of
2460 * hardware to test this situation, this case is not supported.
2461 */
2462 if (chip->options & NAND_ROW_ADDR_3)
2463 marvell_nand->addr_cyc += 3;
2464 else
2465 marvell_nand->addr_cyc += 2;
2466
2467 if (pdata) {
2468 chip->ecc.size = pdata->ecc_step_size;
2469 chip->ecc.strength = pdata->ecc_strength;
2470 }
2471
2472 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2473 if (ret) {
2474 dev_err(dev, "ECC init failed: %d\n", ret);
2475 return ret;
2476 }
2477
2478 if (chip->ecc.mode == NAND_ECC_HW) {
2479 /*
2480 * Subpage write not available with hardware ECC, prohibit also
2481 * subpage read as in userspace subpage access would still be
2482 * allowed and subpage write, if used, would lead to numerous
2483 * uncorrectable ECC errors.
2484 */
2485 chip->options |= NAND_NO_SUBPAGE_WRITE;
2486 }
2487
2488 if (pdata || nfc->caps->legacy_of_bindings) {
2489 /*
2490 * We keep the MTD name unchanged to avoid breaking platforms
2491 * where the MTD cmdline parser is used and the bootloader
2492 * has not been updated to use the new naming scheme.
2493 */
2494 mtd->name = "pxa3xx_nand-0";
2495 } else if (!mtd->name) {
2496 /*
2497 * If the new bindings are used and the bootloader has not been
2498 * updated to pass a new mtdparts parameter on the cmdline, you
2499 * should define the following property in your NAND node, ie:
2500 *
2501 * label = "main-storage";
2502 *
2503 * This way, mtd->name will be set by the core when
2504 * nand_set_flash_node() is called.
2505 */
2506 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
2507 "%s:nand.%d", dev_name(nfc->dev),
2508 marvell_nand->sels[0].cs);
2509 if (!mtd->name) {
2510 dev_err(nfc->dev, "Failed to allocate mtd->name\n");
2511 return -ENOMEM;
2512 }
2513 }
2514
2515 ret = nand_scan_tail(mtd);
2516 if (ret) {
2517 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
2518 return ret;
2519 }
2520
2521 if (pdata)
2522 /* Legacy bindings support only one chip */
2523 ret = mtd_device_register(mtd, pdata->parts[0],
2524 pdata->nr_parts[0]);
2525 else
2526 ret = mtd_device_register(mtd, NULL, 0);
2527 if (ret) {
2528 dev_err(dev, "failed to register mtd device: %d\n", ret);
2529 nand_release(mtd);
2530 return ret;
2531 }
2532
2533 list_add_tail(&marvell_nand->node, &nfc->chips);
2534
2535 return 0;
2536 }
2537
2538 static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
2539 {
2540 struct device_node *np = dev->of_node;
2541 struct device_node *nand_np;
2542 int max_cs = nfc->caps->max_cs_nb;
2543 int nchips;
2544 int ret;
2545
2546 if (!np)
2547 nchips = 1;
2548 else
2549 nchips = of_get_child_count(np);
2550
2551 if (nchips > max_cs) {
2552 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips,
2553 max_cs);
2554 return -EINVAL;
2555 }
2556
2557 /*
2558 * Legacy bindings do not use child nodes to exhibit NAND chip
2559 * properties and layout. Instead, NAND properties are mixed with the
2560 * controller ones, and partitions are defined as direct subnodes of the
2561 * NAND controller node.
2562 */
2563 if (nfc->caps->legacy_of_bindings) {
2564 ret = marvell_nand_chip_init(dev, nfc, np);
2565 return ret;
2566 }
2567
2568 for_each_child_of_node(np, nand_np) {
2569 ret = marvell_nand_chip_init(dev, nfc, nand_np);
2570 if (ret) {
2571 of_node_put(nand_np);
2572 return ret;
2573 }
2574 }
2575
2576 return 0;
2577 }
2578
2579 static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
2580 {
2581 struct marvell_nand_chip *entry, *temp;
2582
2583 list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
2584 nand_release(nand_to_mtd(&entry->chip));
2585 list_del(&entry->node);
2586 }
2587 }
2588
2589 static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
2590 {
2591 struct platform_device *pdev = container_of(nfc->dev,
2592 struct platform_device,
2593 dev);
2594 struct dma_slave_config config = {};
2595 struct resource *r;
2596 dma_cap_mask_t mask;
2597 struct pxad_param param;
2598 int ret;
2599
2600 if (!IS_ENABLED(CONFIG_PXA_DMA)) {
2601 dev_warn(nfc->dev,
2602 "DMA not enabled in configuration\n");
2603 return -ENOTSUPP;
2604 }
2605
2606 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
2607 if (ret)
2608 return ret;
2609
2610 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2611 if (!r) {
2612 dev_err(nfc->dev, "No resource defined for data DMA\n");
2613 return -ENXIO;
2614 }
2615
2616 param.drcmr = r->start;
2617 param.prio = PXAD_PRIO_LOWEST;
2618 dma_cap_zero(mask);
2619 dma_cap_set(DMA_SLAVE, mask);
2620 nfc->dma_chan =
2621 dma_request_slave_channel_compat(mask, pxad_filter_fn,
2622 &param, nfc->dev,
2623 "data");
2624 if (!nfc->dma_chan) {
2625 dev_err(nfc->dev,
2626 "Unable to request data DMA channel\n");
2627 return -ENODEV;
2628 }
2629
2630 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2631 if (!r)
2632 return -ENXIO;
2633
2634 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2635 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2636 config.src_addr = r->start + NDDB;
2637 config.dst_addr = r->start + NDDB;
2638 config.src_maxburst = 32;
2639 config.dst_maxburst = 32;
2640 ret = dmaengine_slave_config(nfc->dma_chan, &config);
2641 if (ret < 0) {
2642 dev_err(nfc->dev, "Failed to configure DMA channel\n");
2643 return ret;
2644 }
2645
2646 /*
2647 * DMA must act on length multiple of 32 and this length may be
2648 * bigger than the destination buffer. Use this buffer instead
2649 * for DMA transfers and then copy the desired amount of data to
2650 * the provided buffer.
2651 */
2652 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2653 if (!nfc->dma_buf)
2654 return -ENOMEM;
2655
2656 nfc->use_dma = true;
2657
2658 return 0;
2659 }
2660
2661 static int marvell_nfc_init(struct marvell_nfc *nfc)
2662 {
2663 struct device_node *np = nfc->dev->of_node;
2664
2665 /*
2666 * Some SoCs like A7k/A8k need to enable manually the NAND
2667 * controller, gated clocks and reset bits to avoid being bootloader
2668 * dependent. This is done through the use of the System Functions
2669 * registers.
2670 */
2671 if (nfc->caps->need_system_controller) {
2672 struct regmap *sysctrl_base =
2673 syscon_regmap_lookup_by_phandle(np,
2674 "marvell,system-controller");
2675 u32 reg;
2676
2677 if (IS_ERR(sysctrl_base))
2678 return PTR_ERR(sysctrl_base);
2679
2680 reg = GENCONF_SOC_DEVICE_MUX_NFC_EN |
2681 GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
2682 GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
2683 GENCONF_SOC_DEVICE_MUX_NFC_INT_EN;
2684 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
2685
2686 regmap_read(sysctrl_base, GENCONF_CLK_GATING_CTRL, &reg);
2687 reg |= GENCONF_CLK_GATING_CTRL_ND_GATE;
2688 regmap_write(sysctrl_base, GENCONF_CLK_GATING_CTRL, reg);
2689
2690 regmap_read(sysctrl_base, GENCONF_ND_CLK_CTRL, &reg);
2691 reg |= GENCONF_ND_CLK_CTRL_EN;
2692 regmap_write(sysctrl_base, GENCONF_ND_CLK_CTRL, reg);
2693 }
2694
2695 /* Configure the DMA if appropriate */
2696 if (!nfc->caps->is_nfcv2)
2697 marvell_nfc_init_dma(nfc);
2698
2699 /*
2700 * ECC operations and interruptions are only enabled when specifically
2701 * needed. ECC shall not be activated in the early stages (fails probe).
2702 * Arbiter flag, even if marked as "reserved", must be set (empirical).
2703 * SPARE_EN bit must always be set or ECC bytes will not be at the same
2704 * offset in the read page and this will fail the protection.
2705 */
2706 writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
2707 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);
2708 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
2709 writel_relaxed(0, nfc->regs + NDECCCTRL);
2710
2711 return 0;
2712 }
2713
2714 static int marvell_nfc_probe(struct platform_device *pdev)
2715 {
2716 struct device *dev = &pdev->dev;
2717 struct resource *r;
2718 struct marvell_nfc *nfc;
2719 int ret;
2720 int irq;
2721
2722 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc),
2723 GFP_KERNEL);
2724 if (!nfc)
2725 return -ENOMEM;
2726
2727 nfc->dev = dev;
2728 nand_hw_control_init(&nfc->controller);
2729 INIT_LIST_HEAD(&nfc->chips);
2730
2731 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2732 nfc->regs = devm_ioremap_resource(dev, r);
2733 if (IS_ERR(nfc->regs))
2734 return PTR_ERR(nfc->regs);
2735
2736 irq = platform_get_irq(pdev, 0);
2737 if (irq < 0) {
2738 dev_err(dev, "failed to retrieve irq\n");
2739 return irq;
2740 }
2741
2742 nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL);
2743 if (IS_ERR(nfc->ecc_clk))
2744 return PTR_ERR(nfc->ecc_clk);
2745
2746 ret = clk_prepare_enable(nfc->ecc_clk);
2747 if (ret)
2748 return ret;
2749
2750 marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
2751 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
2752 ret = devm_request_irq(dev, irq, marvell_nfc_isr,
2753 0, "marvell-nfc", nfc);
2754 if (ret)
2755 goto unprepare_clk;
2756
2757 /* Get NAND controller capabilities */
2758 if (pdev->id_entry)
2759 nfc->caps = (void *)pdev->id_entry->driver_data;
2760 else
2761 nfc->caps = of_device_get_match_data(&pdev->dev);
2762
2763 if (!nfc->caps) {
2764 dev_err(dev, "Could not retrieve NFC caps\n");
2765 ret = -EINVAL;
2766 goto unprepare_clk;
2767 }
2768
2769 /* Init the controller and then probe the chips */
2770 ret = marvell_nfc_init(nfc);
2771 if (ret)
2772 goto unprepare_clk;
2773
2774 platform_set_drvdata(pdev, nfc);
2775
2776 ret = marvell_nand_chips_init(dev, nfc);
2777 if (ret)
2778 goto unprepare_clk;
2779
2780 return 0;
2781
2782 unprepare_clk:
2783 clk_disable_unprepare(nfc->ecc_clk);
2784
2785 return ret;
2786 }
2787
2788 static int marvell_nfc_remove(struct platform_device *pdev)
2789 {
2790 struct marvell_nfc *nfc = platform_get_drvdata(pdev);
2791
2792 marvell_nand_chips_cleanup(nfc);
2793
2794 if (nfc->use_dma) {
2795 dmaengine_terminate_all(nfc->dma_chan);
2796 dma_release_channel(nfc->dma_chan);
2797 }
2798
2799 clk_disable_unprepare(nfc->ecc_clk);
2800
2801 return 0;
2802 }
2803
2804 static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
2805 .max_cs_nb = 4,
2806 .max_rb_nb = 2,
2807 .need_system_controller = true,
2808 .is_nfcv2 = true,
2809 };
2810
2811 static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
2812 .max_cs_nb = 4,
2813 .max_rb_nb = 2,
2814 .is_nfcv2 = true,
2815 };
2816
2817 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = {
2818 .max_cs_nb = 2,
2819 .max_rb_nb = 1,
2820 .use_dma = true,
2821 };
2822
2823 static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = {
2824 .max_cs_nb = 4,
2825 .max_rb_nb = 2,
2826 .need_system_controller = true,
2827 .legacy_of_bindings = true,
2828 .is_nfcv2 = true,
2829 };
2830
2831 static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = {
2832 .max_cs_nb = 4,
2833 .max_rb_nb = 2,
2834 .legacy_of_bindings = true,
2835 .is_nfcv2 = true,
2836 };
2837
2838 static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = {
2839 .max_cs_nb = 2,
2840 .max_rb_nb = 1,
2841 .legacy_of_bindings = true,
2842 .use_dma = true,
2843 };
2844
2845 static const struct platform_device_id marvell_nfc_platform_ids[] = {
2846 {
2847 .name = "pxa3xx-nand",
2848 .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps,
2849 },
2850 { /* sentinel */ },
2851 };
2852 MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids);
2853
2854 static const struct of_device_id marvell_nfc_of_ids[] = {
2855 {
2856 .compatible = "marvell,armada-8k-nand-controller",
2857 .data = &marvell_armada_8k_nfc_caps,
2858 },
2859 {
2860 .compatible = "marvell,armada370-nand-controller",
2861 .data = &marvell_armada370_nfc_caps,
2862 },
2863 {
2864 .compatible = "marvell,pxa3xx-nand-controller",
2865 .data = &marvell_pxa3xx_nfc_caps,
2866 },
2867 /* Support for old/deprecated bindings: */
2868 {
2869 .compatible = "marvell,armada-8k-nand",
2870 .data = &marvell_armada_8k_nfc_legacy_caps,
2871 },
2872 {
2873 .compatible = "marvell,armada370-nand",
2874 .data = &marvell_armada370_nfc_legacy_caps,
2875 },
2876 {
2877 .compatible = "marvell,pxa3xx-nand",
2878 .data = &marvell_pxa3xx_nfc_legacy_caps,
2879 },
2880 { /* sentinel */ },
2881 };
2882 MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids);
2883
2884 static struct platform_driver marvell_nfc_driver = {
2885 .driver = {
2886 .name = "marvell-nfc",
2887 .of_match_table = marvell_nfc_of_ids,
2888 },
2889 .id_table = marvell_nfc_platform_ids,
2890 .probe = marvell_nfc_probe,
2891 .remove = marvell_nfc_remove,
2892 };
2893 module_platform_driver(marvell_nfc_driver);
2894
2895 MODULE_LICENSE("GPL");
2896 MODULE_DESCRIPTION("Marvell NAND controller driver");
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