drivers/mtd/nand/orion_nand.c

   1 /*
   2  * drivers/mtd/nand/orion_nand.c
   3  *
   4  * NAND support for Marvell Orion SoC platforms
   5  *
   6  * Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/rawnand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <asm/sizes.h>
  24 #include <linux/platform_data/mtd-orion_nand.h>
  25
  26 struct orion_nand_info {
  27         struct nand_chip chip;
  28         struct clk *clk;
  29 };
  30
  31 static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  32 {
  33         struct nand_chip *nc = mtd_to_nand(mtd);
  34         struct orion_nand_data *board = nand_get_controller_data(nc);
  35         u32 offs;
  36
  37         if (cmd == NAND_CMD_NONE)
  38                 return;
  39
  40         if (ctrl & NAND_CLE)
  41                 offs = (1 << board->cle);
  42         else if (ctrl & NAND_ALE)
  43                 offs = (1 << board->ale);
  44         else
  45                 return;
  46
  47         if (nc->options & NAND_BUSWIDTH_16)
  48                 offs <<= 1;
  49
  50         writeb(cmd, nc->IO_ADDR_W + offs);
  51 }
  52
  53 static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  54 {
  55         struct nand_chip *chip = mtd_to_nand(mtd);
  56         void __iomem *io_base = chip->IO_ADDR_R;
  57 #if __LINUX_ARM_ARCH__ >= 5
  58         uint64_t *buf64;
  59 #endif
  60         int i = 0;
  61
  62         while (len && (unsigned long)buf & 7) {
  63                 *buf++ = readb(io_base);
  64                 len--;
  65         }
  66 #if __LINUX_ARM_ARCH__ >= 5
  67         buf64 = (uint64_t *)buf;
  68         while (i < len/8) {
  69                 /*
  70                  * Since GCC has no proper constraint (PR 43518)
  71                  * force x variable to r2/r3 registers as ldrd instruction
  72                  * requires first register to be even.
  73                  */
  74                 register uint64_t x asm ("r2");
  75
  76                 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
  77                 buf64[i++] = x;
  78         }
  79         i *= 8;
  80 #else
  81         readsl(io_base, buf, len/4);
  82         i = len / 4 * 4;
  83 #endif
  84         while (i < len)
  85                 buf[i++] = readb(io_base);
  86 }
  87
  88 static int __init orion_nand_probe(struct platform_device *pdev)
  89 {
  90         struct orion_nand_info *info;
  91         struct mtd_info *mtd;
  92         struct nand_chip *nc;
  93         struct orion_nand_data *board;
  94         struct resource *res;
  95         void __iomem *io_base;
  96         int ret = 0;
  97         u32 val = 0;
  98
  99         info = devm_kzalloc(&pdev->dev,
 100                         sizeof(struct orion_nand_info),
 101                         GFP_KERNEL);
 102         if (!info)
 103                 return -ENOMEM;
 104         nc = &info->chip;
 105         mtd = nand_to_mtd(nc);
 106
 107         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 108         io_base = devm_ioremap_resource(&pdev->dev, res);
 109
 110         if (IS_ERR(io_base))
 111                 return PTR_ERR(io_base);
 112
 113         if (pdev->dev.of_node) {
 114                 board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
 115                                         GFP_KERNEL);
 116                 if (!board)
 117                         return -ENOMEM;
 118                 if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
 119                         board->cle = (u8)val;
 120                 else
 121                         board->cle = 0;
 122                 if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
 123                         board->ale = (u8)val;
 124                 else
 125                         board->ale = 1;
 126                 if (!of_property_read_u32(pdev->dev.of_node,
 127                                                 "bank-width", &val))
 128                         board->width = (u8)val * 8;
 129                 else
 130                         board->width = 8;
 131                 if (!of_property_read_u32(pdev->dev.of_node,
 132                                                 "chip-delay", &val))
 133                         board->chip_delay = (u8)val;
 134         } else {
 135                 board = dev_get_platdata(&pdev->dev);
 136         }
 137
 138         mtd->dev.parent = &pdev->dev;
 139
 140         nand_set_controller_data(nc, board);
 141         nand_set_flash_node(nc, pdev->dev.of_node);
 142         nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
 143         nc->cmd_ctrl = orion_nand_cmd_ctrl;
 144         nc->read_buf = orion_nand_read_buf;
 145         nc->ecc.mode = NAND_ECC_SOFT;
 146         nc->ecc.algo = NAND_ECC_HAMMING;
 147
 148         if (board->chip_delay)
 149                 nc->chip_delay = board->chip_delay;
 150
 151         WARN(board->width > 16,
 152                 "%d bit bus width out of range",
 153                 board->width);
 154
 155         if (board->width == 16)
 156                 nc->options |= NAND_BUSWIDTH_16;
 157
 158         if (board->dev_ready)
 159                 nc->dev_ready = board->dev_ready;
 160
 161         platform_set_drvdata(pdev, info);
 162
 163         /* Not all platforms can gate the clock, so it is not
 164            an error if the clock does not exists. */
 165         info->clk = devm_clk_get(&pdev->dev, NULL);
 166         if (IS_ERR(info->clk)) {
 167                 ret = PTR_ERR(info->clk);
 168                 if (ret == -ENOENT) {
 169                         info->clk = NULL;
 170                 } else {
 171                         dev_err(&pdev->dev, "failed to get clock!\n");
 172                         return ret;
 173                 }
 174         }
 175
 176         ret = clk_prepare_enable(info->clk);
 177         if (ret) {
 178                 dev_err(&pdev->dev, "failed to prepare clock!\n");
 179                 return ret;
 180         }
 181
 182         ret = nand_scan(mtd, 1);
 183         if (ret)
 184                 goto no_dev;
 185
 186         mtd->name = "orion_nand";
 187         ret = mtd_device_register(mtd, board->parts, board->nr_parts);
 188         if (ret) {
 189                 nand_release(mtd);
 190                 goto no_dev;
 191         }
 192
 193         return 0;
 194
 195 no_dev:
 196         clk_disable_unprepare(info->clk);
 197         return ret;
 198 }
 199
 200 static int orion_nand_remove(struct platform_device *pdev)
 201 {
 202         struct orion_nand_info *info = platform_get_drvdata(pdev);
 203         struct nand_chip *chip = &info->chip;
 204         struct mtd_info *mtd = nand_to_mtd(chip);
 205
 206         nand_release(mtd);
 207
 208         clk_disable_unprepare(info->clk);
 209
 210         return 0;
 211 }
 212
 213 #ifdef CONFIG_OF
 214 static const struct of_device_id orion_nand_of_match_table[] = {
 215         { .compatible = "marvell,orion-nand", },
 216         {},
 217 };
 218 MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
 219 #endif
 220
 221 static struct platform_driver orion_nand_driver = {
 222         .remove         = orion_nand_remove,
 223         .driver         = {
 224                 .name   = "orion_nand",
 225                 .of_match_table = of_match_ptr(orion_nand_of_match_table),
 226         },
 227 };
 228
 229 module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
 230
 231 MODULE_LICENSE("GPL");
 232 MODULE_AUTHOR("Tzachi Perelstein");
 233 MODULE_DESCRIPTION("NAND glue for Orion platforms");
 234 MODULE_ALIAS("platform:orion_nand");