drivers/net/dsa/mv88e6xxx/global2.c

   1 /*
   2  * Marvell 88E6xxx Switch Global 2 Registers support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   7  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/bitfield.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18
  19 #include "chip.h"
  20 #include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
  21 #include "global2.h"
  22
  23 static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
  24 {
  25         return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
  26 }
  27
  28 static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
  29 {
  30         return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
  31 }
  32
  33 static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
  34 {
  35         return mv88e6xxx_update(chip, chip->info->global2_addr, reg, update);
  36 }
  37
  38 static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
  39 {
  40         return mv88e6xxx_wait(chip, chip->info->global2_addr, reg, mask);
  41 }
  42
  43 /* Offset 0x00: Interrupt Source Register */
  44
  45 static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
  46 {
  47         /* Read (and clear most of) the Interrupt Source bits */
  48         return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
  49 }
  50
  51 /* Offset 0x01: Interrupt Mask Register */
  52
  53 static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
  54 {
  55         return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
  56 }
  57
  58 /* Offset 0x02: Management Enable 2x */
  59
  60 static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
  61 {
  62         return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
  63 }
  64
  65 /* Offset 0x03: Management Enable 0x */
  66
  67 static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
  68 {
  69         return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
  70 }
  71
  72 /* Offset 0x05: Switch Management Register */
  73
  74 static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
  75                                              bool enable)
  76 {
  77         u16 val;
  78         int err;
  79
  80         err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
  81         if (err)
  82                 return err;
  83
  84         if (enable)
  85                 val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
  86         else
  87                 val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
  88
  89         return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
  90 }
  91
  92 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
  93 {
  94         int err;
  95
  96         /* Consider the frames with reserved multicast destination
  97          * addresses matching 01:80:c2:00:00:0x as MGMT.
  98          */
  99         err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
 100         if (err)
 101                 return err;
 102
 103         return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
 104 }
 105
 106 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
 107 {
 108         int err;
 109
 110         /* Consider the frames with reserved multicast destination
 111          * addresses matching 01:80:c2:00:00:2x as MGMT.
 112          */
 113         err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
 114         if (err)
 115                 return err;
 116
 117         return mv88e6185_g2_mgmt_rsvd2cpu(chip);
 118 }
 119
 120 /* Offset 0x06: Device Mapping Table register */
 121
 122 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
 123                                              int target, int port)
 124 {
 125         u16 val = (target << 8) | (port & 0xf);
 126
 127         return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val);
 128 }
 129
 130 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
 131 {
 132         int target, port;
 133         int err;
 134
 135         /* Initialize the routing port to the 32 possible target devices */
 136         for (target = 0; target < 32; ++target) {
 137                 port = 0xf;
 138
 139                 if (target < DSA_MAX_SWITCHES) {
 140                         port = chip->ds->rtable[target];
 141                         if (port == DSA_RTABLE_NONE)
 142                                 port = 0xf;
 143                 }
 144
 145                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
 146                 if (err)
 147                         break;
 148         }
 149
 150         return err;
 151 }
 152
 153 /* Offset 0x07: Trunk Mask Table register */
 154
 155 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
 156                                          bool hash, u16 mask)
 157 {
 158         u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
 159
 160         if (hash)
 161                 val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
 162
 163         return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val);
 164 }
 165
 166 /* Offset 0x08: Trunk Mapping Table register */
 167
 168 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
 169                                             u16 map)
 170 {
 171         const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
 172         u16 val = (id << 11) | (map & port_mask);
 173
 174         return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val);
 175 }
 176
 177 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
 178 {
 179         const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
 180         int i, err;
 181
 182         /* Clear all eight possible Trunk Mask vectors */
 183         for (i = 0; i < 8; ++i) {
 184                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
 185                 if (err)
 186                         return err;
 187         }
 188
 189         /* Clear all sixteen possible Trunk ID routing vectors */
 190         for (i = 0; i < 16; ++i) {
 191                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
 192                 if (err)
 193                         return err;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /* Offset 0x09: Ingress Rate Command register
 200  * Offset 0x0A: Ingress Rate Data register
 201  */
 202
 203 static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
 204 {
 205         return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD,
 206                                  MV88E6XXX_G2_IRL_CMD_BUSY);
 207 }
 208
 209 static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
 210                                int res, int reg)
 211 {
 212         int err;
 213
 214         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
 215                                  MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
 216                                  (res << 5) | reg);
 217         if (err)
 218                 return err;
 219
 220         return mv88e6xxx_g2_irl_wait(chip);
 221 }
 222
 223 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
 224 {
 225         return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
 226                                    0, 0);
 227 }
 228
 229 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
 230 {
 231         return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
 232                                    0, 0);
 233 }
 234
 235 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
 236  * Offset 0x0C: Cross-chip Port VLAN Data Register
 237  */
 238
 239 static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
 240 {
 241         return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR,
 242                                  MV88E6XXX_G2_PVT_ADDR_BUSY);
 243 }
 244
 245 static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
 246                                int src_port, u16 op)
 247 {
 248         int err;
 249
 250         /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
 251          * cleared, source device is 5-bit, source port is 4-bit.
 252          */
 253         op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
 254         op |= (src_dev & 0x1f) << 4;
 255         op |= (src_port & 0xf);
 256
 257         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
 258         if (err)
 259                 return err;
 260
 261         return mv88e6xxx_g2_pvt_op_wait(chip);
 262 }
 263
 264 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
 265                            int src_port, u16 data)
 266 {
 267         int err;
 268
 269         err = mv88e6xxx_g2_pvt_op_wait(chip);
 270         if (err)
 271                 return err;
 272
 273         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
 274         if (err)
 275                 return err;
 276
 277         return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
 278                                    MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
 279 }
 280
 281 /* Offset 0x0D: Switch MAC/WoL/WoF register */
 282
 283 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
 284                                          unsigned int pointer, u8 data)
 285 {
 286         u16 val = (pointer << 8) | data;
 287
 288         return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val);
 289 }
 290
 291 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
 292 {
 293         int i, err;
 294
 295         for (i = 0; i < 6; i++) {
 296                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
 297                 if (err)
 298                         break;
 299         }
 300
 301         return err;
 302 }
 303
 304 /* Offset 0x0F: Priority Override Table */
 305
 306 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
 307                                   u8 data)
 308 {
 309         u16 val = (pointer << 8) | (data & 0x7);
 310
 311         return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
 312 }
 313
 314 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
 315 {
 316         int i, err;
 317
 318         /* Clear all sixteen possible Priority Override entries */
 319         for (i = 0; i < 16; i++) {
 320                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
 321                 if (err)
 322                         break;
 323         }
 324
 325         return err;
 326 }
 327
 328 /* Offset 0x14: EEPROM Command
 329  * Offset 0x15: EEPROM Data (for 16-bit data access)
 330  * Offset 0x15: EEPROM Addr (for 8-bit data access)
 331  */
 332
 333 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
 334 {
 335         return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD,
 336                                  MV88E6XXX_G2_EEPROM_CMD_BUSY |
 337                                  MV88E6XXX_G2_EEPROM_CMD_RUNNING);
 338 }
 339
 340 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
 341 {
 342         int err;
 343
 344         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
 345                                  MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
 346         if (err)
 347                 return err;
 348
 349         return mv88e6xxx_g2_eeprom_wait(chip);
 350 }
 351
 352 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
 353                                      u16 addr, u8 *data)
 354 {
 355         u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
 356         int err;
 357
 358         err = mv88e6xxx_g2_eeprom_wait(chip);
 359         if (err)
 360                 return err;
 361
 362         err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
 363         if (err)
 364                 return err;
 365
 366         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
 367         if (err)
 368                 return err;
 369
 370         err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
 371         if (err)
 372                 return err;
 373
 374         *data = cmd & 0xff;
 375
 376         return 0;
 377 }
 378
 379 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
 380                                       u16 addr, u8 data)
 381 {
 382         u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
 383                 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
 384         int err;
 385
 386         err = mv88e6xxx_g2_eeprom_wait(chip);
 387         if (err)
 388                 return err;
 389
 390         err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
 391         if (err)
 392                 return err;
 393
 394         return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
 395 }
 396
 397 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
 398                                       u8 addr, u16 *data)
 399 {
 400         u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
 401         int err;
 402
 403         err = mv88e6xxx_g2_eeprom_wait(chip);
 404         if (err)
 405                 return err;
 406
 407         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
 408         if (err)
 409                 return err;
 410
 411         return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
 412 }
 413
 414 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
 415                                        u8 addr, u16 data)
 416 {
 417         u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
 418         int err;
 419
 420         err = mv88e6xxx_g2_eeprom_wait(chip);
 421         if (err)
 422                 return err;
 423
 424         err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
 425         if (err)
 426                 return err;
 427
 428         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
 429 }
 430
 431 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 432                              struct ethtool_eeprom *eeprom, u8 *data)
 433 {
 434         unsigned int offset = eeprom->offset;
 435         unsigned int len = eeprom->len;
 436         int err;
 437
 438         eeprom->len = 0;
 439
 440         while (len) {
 441                 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
 442                 if (err)
 443                         return err;
 444
 445                 eeprom->len++;
 446                 offset++;
 447                 data++;
 448                 len--;
 449         }
 450
 451         return 0;
 452 }
 453
 454 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 455                              struct ethtool_eeprom *eeprom, u8 *data)
 456 {
 457         unsigned int offset = eeprom->offset;
 458         unsigned int len = eeprom->len;
 459         int err;
 460
 461         eeprom->len = 0;
 462
 463         while (len) {
 464                 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
 465                 if (err)
 466                         return err;
 467
 468                 eeprom->len++;
 469                 offset++;
 470                 data++;
 471                 len--;
 472         }
 473
 474         return 0;
 475 }
 476
 477 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 478                               struct ethtool_eeprom *eeprom, u8 *data)
 479 {
 480         unsigned int offset = eeprom->offset;
 481         unsigned int len = eeprom->len;
 482         u16 val;
 483         int err;
 484
 485         eeprom->len = 0;
 486
 487         if (offset & 1) {
 488                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
 489                 if (err)
 490                         return err;
 491
 492                 *data++ = (val >> 8) & 0xff;
 493
 494                 offset++;
 495                 len--;
 496                 eeprom->len++;
 497         }
 498
 499         while (len >= 2) {
 500                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
 501                 if (err)
 502                         return err;
 503
 504                 *data++ = val & 0xff;
 505                 *data++ = (val >> 8) & 0xff;
 506
 507                 offset += 2;
 508                 len -= 2;
 509                 eeprom->len += 2;
 510         }
 511
 512         if (len) {
 513                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
 514                 if (err)
 515                         return err;
 516
 517                 *data++ = val & 0xff;
 518
 519                 offset++;
 520                 len--;
 521                 eeprom->len++;
 522         }
 523
 524         return 0;
 525 }
 526
 527 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 528                               struct ethtool_eeprom *eeprom, u8 *data)
 529 {
 530         unsigned int offset = eeprom->offset;
 531         unsigned int len = eeprom->len;
 532         u16 val;
 533         int err;
 534
 535         /* Ensure the RO WriteEn bit is set */
 536         err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
 537         if (err)
 538                 return err;
 539
 540         if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
 541                 return -EROFS;
 542
 543         eeprom->len = 0;
 544
 545         if (offset & 1) {
 546                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
 547                 if (err)
 548                         return err;
 549
 550                 val = (*data++ << 8) | (val & 0xff);
 551
 552                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
 553                 if (err)
 554                         return err;
 555
 556                 offset++;
 557                 len--;
 558                 eeprom->len++;
 559         }
 560
 561         while (len >= 2) {
 562                 val = *data++;
 563                 val |= *data++ << 8;
 564
 565                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
 566                 if (err)
 567                         return err;
 568
 569                 offset += 2;
 570                 len -= 2;
 571                 eeprom->len += 2;
 572         }
 573
 574         if (len) {
 575                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
 576                 if (err)
 577                         return err;
 578
 579                 val = (val & 0xff00) | *data++;
 580
 581                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
 582                 if (err)
 583                         return err;
 584
 585                 offset++;
 586                 len--;
 587                 eeprom->len++;
 588         }
 589
 590         return 0;
 591 }
 592
 593 /* Offset 0x18: SMI PHY Command Register
 594  * Offset 0x19: SMI PHY Data Register
 595  */
 596
 597 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
 598 {
 599         return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD,
 600                                  MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
 601 }
 602
 603 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
 604 {
 605         int err;
 606
 607         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
 608                                  MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
 609         if (err)
 610                 return err;
 611
 612         return mv88e6xxx_g2_smi_phy_wait(chip);
 613 }
 614
 615 static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
 616                                        bool external, bool c45, u16 op, int dev,
 617                                        int reg)
 618 {
 619         u16 cmd = op;
 620
 621         if (external)
 622                 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
 623         else
 624                 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */
 625
 626         if (c45)
 627                 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */
 628         else
 629                 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
 630
 631         dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
 632         cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
 633         cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
 634
 635         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
 636 }
 637
 638 static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
 639                                            bool external, u16 op, int dev,
 640                                            int reg)
 641 {
 642         return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
 643 }
 644
 645 /* IEEE 802.3 Clause 22 Read Data Register */
 646 static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
 647                                               bool external, int dev, int reg,
 648                                               u16 *data)
 649 {
 650         u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
 651         int err;
 652
 653         err = mv88e6xxx_g2_smi_phy_wait(chip);
 654         if (err)
 655                 return err;
 656
 657         err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
 658         if (err)
 659                 return err;
 660
 661         return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
 662 }
 663
 664 /* IEEE 802.3 Clause 22 Write Data Register */
 665 static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
 666                                                bool external, int dev, int reg,
 667                                                u16 data)
 668 {
 669         u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
 670         int err;
 671
 672         err = mv88e6xxx_g2_smi_phy_wait(chip);
 673         if (err)
 674                 return err;
 675
 676         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
 677         if (err)
 678                 return err;
 679
 680         return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
 681 }
 682
 683 static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
 684                                            bool external, u16 op, int port,
 685                                            int dev)
 686 {
 687         return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
 688 }
 689
 690 /* IEEE 802.3 Clause 45 Write Address Register */
 691 static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
 692                                                bool external, int port, int dev,
 693                                                int addr)
 694 {
 695         u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
 696         int err;
 697
 698         err = mv88e6xxx_g2_smi_phy_wait(chip);
 699         if (err)
 700                 return err;
 701
 702         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
 703         if (err)
 704                 return err;
 705
 706         return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
 707 }
 708
 709 /* IEEE 802.3 Clause 45 Read Data Register */
 710 static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
 711                                               bool external, int port, int dev,
 712                                               u16 *data)
 713 {
 714         u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
 715         int err;
 716
 717         err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
 718         if (err)
 719                 return err;
 720
 721         return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
 722 }
 723
 724 static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
 725                                          bool external, int port, int reg,
 726                                          u16 *data)
 727 {
 728         int dev = (reg >> 16) & 0x1f;
 729         int addr = reg & 0xffff;
 730         int err;
 731
 732         err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
 733                                                   addr);
 734         if (err)
 735                 return err;
 736
 737         return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
 738                                                   data);
 739 }
 740
 741 /* IEEE 802.3 Clause 45 Write Data Register */
 742 static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
 743                                                bool external, int port, int dev,
 744                                                u16 data)
 745 {
 746         u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
 747         int err;
 748
 749         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
 750         if (err)
 751                 return err;
 752
 753         return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
 754 }
 755
 756 static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
 757                                           bool external, int port, int reg,
 758                                           u16 data)
 759 {
 760         int dev = (reg >> 16) & 0x1f;
 761         int addr = reg & 0xffff;
 762         int err;
 763
 764         err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
 765                                                   addr);
 766         if (err)
 767                 return err;
 768
 769         return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
 770                                                    data);
 771 }
 772
 773 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
 774                               int addr, int reg, u16 *val)
 775 {
 776         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
 777         bool external = mdio_bus->external;
 778
 779         if (reg & MII_ADDR_C45)
 780                 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
 781                                                      val);
 782
 783         return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
 784                                                   val);
 785 }
 786
 787 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
 788                                int addr, int reg, u16 val)
 789 {
 790         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
 791         bool external = mdio_bus->external;
 792
 793         if (reg & MII_ADDR_C45)
 794                 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
 795                                                       val);
 796
 797         return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
 798                                                    val);
 799 }
 800
 801 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
 802 {
 803         u16 reg;
 804
 805         mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, &reg);
 806
 807         dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
 808
 809         return IRQ_HANDLED;
 810 }
 811
 812 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
 813 {
 814         u16 reg;
 815
 816         mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, &reg);
 817
 818         reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
 819                  MV88E6352_G2_WDOG_CTL_QC_ENABLE);
 820
 821         mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
 822 }
 823
 824 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
 825 {
 826         return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
 827                                   MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
 828                                   MV88E6352_G2_WDOG_CTL_QC_ENABLE |
 829                                   MV88E6352_G2_WDOG_CTL_SWRESET);
 830 }
 831
 832 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
 833         .irq_action = mv88e6097_watchdog_action,
 834         .irq_setup = mv88e6097_watchdog_setup,
 835         .irq_free = mv88e6097_watchdog_free,
 836 };
 837
 838 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
 839 {
 840         return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
 841                                    MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
 842                                    MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
 843                                    MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
 844                                    MV88E6390_G2_WDOG_CTL_EGRESS |
 845                                    MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
 846 }
 847
 848 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
 849 {
 850         int err;
 851         u16 reg;
 852
 853         mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
 854                            MV88E6390_G2_WDOG_CTL_PTR_EVENT);
 855         err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, &reg);
 856
 857         dev_info(chip->dev, "Watchdog event: 0x%04x",
 858                  reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
 859
 860         mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
 861                            MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
 862         err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, &reg);
 863
 864         dev_info(chip->dev, "Watchdog history: 0x%04x",
 865                  reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
 866
 867         /* Trigger a software reset to try to recover the switch */
 868         if (chip->info->ops->reset)
 869                 chip->info->ops->reset(chip);
 870
 871         mv88e6390_watchdog_setup(chip);
 872
 873         return IRQ_HANDLED;
 874 }
 875
 876 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
 877 {
 878         mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
 879                             MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
 880 }
 881
 882 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
 883         .irq_action = mv88e6390_watchdog_action,
 884         .irq_setup = mv88e6390_watchdog_setup,
 885         .irq_free = mv88e6390_watchdog_free,
 886 };
 887
 888 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
 889 {
 890         struct mv88e6xxx_chip *chip = dev_id;
 891         irqreturn_t ret = IRQ_NONE;
 892
 893         mutex_lock(&chip->reg_lock);
 894         if (chip->info->ops->watchdog_ops->irq_action)
 895                 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
 896         mutex_unlock(&chip->reg_lock);
 897
 898         return ret;
 899 }
 900
 901 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
 902 {
 903         mutex_lock(&chip->reg_lock);
 904         if (chip->info->ops->watchdog_ops->irq_free)
 905                 chip->info->ops->watchdog_ops->irq_free(chip);
 906         mutex_unlock(&chip->reg_lock);
 907
 908         free_irq(chip->watchdog_irq, chip);
 909         irq_dispose_mapping(chip->watchdog_irq);
 910 }
 911
 912 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
 913 {
 914         int err;
 915
 916         chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
 917                                               MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
 918         if (chip->watchdog_irq < 0)
 919                 return chip->watchdog_irq;
 920
 921         err = request_threaded_irq(chip->watchdog_irq, NULL,
 922                                    mv88e6xxx_g2_watchdog_thread_fn,
 923                                    IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
 924                                    "mv88e6xxx-watchdog", chip);
 925         if (err)
 926                 return err;
 927
 928         mutex_lock(&chip->reg_lock);
 929         if (chip->info->ops->watchdog_ops->irq_setup)
 930                 err = chip->info->ops->watchdog_ops->irq_setup(chip);
 931         mutex_unlock(&chip->reg_lock);
 932
 933         return err;
 934 }
 935
 936 /* Offset 0x1D: Misc Register */
 937
 938 static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
 939                                         bool port_5_bit)
 940 {
 941         u16 val;
 942         int err;
 943
 944         err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
 945         if (err)
 946                 return err;
 947
 948         if (port_5_bit)
 949                 val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
 950         else
 951                 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
 952
 953         return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
 954 }
 955
 956 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
 957 {
 958         return mv88e6xxx_g2_misc_5_bit_port(chip, false);
 959 }
 960
 961 static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
 962 {
 963         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 964         unsigned int n = d->hwirq;
 965
 966         chip->g2_irq.masked |= (1 << n);
 967 }
 968
 969 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
 970 {
 971         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 972         unsigned int n = d->hwirq;
 973
 974         chip->g2_irq.masked &= ~(1 << n);
 975 }
 976
 977 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
 978 {
 979         struct mv88e6xxx_chip *chip = dev_id;
 980         unsigned int nhandled = 0;
 981         unsigned int sub_irq;
 982         unsigned int n;
 983         int err;
 984         u16 reg;
 985
 986         mutex_lock(&chip->reg_lock);
 987         err = mv88e6xxx_g2_int_source(chip, &reg);
 988         mutex_unlock(&chip->reg_lock);
 989         if (err)
 990                 goto out;
 991
 992         for (n = 0; n < 16; ++n) {
 993                 if (reg & (1 << n)) {
 994                         sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
 995                         handle_nested_irq(sub_irq);
 996                         ++nhandled;
 997                 }
 998         }
 999 out:
1000         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1001 }
1002
1003 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
1004 {
1005         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1006
1007         mutex_lock(&chip->reg_lock);
1008 }
1009
1010 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
1011 {
1012         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1013         int err;
1014
1015         err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1016         if (err)
1017                 dev_err(chip->dev, "failed to mask interrupts\n");
1018
1019         mutex_unlock(&chip->reg_lock);
1020 }
1021
1022 static const struct irq_chip mv88e6xxx_g2_irq_chip = {
1023         .name                   = "mv88e6xxx-g2",
1024         .irq_mask               = mv88e6xxx_g2_irq_mask,
1025         .irq_unmask             = mv88e6xxx_g2_irq_unmask,
1026         .irq_bus_lock           = mv88e6xxx_g2_irq_bus_lock,
1027         .irq_bus_sync_unlock    = mv88e6xxx_g2_irq_bus_sync_unlock,
1028 };
1029
1030 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
1031                                        unsigned int irq,
1032                                        irq_hw_number_t hwirq)
1033 {
1034         struct mv88e6xxx_chip *chip = d->host_data;
1035
1036         irq_set_chip_data(irq, d->host_data);
1037         irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1038         irq_set_noprobe(irq);
1039
1040         return 0;
1041 }
1042
1043 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
1044         .map    = mv88e6xxx_g2_irq_domain_map,
1045         .xlate  = irq_domain_xlate_twocell,
1046 };
1047
1048 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1049 {
1050         int irq, virq;
1051
1052         mv88e6xxx_g2_watchdog_free(chip);
1053
1054         free_irq(chip->device_irq, chip);
1055         irq_dispose_mapping(chip->device_irq);
1056
1057         for (irq = 0; irq < 16; irq++) {
1058                 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1059                 irq_dispose_mapping(virq);
1060         }
1061
1062         irq_domain_remove(chip->g2_irq.domain);
1063 }
1064
1065 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1066 {
1067         int err, irq, virq;
1068
1069         if (!chip->dev->of_node)
1070                 return -EINVAL;
1071
1072         chip->g2_irq.domain = irq_domain_add_simple(
1073                 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1074         if (!chip->g2_irq.domain)
1075                 return -ENOMEM;
1076
1077         for (irq = 0; irq < 16; irq++)
1078                 irq_create_mapping(chip->g2_irq.domain, irq);
1079
1080         chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1081         chip->g2_irq.masked = ~0;
1082
1083         chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1084                                             MV88E6XXX_G1_STS_IRQ_DEVICE);
1085         if (chip->device_irq < 0) {
1086                 err = chip->device_irq;
1087                 goto out;
1088         }
1089
1090         err = request_threaded_irq(chip->device_irq, NULL,
1091                                    mv88e6xxx_g2_irq_thread_fn,
1092                                    IRQF_ONESHOT, "mv88e6xxx-g1", chip);
1093         if (err)
1094                 goto out;
1095
1096         return mv88e6xxx_g2_watchdog_setup(chip);
1097
1098 out:
1099         for (irq = 0; irq < 16; irq++) {
1100                 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1101                 irq_dispose_mapping(virq);
1102         }
1103
1104         irq_domain_remove(chip->g2_irq.domain);
1105
1106         return err;
1107 }
1108
1109 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
1110 {
1111         u16 reg;
1112         int err;
1113
1114         /* Ignore removed tag data on doubly tagged packets, disable
1115          * flow control messages, force flow control priority to the
1116          * highest, and send all special multicast frames to the CPU
1117          * port at the highest priority.
1118          */
1119         reg = MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI | (0x7 << 4);
1120         err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, reg);
1121         if (err)
1122                 return err;
1123
1124         /* Program the DSA routing table. */
1125         err = mv88e6xxx_g2_set_device_mapping(chip);
1126         if (err)
1127                 return err;
1128
1129         /* Clear all trunk masks and mapping. */
1130         err = mv88e6xxx_g2_clear_trunk(chip);
1131         if (err)
1132                 return err;
1133
1134         return 0;
1135 }