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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
blob6975150d144e5ec8726d30cfe888b6888bb7a8b4
1 /*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #ifdef CONFIG_RFS_ACCEL
36 #include <linux/cpu_rmap.h>
37 #endif /* CONFIG_RFS_ACCEL */
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/numa.h>
44 #include <linux/pci.h>
45 #include <linux/utsname.h>
46 #include <linux/version.h>
47 #include <linux/vmalloc.h>
48 #include <net/ip.h>
49
50 #include "ena_netdev.h"
51 #include "ena_pci_id_tbl.h"
52
53 static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55 MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56 MODULE_DESCRIPTION(DEVICE_NAME);
57 MODULE_LICENSE("GPL");
58 MODULE_VERSION(DRV_MODULE_VERSION);
59
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (5 * HZ)
62
63 #define ENA_NAPI_BUDGET 64
64
65 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67 static int debug = -1;
68 module_param(debug, int, 0);
69 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71 static struct ena_aenq_handlers aenq_handlers;
72
73 static struct workqueue_struct *ena_wq;
74
75 MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77 static int ena_rss_init_default(struct ena_adapter *adapter);
78 static void check_for_admin_com_state(struct ena_adapter *adapter);
79 static void ena_destroy_device(struct ena_adapter *adapter);
80 static int ena_restore_device(struct ena_adapter *adapter);
81
82 static void ena_tx_timeout(struct net_device *dev)
83 {
84 struct ena_adapter *adapter = netdev_priv(dev);
85
86 /* Change the state of the device to trigger reset
87 * Check that we are not in the middle or a trigger already
88 */
89
90 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
91 return;
92
93 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
94 u64_stats_update_begin(&adapter->syncp);
95 adapter->dev_stats.tx_timeout++;
96 u64_stats_update_end(&adapter->syncp);
97
98 netif_err(adapter, tx_err, dev, "Transmit time out\n");
99 }
100
101 static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
102 {
103 int i;
104
105 for (i = 0; i < adapter->num_queues; i++)
106 adapter->rx_ring[i].mtu = mtu;
107 }
108
109 static int ena_change_mtu(struct net_device *dev, int new_mtu)
110 {
111 struct ena_adapter *adapter = netdev_priv(dev);
112 int ret;
113
114 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
115 if (!ret) {
116 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
117 update_rx_ring_mtu(adapter, new_mtu);
118 dev->mtu = new_mtu;
119 } else {
120 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
121 new_mtu);
122 }
123
124 return ret;
125 }
126
127 static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
128 {
129 #ifdef CONFIG_RFS_ACCEL
130 u32 i;
131 int rc;
132
133 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
134 if (!adapter->netdev->rx_cpu_rmap)
135 return -ENOMEM;
136 for (i = 0; i < adapter->num_queues; i++) {
137 int irq_idx = ENA_IO_IRQ_IDX(i);
138
139 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
140 pci_irq_vector(adapter->pdev, irq_idx));
141 if (rc) {
142 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
143 adapter->netdev->rx_cpu_rmap = NULL;
144 return rc;
145 }
146 }
147 #endif /* CONFIG_RFS_ACCEL */
148 return 0;
149 }
150
151 static void ena_init_io_rings_common(struct ena_adapter *adapter,
152 struct ena_ring *ring, u16 qid)
153 {
154 ring->qid = qid;
155 ring->pdev = adapter->pdev;
156 ring->dev = &adapter->pdev->dev;
157 ring->netdev = adapter->netdev;
158 ring->napi = &adapter->ena_napi[qid].napi;
159 ring->adapter = adapter;
160 ring->ena_dev = adapter->ena_dev;
161 ring->per_napi_packets = 0;
162 ring->per_napi_bytes = 0;
163 ring->cpu = 0;
164 ring->first_interrupt = false;
165 ring->no_interrupt_event_cnt = 0;
166 u64_stats_init(&ring->syncp);
167 }
168
169 static void ena_init_io_rings(struct ena_adapter *adapter)
170 {
171 struct ena_com_dev *ena_dev;
172 struct ena_ring *txr, *rxr;
173 int i;
174
175 ena_dev = adapter->ena_dev;
176
177 for (i = 0; i < adapter->num_queues; i++) {
178 txr = &adapter->tx_ring[i];
179 rxr = &adapter->rx_ring[i];
180
181 /* TX/RX common ring state */
182 ena_init_io_rings_common(adapter, txr, i);
183 ena_init_io_rings_common(adapter, rxr, i);
184
185 /* TX specific ring state */
186 txr->ring_size = adapter->tx_ring_size;
187 txr->tx_max_header_size = ena_dev->tx_max_header_size;
188 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
189 txr->sgl_size = adapter->max_tx_sgl_size;
190 txr->smoothed_interval =
191 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
192
193 /* RX specific ring state */
194 rxr->ring_size = adapter->rx_ring_size;
195 rxr->rx_copybreak = adapter->rx_copybreak;
196 rxr->sgl_size = adapter->max_rx_sgl_size;
197 rxr->smoothed_interval =
198 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
199 rxr->empty_rx_queue = 0;
200 }
201 }
202
203 /* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
204 * @adapter: network interface device structure
205 * @qid: queue index
206 *
207 * Return 0 on success, negative on failure
208 */
209 static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
210 {
211 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
212 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
213 int size, i, node;
214
215 if (tx_ring->tx_buffer_info) {
216 netif_err(adapter, ifup,
217 adapter->netdev, "tx_buffer_info info is not NULL");
218 return -EEXIST;
219 }
220
221 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
222 node = cpu_to_node(ena_irq->cpu);
223
224 tx_ring->tx_buffer_info = vzalloc_node(size, node);
225 if (!tx_ring->tx_buffer_info) {
226 tx_ring->tx_buffer_info = vzalloc(size);
227 if (!tx_ring->tx_buffer_info)
228 return -ENOMEM;
229 }
230
231 size = sizeof(u16) * tx_ring->ring_size;
232 tx_ring->free_tx_ids = vzalloc_node(size, node);
233 if (!tx_ring->free_tx_ids) {
234 tx_ring->free_tx_ids = vzalloc(size);
235 if (!tx_ring->free_tx_ids) {
236 vfree(tx_ring->tx_buffer_info);
237 return -ENOMEM;
238 }
239 }
240
241 /* Req id ring for TX out of order completions */
242 for (i = 0; i < tx_ring->ring_size; i++)
243 tx_ring->free_tx_ids[i] = i;
244
245 /* Reset tx statistics */
246 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
247
248 tx_ring->next_to_use = 0;
249 tx_ring->next_to_clean = 0;
250 tx_ring->cpu = ena_irq->cpu;
251 return 0;
252 }
253
254 /* ena_free_tx_resources - Free I/O Tx Resources per Queue
255 * @adapter: network interface device structure
256 * @qid: queue index
257 *
258 * Free all transmit software resources
259 */
260 static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
261 {
262 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
263
264 vfree(tx_ring->tx_buffer_info);
265 tx_ring->tx_buffer_info = NULL;
266
267 vfree(tx_ring->free_tx_ids);
268 tx_ring->free_tx_ids = NULL;
269 }
270
271 /* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
272 * @adapter: private structure
273 *
274 * Return 0 on success, negative on failure
275 */
276 static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
277 {
278 int i, rc = 0;
279
280 for (i = 0; i < adapter->num_queues; i++) {
281 rc = ena_setup_tx_resources(adapter, i);
282 if (rc)
283 goto err_setup_tx;
284 }
285
286 return 0;
287
288 err_setup_tx:
289
290 netif_err(adapter, ifup, adapter->netdev,
291 "Tx queue %d: allocation failed\n", i);
292
293 /* rewind the index freeing the rings as we go */
294 while (i--)
295 ena_free_tx_resources(adapter, i);
296 return rc;
297 }
298
299 /* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
300 * @adapter: board private structure
301 *
302 * Free all transmit software resources
303 */
304 static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
305 {
306 int i;
307
308 for (i = 0; i < adapter->num_queues; i++)
309 ena_free_tx_resources(adapter, i);
310 }
311
312 static inline int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id)
313 {
314 if (likely(req_id < rx_ring->ring_size))
315 return 0;
316
317 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
318 "Invalid rx req_id: %hu\n", req_id);
319
320 u64_stats_update_begin(&rx_ring->syncp);
321 rx_ring->rx_stats.bad_req_id++;
322 u64_stats_update_end(&rx_ring->syncp);
323
324 /* Trigger device reset */
325 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
326 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags);
327 return -EFAULT;
328 }
329
330 /* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
331 * @adapter: network interface device structure
332 * @qid: queue index
333 *
334 * Returns 0 on success, negative on failure
335 */
336 static int ena_setup_rx_resources(struct ena_adapter *adapter,
337 u32 qid)
338 {
339 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
340 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
341 int size, node, i;
342
343 if (rx_ring->rx_buffer_info) {
344 netif_err(adapter, ifup, adapter->netdev,
345 "rx_buffer_info is not NULL");
346 return -EEXIST;
347 }
348
349 /* alloc extra element so in rx path
350 * we can always prefetch rx_info + 1
351 */
352 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
353 node = cpu_to_node(ena_irq->cpu);
354
355 rx_ring->rx_buffer_info = vzalloc_node(size, node);
356 if (!rx_ring->rx_buffer_info) {
357 rx_ring->rx_buffer_info = vzalloc(size);
358 if (!rx_ring->rx_buffer_info)
359 return -ENOMEM;
360 }
361
362 size = sizeof(u16) * rx_ring->ring_size;
363 rx_ring->free_rx_ids = vzalloc_node(size, node);
364 if (!rx_ring->free_rx_ids) {
365 rx_ring->free_rx_ids = vzalloc(size);
366 if (!rx_ring->free_rx_ids) {
367 vfree(rx_ring->rx_buffer_info);
368 return -ENOMEM;
369 }
370 }
371
372 /* Req id ring for receiving RX pkts out of order */
373 for (i = 0; i < rx_ring->ring_size; i++)
374 rx_ring->free_rx_ids[i] = i;
375
376 /* Reset rx statistics */
377 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
378
379 rx_ring->next_to_clean = 0;
380 rx_ring->next_to_use = 0;
381 rx_ring->cpu = ena_irq->cpu;
382
383 return 0;
384 }
385
386 /* ena_free_rx_resources - Free I/O Rx Resources
387 * @adapter: network interface device structure
388 * @qid: queue index
389 *
390 * Free all receive software resources
391 */
392 static void ena_free_rx_resources(struct ena_adapter *adapter,
393 u32 qid)
394 {
395 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
396
397 vfree(rx_ring->rx_buffer_info);
398 rx_ring->rx_buffer_info = NULL;
399
400 vfree(rx_ring->free_rx_ids);
401 rx_ring->free_rx_ids = NULL;
402 }
403
404 /* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
405 * @adapter: board private structure
406 *
407 * Return 0 on success, negative on failure
408 */
409 static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
410 {
411 int i, rc = 0;
412
413 for (i = 0; i < adapter->num_queues; i++) {
414 rc = ena_setup_rx_resources(adapter, i);
415 if (rc)
416 goto err_setup_rx;
417 }
418
419 return 0;
420
421 err_setup_rx:
422
423 netif_err(adapter, ifup, adapter->netdev,
424 "Rx queue %d: allocation failed\n", i);
425
426 /* rewind the index freeing the rings as we go */
427 while (i--)
428 ena_free_rx_resources(adapter, i);
429 return rc;
430 }
431
432 /* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
433 * @adapter: board private structure
434 *
435 * Free all receive software resources
436 */
437 static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
438 {
439 int i;
440
441 for (i = 0; i < adapter->num_queues; i++)
442 ena_free_rx_resources(adapter, i);
443 }
444
445 static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
446 struct ena_rx_buffer *rx_info, gfp_t gfp)
447 {
448 struct ena_com_buf *ena_buf;
449 struct page *page;
450 dma_addr_t dma;
451
452 /* if previous allocated page is not used */
453 if (unlikely(rx_info->page))
454 return 0;
455
456 page = alloc_page(gfp);
457 if (unlikely(!page)) {
458 u64_stats_update_begin(&rx_ring->syncp);
459 rx_ring->rx_stats.page_alloc_fail++;
460 u64_stats_update_end(&rx_ring->syncp);
461 return -ENOMEM;
462 }
463
464 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
465 DMA_FROM_DEVICE);
466 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
467 u64_stats_update_begin(&rx_ring->syncp);
468 rx_ring->rx_stats.dma_mapping_err++;
469 u64_stats_update_end(&rx_ring->syncp);
470
471 __free_page(page);
472 return -EIO;
473 }
474 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
475 "alloc page %p, rx_info %p\n", page, rx_info);
476
477 rx_info->page = page;
478 rx_info->page_offset = 0;
479 ena_buf = &rx_info->ena_buf;
480 ena_buf->paddr = dma;
481 ena_buf->len = PAGE_SIZE;
482
483 return 0;
484 }
485
486 static void ena_free_rx_page(struct ena_ring *rx_ring,
487 struct ena_rx_buffer *rx_info)
488 {
489 struct page *page = rx_info->page;
490 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
491
492 if (unlikely(!page)) {
493 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
494 "Trying to free unallocated buffer\n");
495 return;
496 }
497
498 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
499 DMA_FROM_DEVICE);
500
501 __free_page(page);
502 rx_info->page = NULL;
503 }
504
505 static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
506 {
507 u16 next_to_use, req_id;
508 u32 i;
509 int rc;
510
511 next_to_use = rx_ring->next_to_use;
512
513 for (i = 0; i < num; i++) {
514 struct ena_rx_buffer *rx_info;
515
516 req_id = rx_ring->free_rx_ids[next_to_use];
517 rc = validate_rx_req_id(rx_ring, req_id);
518 if (unlikely(rc < 0))
519 break;
520
521 rx_info = &rx_ring->rx_buffer_info[req_id];
522
523
524 rc = ena_alloc_rx_page(rx_ring, rx_info,
525 GFP_ATOMIC | __GFP_COMP);
526 if (unlikely(rc < 0)) {
527 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
528 "failed to alloc buffer for rx queue %d\n",
529 rx_ring->qid);
530 break;
531 }
532 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
533 &rx_info->ena_buf,
534 req_id);
535 if (unlikely(rc)) {
536 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
537 "failed to add buffer for rx queue %d\n",
538 rx_ring->qid);
539 break;
540 }
541 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
542 rx_ring->ring_size);
543 }
544
545 if (unlikely(i < num)) {
546 u64_stats_update_begin(&rx_ring->syncp);
547 rx_ring->rx_stats.refil_partial++;
548 u64_stats_update_end(&rx_ring->syncp);
549 netdev_warn(rx_ring->netdev,
550 "refilled rx qid %d with only %d buffers (from %d)\n",
551 rx_ring->qid, i, num);
552 }
553
554 if (likely(i)) {
555 /* Add memory barrier to make sure the desc were written before
556 * issue a doorbell
557 */
558 wmb();
559 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
560 }
561
562 rx_ring->next_to_use = next_to_use;
563
564 return i;
565 }
566
567 static void ena_free_rx_bufs(struct ena_adapter *adapter,
568 u32 qid)
569 {
570 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
571 u32 i;
572
573 for (i = 0; i < rx_ring->ring_size; i++) {
574 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
575
576 if (rx_info->page)
577 ena_free_rx_page(rx_ring, rx_info);
578 }
579 }
580
581 /* ena_refill_all_rx_bufs - allocate all queues Rx buffers
582 * @adapter: board private structure
583 *
584 */
585 static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
586 {
587 struct ena_ring *rx_ring;
588 int i, rc, bufs_num;
589
590 for (i = 0; i < adapter->num_queues; i++) {
591 rx_ring = &adapter->rx_ring[i];
592 bufs_num = rx_ring->ring_size - 1;
593 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
594
595 if (unlikely(rc != bufs_num))
596 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
597 "refilling Queue %d failed. allocated %d buffers from: %d\n",
598 i, rc, bufs_num);
599 }
600 }
601
602 static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
603 {
604 int i;
605
606 for (i = 0; i < adapter->num_queues; i++)
607 ena_free_rx_bufs(adapter, i);
608 }
609
610 /* ena_free_tx_bufs - Free Tx Buffers per Queue
611 * @tx_ring: TX ring for which buffers be freed
612 */
613 static void ena_free_tx_bufs(struct ena_ring *tx_ring)
614 {
615 bool print_once = true;
616 u32 i;
617
618 for (i = 0; i < tx_ring->ring_size; i++) {
619 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
620 struct ena_com_buf *ena_buf;
621 int nr_frags;
622 int j;
623
624 if (!tx_info->skb)
625 continue;
626
627 if (print_once) {
628 netdev_notice(tx_ring->netdev,
629 "free uncompleted tx skb qid %d idx 0x%x\n",
630 tx_ring->qid, i);
631 print_once = false;
632 } else {
633 netdev_dbg(tx_ring->netdev,
634 "free uncompleted tx skb qid %d idx 0x%x\n",
635 tx_ring->qid, i);
636 }
637
638 ena_buf = tx_info->bufs;
639 dma_unmap_single(tx_ring->dev,
640 ena_buf->paddr,
641 ena_buf->len,
642 DMA_TO_DEVICE);
643
644 /* unmap remaining mapped pages */
645 nr_frags = tx_info->num_of_bufs - 1;
646 for (j = 0; j < nr_frags; j++) {
647 ena_buf++;
648 dma_unmap_page(tx_ring->dev,
649 ena_buf->paddr,
650 ena_buf->len,
651 DMA_TO_DEVICE);
652 }
653
654 dev_kfree_skb_any(tx_info->skb);
655 }
656 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
657 tx_ring->qid));
658 }
659
660 static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
661 {
662 struct ena_ring *tx_ring;
663 int i;
664
665 for (i = 0; i < adapter->num_queues; i++) {
666 tx_ring = &adapter->tx_ring[i];
667 ena_free_tx_bufs(tx_ring);
668 }
669 }
670
671 static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
672 {
673 u16 ena_qid;
674 int i;
675
676 for (i = 0; i < adapter->num_queues; i++) {
677 ena_qid = ENA_IO_TXQ_IDX(i);
678 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
679 }
680 }
681
682 static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
683 {
684 u16 ena_qid;
685 int i;
686
687 for (i = 0; i < adapter->num_queues; i++) {
688 ena_qid = ENA_IO_RXQ_IDX(i);
689 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
690 }
691 }
692
693 static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
694 {
695 ena_destroy_all_tx_queues(adapter);
696 ena_destroy_all_rx_queues(adapter);
697 }
698
699 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
700 {
701 struct ena_tx_buffer *tx_info = NULL;
702
703 if (likely(req_id < tx_ring->ring_size)) {
704 tx_info = &tx_ring->tx_buffer_info[req_id];
705 if (likely(tx_info->skb))
706 return 0;
707 }
708
709 if (tx_info)
710 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
711 "tx_info doesn't have valid skb\n");
712 else
713 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
714 "Invalid req_id: %hu\n", req_id);
715
716 u64_stats_update_begin(&tx_ring->syncp);
717 tx_ring->tx_stats.bad_req_id++;
718 u64_stats_update_end(&tx_ring->syncp);
719
720 /* Trigger device reset */
721 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
722 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
723 return -EFAULT;
724 }
725
726 static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
727 {
728 struct netdev_queue *txq;
729 bool above_thresh;
730 u32 tx_bytes = 0;
731 u32 total_done = 0;
732 u16 next_to_clean;
733 u16 req_id;
734 int tx_pkts = 0;
735 int rc;
736
737 next_to_clean = tx_ring->next_to_clean;
738 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
739
740 while (tx_pkts < budget) {
741 struct ena_tx_buffer *tx_info;
742 struct sk_buff *skb;
743 struct ena_com_buf *ena_buf;
744 int i, nr_frags;
745
746 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
747 &req_id);
748 if (rc)
749 break;
750
751 rc = validate_tx_req_id(tx_ring, req_id);
752 if (rc)
753 break;
754
755 tx_info = &tx_ring->tx_buffer_info[req_id];
756 skb = tx_info->skb;
757
758 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
759 prefetch(&skb->end);
760
761 tx_info->skb = NULL;
762 tx_info->last_jiffies = 0;
763
764 if (likely(tx_info->num_of_bufs != 0)) {
765 ena_buf = tx_info->bufs;
766
767 dma_unmap_single(tx_ring->dev,
768 dma_unmap_addr(ena_buf, paddr),
769 dma_unmap_len(ena_buf, len),
770 DMA_TO_DEVICE);
771
772 /* unmap remaining mapped pages */
773 nr_frags = tx_info->num_of_bufs - 1;
774 for (i = 0; i < nr_frags; i++) {
775 ena_buf++;
776 dma_unmap_page(tx_ring->dev,
777 dma_unmap_addr(ena_buf, paddr),
778 dma_unmap_len(ena_buf, len),
779 DMA_TO_DEVICE);
780 }
781 }
782
783 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
784 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
785 skb);
786
787 tx_bytes += skb->len;
788 dev_kfree_skb(skb);
789 tx_pkts++;
790 total_done += tx_info->tx_descs;
791
792 tx_ring->free_tx_ids[next_to_clean] = req_id;
793 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
794 tx_ring->ring_size);
795 }
796
797 tx_ring->next_to_clean = next_to_clean;
798 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
799 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
800
801 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
802
803 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
804 "tx_poll: q %d done. total pkts: %d\n",
805 tx_ring->qid, tx_pkts);
806
807 /* need to make the rings circular update visible to
808 * ena_start_xmit() before checking for netif_queue_stopped().
809 */
810 smp_mb();
811
812 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
813 ENA_TX_WAKEUP_THRESH;
814 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
815 __netif_tx_lock(txq, smp_processor_id());
816 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
817 ENA_TX_WAKEUP_THRESH;
818 if (netif_tx_queue_stopped(txq) && above_thresh) {
819 netif_tx_wake_queue(txq);
820 u64_stats_update_begin(&tx_ring->syncp);
821 tx_ring->tx_stats.queue_wakeup++;
822 u64_stats_update_end(&tx_ring->syncp);
823 }
824 __netif_tx_unlock(txq);
825 }
826
827 tx_ring->per_napi_bytes += tx_bytes;
828 tx_ring->per_napi_packets += tx_pkts;
829
830 return tx_pkts;
831 }
832
833 static struct sk_buff *ena_alloc_skb(struct ena_ring *rx_ring, bool frags)
834 {
835 struct sk_buff *skb;
836
837 if (frags)
838 skb = napi_get_frags(rx_ring->napi);
839 else
840 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
841 rx_ring->rx_copybreak);
842
843 if (unlikely(!skb)) {
844 u64_stats_update_begin(&rx_ring->syncp);
845 rx_ring->rx_stats.skb_alloc_fail++;
846 u64_stats_update_end(&rx_ring->syncp);
847 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
848 "Failed to allocate skb. frags: %d\n", frags);
849 return NULL;
850 }
851
852 return skb;
853 }
854
855 static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
856 struct ena_com_rx_buf_info *ena_bufs,
857 u32 descs,
858 u16 *next_to_clean)
859 {
860 struct sk_buff *skb;
861 struct ena_rx_buffer *rx_info;
862 u16 len, req_id, buf = 0;
863 void *va;
864
865 len = ena_bufs[buf].len;
866 req_id = ena_bufs[buf].req_id;
867 rx_info = &rx_ring->rx_buffer_info[req_id];
868
869 if (unlikely(!rx_info->page)) {
870 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
871 "Page is NULL\n");
872 return NULL;
873 }
874
875 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
876 "rx_info %p page %p\n",
877 rx_info, rx_info->page);
878
879 /* save virt address of first buffer */
880 va = page_address(rx_info->page) + rx_info->page_offset;
881 prefetch(va + NET_IP_ALIGN);
882
883 if (len <= rx_ring->rx_copybreak) {
884 skb = ena_alloc_skb(rx_ring, false);
885 if (unlikely(!skb))
886 return NULL;
887
888 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
889 "rx allocated small packet. len %d. data_len %d\n",
890 skb->len, skb->data_len);
891
892 /* sync this buffer for CPU use */
893 dma_sync_single_for_cpu(rx_ring->dev,
894 dma_unmap_addr(&rx_info->ena_buf, paddr),
895 len,
896 DMA_FROM_DEVICE);
897 skb_copy_to_linear_data(skb, va, len);
898 dma_sync_single_for_device(rx_ring->dev,
899 dma_unmap_addr(&rx_info->ena_buf, paddr),
900 len,
901 DMA_FROM_DEVICE);
902
903 skb_put(skb, len);
904 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
905 rx_ring->free_rx_ids[*next_to_clean] = req_id;
906 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
907 rx_ring->ring_size);
908 return skb;
909 }
910
911 skb = ena_alloc_skb(rx_ring, true);
912 if (unlikely(!skb))
913 return NULL;
914
915 do {
916 dma_unmap_page(rx_ring->dev,
917 dma_unmap_addr(&rx_info->ena_buf, paddr),
918 PAGE_SIZE, DMA_FROM_DEVICE);
919
920 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
921 rx_info->page_offset, len, PAGE_SIZE);
922
923 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
924 "rx skb updated. len %d. data_len %d\n",
925 skb->len, skb->data_len);
926
927 rx_info->page = NULL;
928
929 rx_ring->free_rx_ids[*next_to_clean] = req_id;
930 *next_to_clean =
931 ENA_RX_RING_IDX_NEXT(*next_to_clean,
932 rx_ring->ring_size);
933 if (likely(--descs == 0))
934 break;
935
936 buf++;
937 len = ena_bufs[buf].len;
938 req_id = ena_bufs[buf].req_id;
939 rx_info = &rx_ring->rx_buffer_info[req_id];
940 } while (1);
941
942 return skb;
943 }
944
945 /* ena_rx_checksum - indicate in skb if hw indicated a good cksum
946 * @adapter: structure containing adapter specific data
947 * @ena_rx_ctx: received packet context/metadata
948 * @skb: skb currently being received and modified
949 */
950 static inline void ena_rx_checksum(struct ena_ring *rx_ring,
951 struct ena_com_rx_ctx *ena_rx_ctx,
952 struct sk_buff *skb)
953 {
954 /* Rx csum disabled */
955 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
956 skb->ip_summed = CHECKSUM_NONE;
957 return;
958 }
959
960 /* For fragmented packets the checksum isn't valid */
961 if (ena_rx_ctx->frag) {
962 skb->ip_summed = CHECKSUM_NONE;
963 return;
964 }
965
966 /* if IP and error */
967 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
968 (ena_rx_ctx->l3_csum_err))) {
969 /* ipv4 checksum error */
970 skb->ip_summed = CHECKSUM_NONE;
971 u64_stats_update_begin(&rx_ring->syncp);
972 rx_ring->rx_stats.bad_csum++;
973 u64_stats_update_end(&rx_ring->syncp);
974 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
975 "RX IPv4 header checksum error\n");
976 return;
977 }
978
979 /* if TCP/UDP */
980 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
981 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
982 if (unlikely(ena_rx_ctx->l4_csum_err)) {
983 /* TCP/UDP checksum error */
984 u64_stats_update_begin(&rx_ring->syncp);
985 rx_ring->rx_stats.bad_csum++;
986 u64_stats_update_end(&rx_ring->syncp);
987 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
988 "RX L4 checksum error\n");
989 skb->ip_summed = CHECKSUM_NONE;
990 return;
991 }
992
993 skb->ip_summed = CHECKSUM_UNNECESSARY;
994 }
995 }
996
997 static void ena_set_rx_hash(struct ena_ring *rx_ring,
998 struct ena_com_rx_ctx *ena_rx_ctx,
999 struct sk_buff *skb)
1000 {
1001 enum pkt_hash_types hash_type;
1002
1003 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
1004 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
1005 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
1006
1007 hash_type = PKT_HASH_TYPE_L4;
1008 else
1009 hash_type = PKT_HASH_TYPE_NONE;
1010
1011 /* Override hash type if the packet is fragmented */
1012 if (ena_rx_ctx->frag)
1013 hash_type = PKT_HASH_TYPE_NONE;
1014
1015 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
1016 }
1017 }
1018
1019 /* ena_clean_rx_irq - Cleanup RX irq
1020 * @rx_ring: RX ring to clean
1021 * @napi: napi handler
1022 * @budget: how many packets driver is allowed to clean
1023 *
1024 * Returns the number of cleaned buffers.
1025 */
1026 static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
1027 u32 budget)
1028 {
1029 u16 next_to_clean = rx_ring->next_to_clean;
1030 u32 res_budget, work_done;
1031
1032 struct ena_com_rx_ctx ena_rx_ctx;
1033 struct ena_adapter *adapter;
1034 struct sk_buff *skb;
1035 int refill_required;
1036 int refill_threshold;
1037 int rc = 0;
1038 int total_len = 0;
1039 int rx_copybreak_pkt = 0;
1040 int i;
1041
1042 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1043 "%s qid %d\n", __func__, rx_ring->qid);
1044 res_budget = budget;
1045
1046 do {
1047 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1048 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1049 ena_rx_ctx.descs = 0;
1050 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1051 rx_ring->ena_com_io_sq,
1052 &ena_rx_ctx);
1053 if (unlikely(rc))
1054 goto error;
1055
1056 if (unlikely(ena_rx_ctx.descs == 0))
1057 break;
1058
1059 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1060 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
1061 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
1062 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
1063
1064 /* allocate skb and fill it */
1065 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1066 &next_to_clean);
1067
1068 /* exit if we failed to retrieve a buffer */
1069 if (unlikely(!skb)) {
1070 for (i = 0; i < ena_rx_ctx.descs; i++) {
1071 rx_ring->free_tx_ids[next_to_clean] =
1072 rx_ring->ena_bufs[i].req_id;
1073 next_to_clean =
1074 ENA_RX_RING_IDX_NEXT(next_to_clean,
1075 rx_ring->ring_size);
1076 }
1077 break;
1078 }
1079
1080 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1081
1082 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1083
1084 skb_record_rx_queue(skb, rx_ring->qid);
1085
1086 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1087 total_len += rx_ring->ena_bufs[0].len;
1088 rx_copybreak_pkt++;
1089 napi_gro_receive(napi, skb);
1090 } else {
1091 total_len += skb->len;
1092 napi_gro_frags(napi);
1093 }
1094
1095 res_budget--;
1096 } while (likely(res_budget));
1097
1098 work_done = budget - res_budget;
1099 rx_ring->per_napi_bytes += total_len;
1100 rx_ring->per_napi_packets += work_done;
1101 u64_stats_update_begin(&rx_ring->syncp);
1102 rx_ring->rx_stats.bytes += total_len;
1103 rx_ring->rx_stats.cnt += work_done;
1104 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1105 u64_stats_update_end(&rx_ring->syncp);
1106
1107 rx_ring->next_to_clean = next_to_clean;
1108
1109 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1110 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1111
1112 /* Optimization, try to batch new rx buffers */
1113 if (refill_required > refill_threshold) {
1114 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1115 ena_refill_rx_bufs(rx_ring, refill_required);
1116 }
1117
1118 return work_done;
1119
1120 error:
1121 adapter = netdev_priv(rx_ring->netdev);
1122
1123 u64_stats_update_begin(&rx_ring->syncp);
1124 rx_ring->rx_stats.bad_desc_num++;
1125 u64_stats_update_end(&rx_ring->syncp);
1126
1127 /* Too many desc from the device. Trigger reset */
1128 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1129 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1130
1131 return 0;
1132 }
1133
1134 inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1135 struct ena_ring *tx_ring)
1136 {
1137 /* We apply adaptive moderation on Rx path only.
1138 * Tx uses static interrupt moderation.
1139 */
1140 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1141 rx_ring->per_napi_packets,
1142 rx_ring->per_napi_bytes,
1143 &rx_ring->smoothed_interval,
1144 &rx_ring->moder_tbl_idx);
1145
1146 /* Reset per napi packets/bytes */
1147 tx_ring->per_napi_packets = 0;
1148 tx_ring->per_napi_bytes = 0;
1149 rx_ring->per_napi_packets = 0;
1150 rx_ring->per_napi_bytes = 0;
1151 }
1152
1153 static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
1154 struct ena_ring *rx_ring)
1155 {
1156 struct ena_eth_io_intr_reg intr_reg;
1157
1158 /* Update intr register: rx intr delay,
1159 * tx intr delay and interrupt unmask
1160 */
1161 ena_com_update_intr_reg(&intr_reg,
1162 rx_ring->smoothed_interval,
1163 tx_ring->smoothed_interval,
1164 true);
1165
1166 /* It is a shared MSI-X.
1167 * Tx and Rx CQ have pointer to it.
1168 * So we use one of them to reach the intr reg
1169 */
1170 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1171 }
1172
1173 static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1174 struct ena_ring *rx_ring)
1175 {
1176 int cpu = get_cpu();
1177 int numa_node;
1178
1179 /* Check only one ring since the 2 rings are running on the same cpu */
1180 if (likely(tx_ring->cpu == cpu))
1181 goto out;
1182
1183 numa_node = cpu_to_node(cpu);
1184 put_cpu();
1185
1186 if (numa_node != NUMA_NO_NODE) {
1187 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1188 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1189 }
1190
1191 tx_ring->cpu = cpu;
1192 rx_ring->cpu = cpu;
1193
1194 return;
1195 out:
1196 put_cpu();
1197 }
1198
1199 static int ena_io_poll(struct napi_struct *napi, int budget)
1200 {
1201 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1202 struct ena_ring *tx_ring, *rx_ring;
1203
1204 u32 tx_work_done;
1205 u32 rx_work_done;
1206 int tx_budget;
1207 int napi_comp_call = 0;
1208 int ret;
1209
1210 tx_ring = ena_napi->tx_ring;
1211 rx_ring = ena_napi->rx_ring;
1212
1213 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1214
1215 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1216 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1217 napi_complete_done(napi, 0);
1218 return 0;
1219 }
1220
1221 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1222 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1223
1224 /* If the device is about to reset or down, avoid unmask
1225 * the interrupt and return 0 so NAPI won't reschedule
1226 */
1227 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1228 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1229 napi_complete_done(napi, 0);
1230 ret = 0;
1231
1232 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1233 napi_comp_call = 1;
1234
1235 /* Update numa and unmask the interrupt only when schedule
1236 * from the interrupt context (vs from sk_busy_loop)
1237 */
1238 if (napi_complete_done(napi, rx_work_done)) {
1239 /* Tx and Rx share the same interrupt vector */
1240 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1241 ena_adjust_intr_moderation(rx_ring, tx_ring);
1242
1243 ena_unmask_interrupt(tx_ring, rx_ring);
1244 }
1245
1246 ena_update_ring_numa_node(tx_ring, rx_ring);
1247
1248 ret = rx_work_done;
1249 } else {
1250 ret = budget;
1251 }
1252
1253 u64_stats_update_begin(&tx_ring->syncp);
1254 tx_ring->tx_stats.napi_comp += napi_comp_call;
1255 tx_ring->tx_stats.tx_poll++;
1256 u64_stats_update_end(&tx_ring->syncp);
1257
1258 return ret;
1259 }
1260
1261 static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1262 {
1263 struct ena_adapter *adapter = (struct ena_adapter *)data;
1264
1265 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1266
1267 /* Don't call the aenq handler before probe is done */
1268 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1269 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1270
1271 return IRQ_HANDLED;
1272 }
1273
1274 /* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1275 * @irq: interrupt number
1276 * @data: pointer to a network interface private napi device structure
1277 */
1278 static irqreturn_t ena_intr_msix_io(int irq, void *data)
1279 {
1280 struct ena_napi *ena_napi = data;
1281
1282 ena_napi->tx_ring->first_interrupt = true;
1283 ena_napi->rx_ring->first_interrupt = true;
1284
1285 napi_schedule_irqoff(&ena_napi->napi);
1286
1287 return IRQ_HANDLED;
1288 }
1289
1290 /* Reserve a single MSI-X vector for management (admin + aenq).
1291 * plus reserve one vector for each potential io queue.
1292 * the number of potential io queues is the minimum of what the device
1293 * supports and the number of vCPUs.
1294 */
1295 static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1296 {
1297 int msix_vecs, irq_cnt;
1298
1299 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1300 netif_err(adapter, probe, adapter->netdev,
1301 "Error, MSI-X is already enabled\n");
1302 return -EPERM;
1303 }
1304
1305 /* Reserved the max msix vectors we might need */
1306 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1307
1308 netif_dbg(adapter, probe, adapter->netdev,
1309 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1310
1311 irq_cnt = pci_alloc_irq_vectors(adapter->pdev, ENA_MIN_MSIX_VEC,
1312 msix_vecs, PCI_IRQ_MSIX);
1313
1314 if (irq_cnt < 0) {
1315 netif_err(adapter, probe, adapter->netdev,
1316 "Failed to enable MSI-X. irq_cnt %d\n", irq_cnt);
1317 return -ENOSPC;
1318 }
1319
1320 if (irq_cnt != msix_vecs) {
1321 netif_notice(adapter, probe, adapter->netdev,
1322 "enable only %d MSI-X (out of %d), reduce the number of queues\n",
1323 irq_cnt, msix_vecs);
1324 adapter->num_queues = irq_cnt - ENA_ADMIN_MSIX_VEC;
1325 }
1326
1327 if (ena_init_rx_cpu_rmap(adapter))
1328 netif_warn(adapter, probe, adapter->netdev,
1329 "Failed to map IRQs to CPUs\n");
1330
1331 adapter->msix_vecs = irq_cnt;
1332 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags);
1333
1334 return 0;
1335 }
1336
1337 static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1338 {
1339 u32 cpu;
1340
1341 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1342 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1343 pci_name(adapter->pdev));
1344 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1345 ena_intr_msix_mgmnt;
1346 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1347 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
1348 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1349 cpu = cpumask_first(cpu_online_mask);
1350 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1351 cpumask_set_cpu(cpu,
1352 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1353 }
1354
1355 static void ena_setup_io_intr(struct ena_adapter *adapter)
1356 {
1357 struct net_device *netdev;
1358 int irq_idx, i, cpu;
1359
1360 netdev = adapter->netdev;
1361
1362 for (i = 0; i < adapter->num_queues; i++) {
1363 irq_idx = ENA_IO_IRQ_IDX(i);
1364 cpu = i % num_online_cpus();
1365
1366 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1367 "%s-Tx-Rx-%d", netdev->name, i);
1368 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1369 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1370 adapter->irq_tbl[irq_idx].vector =
1371 pci_irq_vector(adapter->pdev, irq_idx);
1372 adapter->irq_tbl[irq_idx].cpu = cpu;
1373
1374 cpumask_set_cpu(cpu,
1375 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1376 }
1377 }
1378
1379 static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1380 {
1381 unsigned long flags = 0;
1382 struct ena_irq *irq;
1383 int rc;
1384
1385 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1386 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1387 irq->data);
1388 if (rc) {
1389 netif_err(adapter, probe, adapter->netdev,
1390 "failed to request admin irq\n");
1391 return rc;
1392 }
1393
1394 netif_dbg(adapter, probe, adapter->netdev,
1395 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1396 irq->affinity_hint_mask.bits[0], irq->vector);
1397
1398 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1399
1400 return rc;
1401 }
1402
1403 static int ena_request_io_irq(struct ena_adapter *adapter)
1404 {
1405 unsigned long flags = 0;
1406 struct ena_irq *irq;
1407 int rc = 0, i, k;
1408
1409 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1410 netif_err(adapter, ifup, adapter->netdev,
1411 "Failed to request I/O IRQ: MSI-X is not enabled\n");
1412 return -EINVAL;
1413 }
1414
1415 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1416 irq = &adapter->irq_tbl[i];
1417 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1418 irq->data);
1419 if (rc) {
1420 netif_err(adapter, ifup, adapter->netdev,
1421 "Failed to request I/O IRQ. index %d rc %d\n",
1422 i, rc);
1423 goto err;
1424 }
1425
1426 netif_dbg(adapter, ifup, adapter->netdev,
1427 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1428 i, irq->affinity_hint_mask.bits[0], irq->vector);
1429
1430 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1431 }
1432
1433 return rc;
1434
1435 err:
1436 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1437 irq = &adapter->irq_tbl[k];
1438 free_irq(irq->vector, irq->data);
1439 }
1440
1441 return rc;
1442 }
1443
1444 static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1445 {
1446 struct ena_irq *irq;
1447
1448 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1449 synchronize_irq(irq->vector);
1450 irq_set_affinity_hint(irq->vector, NULL);
1451 free_irq(irq->vector, irq->data);
1452 }
1453
1454 static void ena_free_io_irq(struct ena_adapter *adapter)
1455 {
1456 struct ena_irq *irq;
1457 int i;
1458
1459 #ifdef CONFIG_RFS_ACCEL
1460 if (adapter->msix_vecs >= 1) {
1461 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1462 adapter->netdev->rx_cpu_rmap = NULL;
1463 }
1464 #endif /* CONFIG_RFS_ACCEL */
1465
1466 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1467 irq = &adapter->irq_tbl[i];
1468 irq_set_affinity_hint(irq->vector, NULL);
1469 free_irq(irq->vector, irq->data);
1470 }
1471 }
1472
1473 static void ena_disable_msix(struct ena_adapter *adapter)
1474 {
1475 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags))
1476 pci_free_irq_vectors(adapter->pdev);
1477 }
1478
1479 static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1480 {
1481 int i;
1482
1483 if (!netif_running(adapter->netdev))
1484 return;
1485
1486 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1487 synchronize_irq(adapter->irq_tbl[i].vector);
1488 }
1489
1490 static void ena_del_napi(struct ena_adapter *adapter)
1491 {
1492 int i;
1493
1494 for (i = 0; i < adapter->num_queues; i++)
1495 netif_napi_del(&adapter->ena_napi[i].napi);
1496 }
1497
1498 static void ena_init_napi(struct ena_adapter *adapter)
1499 {
1500 struct ena_napi *napi;
1501 int i;
1502
1503 for (i = 0; i < adapter->num_queues; i++) {
1504 napi = &adapter->ena_napi[i];
1505
1506 netif_napi_add(adapter->netdev,
1507 &adapter->ena_napi[i].napi,
1508 ena_io_poll,
1509 ENA_NAPI_BUDGET);
1510 napi->rx_ring = &adapter->rx_ring[i];
1511 napi->tx_ring = &adapter->tx_ring[i];
1512 napi->qid = i;
1513 }
1514 }
1515
1516 static void ena_napi_disable_all(struct ena_adapter *adapter)
1517 {
1518 int i;
1519
1520 for (i = 0; i < adapter->num_queues; i++)
1521 napi_disable(&adapter->ena_napi[i].napi);
1522 }
1523
1524 static void ena_napi_enable_all(struct ena_adapter *adapter)
1525 {
1526 int i;
1527
1528 for (i = 0; i < adapter->num_queues; i++)
1529 napi_enable(&adapter->ena_napi[i].napi);
1530 }
1531
1532 static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1533 {
1534 adapter->tx_usecs = 0;
1535 adapter->rx_usecs = 0;
1536 adapter->tx_frames = 1;
1537 adapter->rx_frames = 1;
1538 }
1539
1540 /* Configure the Rx forwarding */
1541 static int ena_rss_configure(struct ena_adapter *adapter)
1542 {
1543 struct ena_com_dev *ena_dev = adapter->ena_dev;
1544 int rc;
1545
1546 /* In case the RSS table wasn't initialized by probe */
1547 if (!ena_dev->rss.tbl_log_size) {
1548 rc = ena_rss_init_default(adapter);
1549 if (rc && (rc != -EOPNOTSUPP)) {
1550 netif_err(adapter, ifup, adapter->netdev,
1551 "Failed to init RSS rc: %d\n", rc);
1552 return rc;
1553 }
1554 }
1555
1556 /* Set indirect table */
1557 rc = ena_com_indirect_table_set(ena_dev);
1558 if (unlikely(rc && rc != -EOPNOTSUPP))
1559 return rc;
1560
1561 /* Configure hash function (if supported) */
1562 rc = ena_com_set_hash_function(ena_dev);
1563 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1564 return rc;
1565
1566 /* Configure hash inputs (if supported) */
1567 rc = ena_com_set_hash_ctrl(ena_dev);
1568 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1569 return rc;
1570
1571 return 0;
1572 }
1573
1574 static int ena_up_complete(struct ena_adapter *adapter)
1575 {
1576 int rc;
1577
1578 rc = ena_rss_configure(adapter);
1579 if (rc)
1580 return rc;
1581
1582 ena_init_napi(adapter);
1583
1584 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1585
1586 ena_refill_all_rx_bufs(adapter);
1587
1588 /* enable transmits */
1589 netif_tx_start_all_queues(adapter->netdev);
1590
1591 ena_restore_ethtool_params(adapter);
1592
1593 ena_napi_enable_all(adapter);
1594
1595 return 0;
1596 }
1597
1598 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1599 {
1600 struct ena_com_create_io_ctx ctx = { 0 };
1601 struct ena_com_dev *ena_dev;
1602 struct ena_ring *tx_ring;
1603 u32 msix_vector;
1604 u16 ena_qid;
1605 int rc;
1606
1607 ena_dev = adapter->ena_dev;
1608
1609 tx_ring = &adapter->tx_ring[qid];
1610 msix_vector = ENA_IO_IRQ_IDX(qid);
1611 ena_qid = ENA_IO_TXQ_IDX(qid);
1612
1613 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1614 ctx.qid = ena_qid;
1615 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1616 ctx.msix_vector = msix_vector;
1617 ctx.queue_size = adapter->tx_ring_size;
1618 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1619
1620 rc = ena_com_create_io_queue(ena_dev, &ctx);
1621 if (rc) {
1622 netif_err(adapter, ifup, adapter->netdev,
1623 "Failed to create I/O TX queue num %d rc: %d\n",
1624 qid, rc);
1625 return rc;
1626 }
1627
1628 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1629 &tx_ring->ena_com_io_sq,
1630 &tx_ring->ena_com_io_cq);
1631 if (rc) {
1632 netif_err(adapter, ifup, adapter->netdev,
1633 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1634 qid, rc);
1635 ena_com_destroy_io_queue(ena_dev, ena_qid);
1636 return rc;
1637 }
1638
1639 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1640 return rc;
1641 }
1642
1643 static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1644 {
1645 struct ena_com_dev *ena_dev = adapter->ena_dev;
1646 int rc, i;
1647
1648 for (i = 0; i < adapter->num_queues; i++) {
1649 rc = ena_create_io_tx_queue(adapter, i);
1650 if (rc)
1651 goto create_err;
1652 }
1653
1654 return 0;
1655
1656 create_err:
1657 while (i--)
1658 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1659
1660 return rc;
1661 }
1662
1663 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1664 {
1665 struct ena_com_dev *ena_dev;
1666 struct ena_com_create_io_ctx ctx = { 0 };
1667 struct ena_ring *rx_ring;
1668 u32 msix_vector;
1669 u16 ena_qid;
1670 int rc;
1671
1672 ena_dev = adapter->ena_dev;
1673
1674 rx_ring = &adapter->rx_ring[qid];
1675 msix_vector = ENA_IO_IRQ_IDX(qid);
1676 ena_qid = ENA_IO_RXQ_IDX(qid);
1677
1678 ctx.qid = ena_qid;
1679 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1680 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1681 ctx.msix_vector = msix_vector;
1682 ctx.queue_size = adapter->rx_ring_size;
1683 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1684
1685 rc = ena_com_create_io_queue(ena_dev, &ctx);
1686 if (rc) {
1687 netif_err(adapter, ifup, adapter->netdev,
1688 "Failed to create I/O RX queue num %d rc: %d\n",
1689 qid, rc);
1690 return rc;
1691 }
1692
1693 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1694 &rx_ring->ena_com_io_sq,
1695 &rx_ring->ena_com_io_cq);
1696 if (rc) {
1697 netif_err(adapter, ifup, adapter->netdev,
1698 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1699 qid, rc);
1700 ena_com_destroy_io_queue(ena_dev, ena_qid);
1701 return rc;
1702 }
1703
1704 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1705
1706 return rc;
1707 }
1708
1709 static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1710 {
1711 struct ena_com_dev *ena_dev = adapter->ena_dev;
1712 int rc, i;
1713
1714 for (i = 0; i < adapter->num_queues; i++) {
1715 rc = ena_create_io_rx_queue(adapter, i);
1716 if (rc)
1717 goto create_err;
1718 }
1719
1720 return 0;
1721
1722 create_err:
1723 while (i--)
1724 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1725
1726 return rc;
1727 }
1728
1729 static int ena_up(struct ena_adapter *adapter)
1730 {
1731 int rc, i;
1732
1733 netdev_dbg(adapter->netdev, "%s\n", __func__);
1734
1735 ena_setup_io_intr(adapter);
1736
1737 rc = ena_request_io_irq(adapter);
1738 if (rc)
1739 goto err_req_irq;
1740
1741 /* allocate transmit descriptors */
1742 rc = ena_setup_all_tx_resources(adapter);
1743 if (rc)
1744 goto err_setup_tx;
1745
1746 /* allocate receive descriptors */
1747 rc = ena_setup_all_rx_resources(adapter);
1748 if (rc)
1749 goto err_setup_rx;
1750
1751 /* Create TX queues */
1752 rc = ena_create_all_io_tx_queues(adapter);
1753 if (rc)
1754 goto err_create_tx_queues;
1755
1756 /* Create RX queues */
1757 rc = ena_create_all_io_rx_queues(adapter);
1758 if (rc)
1759 goto err_create_rx_queues;
1760
1761 rc = ena_up_complete(adapter);
1762 if (rc)
1763 goto err_up;
1764
1765 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1766 netif_carrier_on(adapter->netdev);
1767
1768 u64_stats_update_begin(&adapter->syncp);
1769 adapter->dev_stats.interface_up++;
1770 u64_stats_update_end(&adapter->syncp);
1771
1772 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1773
1774 /* Enable completion queues interrupt */
1775 for (i = 0; i < adapter->num_queues; i++)
1776 ena_unmask_interrupt(&adapter->tx_ring[i],
1777 &adapter->rx_ring[i]);
1778
1779 /* schedule napi in case we had pending packets
1780 * from the last time we disable napi
1781 */
1782 for (i = 0; i < adapter->num_queues; i++)
1783 napi_schedule(&adapter->ena_napi[i].napi);
1784
1785 return rc;
1786
1787 err_up:
1788 ena_destroy_all_rx_queues(adapter);
1789 err_create_rx_queues:
1790 ena_destroy_all_tx_queues(adapter);
1791 err_create_tx_queues:
1792 ena_free_all_io_rx_resources(adapter);
1793 err_setup_rx:
1794 ena_free_all_io_tx_resources(adapter);
1795 err_setup_tx:
1796 ena_free_io_irq(adapter);
1797 err_req_irq:
1798
1799 return rc;
1800 }
1801
1802 static void ena_down(struct ena_adapter *adapter)
1803 {
1804 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1805
1806 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1807
1808 u64_stats_update_begin(&adapter->syncp);
1809 adapter->dev_stats.interface_down++;
1810 u64_stats_update_end(&adapter->syncp);
1811
1812 netif_carrier_off(adapter->netdev);
1813 netif_tx_disable(adapter->netdev);
1814
1815 /* After this point the napi handler won't enable the tx queue */
1816 ena_napi_disable_all(adapter);
1817
1818 /* After destroy the queue there won't be any new interrupts */
1819
1820 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1821 int rc;
1822
1823 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
1824 if (rc)
1825 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1826 }
1827
1828 ena_destroy_all_io_queues(adapter);
1829
1830 ena_disable_io_intr_sync(adapter);
1831 ena_free_io_irq(adapter);
1832 ena_del_napi(adapter);
1833
1834 ena_free_all_tx_bufs(adapter);
1835 ena_free_all_rx_bufs(adapter);
1836 ena_free_all_io_tx_resources(adapter);
1837 ena_free_all_io_rx_resources(adapter);
1838 }
1839
1840 /* ena_open - Called when a network interface is made active
1841 * @netdev: network interface device structure
1842 *
1843 * Returns 0 on success, negative value on failure
1844 *
1845 * The open entry point is called when a network interface is made
1846 * active by the system (IFF_UP). At this point all resources needed
1847 * for transmit and receive operations are allocated, the interrupt
1848 * handler is registered with the OS, the watchdog timer is started,
1849 * and the stack is notified that the interface is ready.
1850 */
1851 static int ena_open(struct net_device *netdev)
1852 {
1853 struct ena_adapter *adapter = netdev_priv(netdev);
1854 int rc;
1855
1856 /* Notify the stack of the actual queue counts. */
1857 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1858 if (rc) {
1859 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1860 return rc;
1861 }
1862
1863 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1864 if (rc) {
1865 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1866 return rc;
1867 }
1868
1869 rc = ena_up(adapter);
1870 if (rc)
1871 return rc;
1872
1873 return rc;
1874 }
1875
1876 /* ena_close - Disables a network interface
1877 * @netdev: network interface device structure
1878 *
1879 * Returns 0, this is not allowed to fail
1880 *
1881 * The close entry point is called when an interface is de-activated
1882 * by the OS. The hardware is still under the drivers control, but
1883 * needs to be disabled. A global MAC reset is issued to stop the
1884 * hardware, and all transmit and receive resources are freed.
1885 */
1886 static int ena_close(struct net_device *netdev)
1887 {
1888 struct ena_adapter *adapter = netdev_priv(netdev);
1889
1890 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1891
1892 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1893 ena_down(adapter);
1894
1895 /* Check for device status and issue reset if needed*/
1896 check_for_admin_com_state(adapter);
1897 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1898 netif_err(adapter, ifdown, adapter->netdev,
1899 "Destroy failure, restarting device\n");
1900 ena_dump_stats_to_dmesg(adapter);
1901 /* rtnl lock already obtained in dev_ioctl() layer */
1902 ena_destroy_device(adapter);
1903 ena_restore_device(adapter);
1904 }
1905
1906 return 0;
1907 }
1908
1909 static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1910 {
1911 u32 mss = skb_shinfo(skb)->gso_size;
1912 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1913 u8 l4_protocol = 0;
1914
1915 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1916 ena_tx_ctx->l4_csum_enable = 1;
1917 if (mss) {
1918 ena_tx_ctx->tso_enable = 1;
1919 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1920 ena_tx_ctx->l4_csum_partial = 0;
1921 } else {
1922 ena_tx_ctx->tso_enable = 0;
1923 ena_meta->l4_hdr_len = 0;
1924 ena_tx_ctx->l4_csum_partial = 1;
1925 }
1926
1927 switch (ip_hdr(skb)->version) {
1928 case IPVERSION:
1929 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1930 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1931 ena_tx_ctx->df = 1;
1932 if (mss)
1933 ena_tx_ctx->l3_csum_enable = 1;
1934 l4_protocol = ip_hdr(skb)->protocol;
1935 break;
1936 case 6:
1937 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1938 l4_protocol = ipv6_hdr(skb)->nexthdr;
1939 break;
1940 default:
1941 break;
1942 }
1943
1944 if (l4_protocol == IPPROTO_TCP)
1945 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1946 else
1947 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1948
1949 ena_meta->mss = mss;
1950 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1951 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1952 ena_tx_ctx->meta_valid = 1;
1953
1954 } else {
1955 ena_tx_ctx->meta_valid = 0;
1956 }
1957 }
1958
1959 static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1960 struct sk_buff *skb)
1961 {
1962 int num_frags, header_len, rc;
1963
1964 num_frags = skb_shinfo(skb)->nr_frags;
1965 header_len = skb_headlen(skb);
1966
1967 if (num_frags < tx_ring->sgl_size)
1968 return 0;
1969
1970 if ((num_frags == tx_ring->sgl_size) &&
1971 (header_len < tx_ring->tx_max_header_size))
1972 return 0;
1973
1974 u64_stats_update_begin(&tx_ring->syncp);
1975 tx_ring->tx_stats.linearize++;
1976 u64_stats_update_end(&tx_ring->syncp);
1977
1978 rc = skb_linearize(skb);
1979 if (unlikely(rc)) {
1980 u64_stats_update_begin(&tx_ring->syncp);
1981 tx_ring->tx_stats.linearize_failed++;
1982 u64_stats_update_end(&tx_ring->syncp);
1983 }
1984
1985 return rc;
1986 }
1987
1988 /* Called with netif_tx_lock. */
1989 static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1990 {
1991 struct ena_adapter *adapter = netdev_priv(dev);
1992 struct ena_tx_buffer *tx_info;
1993 struct ena_com_tx_ctx ena_tx_ctx;
1994 struct ena_ring *tx_ring;
1995 struct netdev_queue *txq;
1996 struct ena_com_buf *ena_buf;
1997 void *push_hdr;
1998 u32 len, last_frag;
1999 u16 next_to_use;
2000 u16 req_id;
2001 u16 push_len;
2002 u16 header_len;
2003 dma_addr_t dma;
2004 int qid, rc, nb_hw_desc;
2005 int i = -1;
2006
2007 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
2008 /* Determine which tx ring we will be placed on */
2009 qid = skb_get_queue_mapping(skb);
2010 tx_ring = &adapter->tx_ring[qid];
2011 txq = netdev_get_tx_queue(dev, qid);
2012
2013 rc = ena_check_and_linearize_skb(tx_ring, skb);
2014 if (unlikely(rc))
2015 goto error_drop_packet;
2016
2017 skb_tx_timestamp(skb);
2018 len = skb_headlen(skb);
2019
2020 next_to_use = tx_ring->next_to_use;
2021 req_id = tx_ring->free_tx_ids[next_to_use];
2022 tx_info = &tx_ring->tx_buffer_info[req_id];
2023 tx_info->num_of_bufs = 0;
2024
2025 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
2026 ena_buf = tx_info->bufs;
2027 tx_info->skb = skb;
2028
2029 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2030 /* prepared the push buffer */
2031 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
2032 header_len = push_len;
2033 push_hdr = skb->data;
2034 } else {
2035 push_len = 0;
2036 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
2037 push_hdr = NULL;
2038 }
2039
2040 netif_dbg(adapter, tx_queued, dev,
2041 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
2042 push_hdr, push_len);
2043
2044 if (len > push_len) {
2045 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
2046 len - push_len, DMA_TO_DEVICE);
2047 if (dma_mapping_error(tx_ring->dev, dma))
2048 goto error_report_dma_error;
2049
2050 ena_buf->paddr = dma;
2051 ena_buf->len = len - push_len;
2052
2053 ena_buf++;
2054 tx_info->num_of_bufs++;
2055 }
2056
2057 last_frag = skb_shinfo(skb)->nr_frags;
2058
2059 for (i = 0; i < last_frag; i++) {
2060 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2061
2062 len = skb_frag_size(frag);
2063 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
2064 DMA_TO_DEVICE);
2065 if (dma_mapping_error(tx_ring->dev, dma))
2066 goto error_report_dma_error;
2067
2068 ena_buf->paddr = dma;
2069 ena_buf->len = len;
2070 ena_buf++;
2071 }
2072
2073 tx_info->num_of_bufs += last_frag;
2074
2075 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2076 ena_tx_ctx.ena_bufs = tx_info->bufs;
2077 ena_tx_ctx.push_header = push_hdr;
2078 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2079 ena_tx_ctx.req_id = req_id;
2080 ena_tx_ctx.header_len = header_len;
2081
2082 /* set flags and meta data */
2083 ena_tx_csum(&ena_tx_ctx, skb);
2084
2085 /* prepare the packet's descriptors to dma engine */
2086 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2087 &nb_hw_desc);
2088
2089 if (unlikely(rc)) {
2090 netif_err(adapter, tx_queued, dev,
2091 "failed to prepare tx bufs\n");
2092 u64_stats_update_begin(&tx_ring->syncp);
2093 tx_ring->tx_stats.queue_stop++;
2094 tx_ring->tx_stats.prepare_ctx_err++;
2095 u64_stats_update_end(&tx_ring->syncp);
2096 netif_tx_stop_queue(txq);
2097 goto error_unmap_dma;
2098 }
2099
2100 netdev_tx_sent_queue(txq, skb->len);
2101
2102 u64_stats_update_begin(&tx_ring->syncp);
2103 tx_ring->tx_stats.cnt++;
2104 tx_ring->tx_stats.bytes += skb->len;
2105 u64_stats_update_end(&tx_ring->syncp);
2106
2107 tx_info->tx_descs = nb_hw_desc;
2108 tx_info->last_jiffies = jiffies;
2109 tx_info->print_once = 0;
2110
2111 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2112 tx_ring->ring_size);
2113
2114 /* This WMB is aimed to:
2115 * 1 - perform smp barrier before reading next_to_completion
2116 * 2 - make sure the desc were written before trigger DB
2117 */
2118 wmb();
2119
2120 /* stop the queue when no more space available, the packet can have up
2121 * to sgl_size + 2. one for the meta descriptor and one for header
2122 * (if the header is larger than tx_max_header_size).
2123 */
2124 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2125 (tx_ring->sgl_size + 2))) {
2126 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2127 __func__, qid);
2128
2129 netif_tx_stop_queue(txq);
2130 u64_stats_update_begin(&tx_ring->syncp);
2131 tx_ring->tx_stats.queue_stop++;
2132 u64_stats_update_end(&tx_ring->syncp);
2133
2134 /* There is a rare condition where this function decide to
2135 * stop the queue but meanwhile clean_tx_irq updates
2136 * next_to_completion and terminates.
2137 * The queue will remain stopped forever.
2138 * To solve this issue this function perform rmb, check
2139 * the wakeup condition and wake up the queue if needed.
2140 */
2141 smp_rmb();
2142
2143 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2144 > ENA_TX_WAKEUP_THRESH) {
2145 netif_tx_wake_queue(txq);
2146 u64_stats_update_begin(&tx_ring->syncp);
2147 tx_ring->tx_stats.queue_wakeup++;
2148 u64_stats_update_end(&tx_ring->syncp);
2149 }
2150 }
2151
2152 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2153 /* trigger the dma engine */
2154 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2155 u64_stats_update_begin(&tx_ring->syncp);
2156 tx_ring->tx_stats.doorbells++;
2157 u64_stats_update_end(&tx_ring->syncp);
2158 }
2159
2160 return NETDEV_TX_OK;
2161
2162 error_report_dma_error:
2163 u64_stats_update_begin(&tx_ring->syncp);
2164 tx_ring->tx_stats.dma_mapping_err++;
2165 u64_stats_update_end(&tx_ring->syncp);
2166 netdev_warn(adapter->netdev, "failed to map skb\n");
2167
2168 tx_info->skb = NULL;
2169
2170 error_unmap_dma:
2171 if (i >= 0) {
2172 /* save value of frag that failed */
2173 last_frag = i;
2174
2175 /* start back at beginning and unmap skb */
2176 tx_info->skb = NULL;
2177 ena_buf = tx_info->bufs;
2178 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2179 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2180
2181 /* unmap remaining mapped pages */
2182 for (i = 0; i < last_frag; i++) {
2183 ena_buf++;
2184 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2185 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2186 }
2187 }
2188
2189 error_drop_packet:
2190
2191 dev_kfree_skb(skb);
2192 return NETDEV_TX_OK;
2193 }
2194
2195 #ifdef CONFIG_NET_POLL_CONTROLLER
2196 static void ena_netpoll(struct net_device *netdev)
2197 {
2198 struct ena_adapter *adapter = netdev_priv(netdev);
2199 int i;
2200
2201 /* Dont schedule NAPI if the driver is in the middle of reset
2202 * or netdev is down.
2203 */
2204
2205 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2206 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2207 return;
2208
2209 for (i = 0; i < adapter->num_queues; i++)
2210 napi_schedule(&adapter->ena_napi[i].napi);
2211 }
2212 #endif /* CONFIG_NET_POLL_CONTROLLER */
2213
2214 static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2215 void *accel_priv, select_queue_fallback_t fallback)
2216 {
2217 u16 qid;
2218 /* we suspect that this is good for in--kernel network services that
2219 * want to loop incoming skb rx to tx in normal user generated traffic,
2220 * most probably we will not get to this
2221 */
2222 if (skb_rx_queue_recorded(skb))
2223 qid = skb_get_rx_queue(skb);
2224 else
2225 qid = fallback(dev, skb);
2226
2227 return qid;
2228 }
2229
2230 static void ena_config_host_info(struct ena_com_dev *ena_dev)
2231 {
2232 struct ena_admin_host_info *host_info;
2233 int rc;
2234
2235 /* Allocate only the host info */
2236 rc = ena_com_allocate_host_info(ena_dev);
2237 if (rc) {
2238 pr_err("Cannot allocate host info\n");
2239 return;
2240 }
2241
2242 host_info = ena_dev->host_attr.host_info;
2243
2244 host_info->os_type = ENA_ADMIN_OS_LINUX;
2245 host_info->kernel_ver = LINUX_VERSION_CODE;
2246 strncpy(host_info->kernel_ver_str, utsname()->version,
2247 sizeof(host_info->kernel_ver_str) - 1);
2248 host_info->os_dist = 0;
2249 strncpy(host_info->os_dist_str, utsname()->release,
2250 sizeof(host_info->os_dist_str) - 1);
2251 host_info->driver_version =
2252 (DRV_MODULE_VER_MAJOR) |
2253 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2254 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2255
2256 rc = ena_com_set_host_attributes(ena_dev);
2257 if (rc) {
2258 if (rc == -EOPNOTSUPP)
2259 pr_warn("Cannot set host attributes\n");
2260 else
2261 pr_err("Cannot set host attributes\n");
2262
2263 goto err;
2264 }
2265
2266 return;
2267
2268 err:
2269 ena_com_delete_host_info(ena_dev);
2270 }
2271
2272 static void ena_config_debug_area(struct ena_adapter *adapter)
2273 {
2274 u32 debug_area_size;
2275 int rc, ss_count;
2276
2277 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2278 if (ss_count <= 0) {
2279 netif_err(adapter, drv, adapter->netdev,
2280 "SS count is negative\n");
2281 return;
2282 }
2283
2284 /* allocate 32 bytes for each string and 64bit for the value */
2285 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2286
2287 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2288 if (rc) {
2289 pr_err("Cannot allocate debug area\n");
2290 return;
2291 }
2292
2293 rc = ena_com_set_host_attributes(adapter->ena_dev);
2294 if (rc) {
2295 if (rc == -EOPNOTSUPP)
2296 netif_warn(adapter, drv, adapter->netdev,
2297 "Cannot set host attributes\n");
2298 else
2299 netif_err(adapter, drv, adapter->netdev,
2300 "Cannot set host attributes\n");
2301 goto err;
2302 }
2303
2304 return;
2305 err:
2306 ena_com_delete_debug_area(adapter->ena_dev);
2307 }
2308
2309 static void ena_get_stats64(struct net_device *netdev,
2310 struct rtnl_link_stats64 *stats)
2311 {
2312 struct ena_adapter *adapter = netdev_priv(netdev);
2313 struct ena_ring *rx_ring, *tx_ring;
2314 unsigned int start;
2315 u64 rx_drops;
2316 int i;
2317
2318 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2319 return;
2320
2321 for (i = 0; i < adapter->num_queues; i++) {
2322 u64 bytes, packets;
2323
2324 tx_ring = &adapter->tx_ring[i];
2325
2326 do {
2327 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2328 packets = tx_ring->tx_stats.cnt;
2329 bytes = tx_ring->tx_stats.bytes;
2330 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
2331
2332 stats->tx_packets += packets;
2333 stats->tx_bytes += bytes;
2334
2335 rx_ring = &adapter->rx_ring[i];
2336
2337 do {
2338 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2339 packets = rx_ring->rx_stats.cnt;
2340 bytes = rx_ring->rx_stats.bytes;
2341 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2342
2343 stats->rx_packets += packets;
2344 stats->rx_bytes += bytes;
2345 }
2346
2347 do {
2348 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2349 rx_drops = adapter->dev_stats.rx_drops;
2350 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
2351
2352 stats->rx_dropped = rx_drops;
2353
2354 stats->multicast = 0;
2355 stats->collisions = 0;
2356
2357 stats->rx_length_errors = 0;
2358 stats->rx_crc_errors = 0;
2359 stats->rx_frame_errors = 0;
2360 stats->rx_fifo_errors = 0;
2361 stats->rx_missed_errors = 0;
2362 stats->tx_window_errors = 0;
2363
2364 stats->rx_errors = 0;
2365 stats->tx_errors = 0;
2366 }
2367
2368 static const struct net_device_ops ena_netdev_ops = {
2369 .ndo_open = ena_open,
2370 .ndo_stop = ena_close,
2371 .ndo_start_xmit = ena_start_xmit,
2372 .ndo_select_queue = ena_select_queue,
2373 .ndo_get_stats64 = ena_get_stats64,
2374 .ndo_tx_timeout = ena_tx_timeout,
2375 .ndo_change_mtu = ena_change_mtu,
2376 .ndo_set_mac_address = NULL,
2377 .ndo_validate_addr = eth_validate_addr,
2378 #ifdef CONFIG_NET_POLL_CONTROLLER
2379 .ndo_poll_controller = ena_netpoll,
2380 #endif /* CONFIG_NET_POLL_CONTROLLER */
2381 };
2382
2383 static int ena_device_validate_params(struct ena_adapter *adapter,
2384 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2385 {
2386 struct net_device *netdev = adapter->netdev;
2387 int rc;
2388
2389 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2390 adapter->mac_addr);
2391 if (!rc) {
2392 netif_err(adapter, drv, netdev,
2393 "Error, mac address are different\n");
2394 return -EINVAL;
2395 }
2396
2397 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2398 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2399 netif_err(adapter, drv, netdev,
2400 "Error, device doesn't support enough queues\n");
2401 return -EINVAL;
2402 }
2403
2404 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2405 netif_err(adapter, drv, netdev,
2406 "Error, device max mtu is smaller than netdev MTU\n");
2407 return -EINVAL;
2408 }
2409
2410 return 0;
2411 }
2412
2413 static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2414 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2415 bool *wd_state)
2416 {
2417 struct device *dev = &pdev->dev;
2418 bool readless_supported;
2419 u32 aenq_groups;
2420 int dma_width;
2421 int rc;
2422
2423 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2424 if (rc) {
2425 dev_err(dev, "failed to init mmio read less\n");
2426 return rc;
2427 }
2428
2429 /* The PCIe configuration space revision id indicate if mmio reg
2430 * read is disabled
2431 */
2432 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2433 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2434
2435 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
2436 if (rc) {
2437 dev_err(dev, "Can not reset device\n");
2438 goto err_mmio_read_less;
2439 }
2440
2441 rc = ena_com_validate_version(ena_dev);
2442 if (rc) {
2443 dev_err(dev, "device version is too low\n");
2444 goto err_mmio_read_less;
2445 }
2446
2447 dma_width = ena_com_get_dma_width(ena_dev);
2448 if (dma_width < 0) {
2449 dev_err(dev, "Invalid dma width value %d", dma_width);
2450 rc = dma_width;
2451 goto err_mmio_read_less;
2452 }
2453
2454 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2455 if (rc) {
2456 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2457 goto err_mmio_read_less;
2458 }
2459
2460 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2461 if (rc) {
2462 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2463 rc);
2464 goto err_mmio_read_less;
2465 }
2466
2467 /* ENA admin level init */
2468 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2469 if (rc) {
2470 dev_err(dev,
2471 "Can not initialize ena admin queue with device\n");
2472 goto err_mmio_read_less;
2473 }
2474
2475 /* To enable the msix interrupts the driver needs to know the number
2476 * of queues. So the driver uses polling mode to retrieve this
2477 * information
2478 */
2479 ena_com_set_admin_polling_mode(ena_dev, true);
2480
2481 ena_config_host_info(ena_dev);
2482
2483 /* Get Device Attributes*/
2484 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2485 if (rc) {
2486 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2487 goto err_admin_init;
2488 }
2489
2490 /* Try to turn all the available aenq groups */
2491 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2492 BIT(ENA_ADMIN_FATAL_ERROR) |
2493 BIT(ENA_ADMIN_WARNING) |
2494 BIT(ENA_ADMIN_NOTIFICATION) |
2495 BIT(ENA_ADMIN_KEEP_ALIVE);
2496
2497 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2498
2499 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2500 if (rc) {
2501 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2502 goto err_admin_init;
2503 }
2504
2505 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2506
2507 return 0;
2508
2509 err_admin_init:
2510 ena_com_delete_host_info(ena_dev);
2511 ena_com_admin_destroy(ena_dev);
2512 err_mmio_read_less:
2513 ena_com_mmio_reg_read_request_destroy(ena_dev);
2514
2515 return rc;
2516 }
2517
2518 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2519 int io_vectors)
2520 {
2521 struct ena_com_dev *ena_dev = adapter->ena_dev;
2522 struct device *dev = &adapter->pdev->dev;
2523 int rc;
2524
2525 rc = ena_enable_msix(adapter, io_vectors);
2526 if (rc) {
2527 dev_err(dev, "Can not reserve msix vectors\n");
2528 return rc;
2529 }
2530
2531 ena_setup_mgmnt_intr(adapter);
2532
2533 rc = ena_request_mgmnt_irq(adapter);
2534 if (rc) {
2535 dev_err(dev, "Can not setup management interrupts\n");
2536 goto err_disable_msix;
2537 }
2538
2539 ena_com_set_admin_polling_mode(ena_dev, false);
2540
2541 ena_com_admin_aenq_enable(ena_dev);
2542
2543 return 0;
2544
2545 err_disable_msix:
2546 ena_disable_msix(adapter);
2547
2548 return rc;
2549 }
2550
2551 static void ena_destroy_device(struct ena_adapter *adapter)
2552 {
2553 struct net_device *netdev = adapter->netdev;
2554 struct ena_com_dev *ena_dev = adapter->ena_dev;
2555 bool dev_up;
2556
2557 netif_carrier_off(netdev);
2558
2559 del_timer_sync(&adapter->timer_service);
2560
2561 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2562 adapter->dev_up_before_reset = dev_up;
2563
2564 ena_com_set_admin_running_state(ena_dev, false);
2565
2566 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2567 ena_down(adapter);
2568
2569 /* Before releasing the ENA resources, a device reset is required.
2570 * (to prevent the device from accessing them).
2571 * In case the reset flag is set and the device is up, ena_down()
2572 * already perform the reset, so it can be skipped.
2573 */
2574 if (!(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags) && dev_up))
2575 ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
2576
2577 ena_free_mgmnt_irq(adapter);
2578
2579 ena_disable_msix(adapter);
2580
2581 ena_com_abort_admin_commands(ena_dev);
2582
2583 ena_com_wait_for_abort_completion(ena_dev);
2584
2585 ena_com_admin_destroy(ena_dev);
2586
2587 ena_com_mmio_reg_read_request_destroy(ena_dev);
2588
2589 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
2590
2591 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2592 }
2593
2594 static int ena_restore_device(struct ena_adapter *adapter)
2595 {
2596 struct ena_com_dev_get_features_ctx get_feat_ctx;
2597 struct ena_com_dev *ena_dev = adapter->ena_dev;
2598 struct pci_dev *pdev = adapter->pdev;
2599 bool wd_state;
2600 int rc;
2601
2602 set_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2603 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2604 if (rc) {
2605 dev_err(&pdev->dev, "Can not initialize device\n");
2606 goto err;
2607 }
2608 adapter->wd_state = wd_state;
2609
2610 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2611 if (rc) {
2612 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2613 goto err_device_destroy;
2614 }
2615
2616 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2617 /* Make sure we don't have a race with AENQ Links state handler */
2618 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
2619 netif_carrier_on(adapter->netdev);
2620
2621 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2622 adapter->num_queues);
2623 if (rc) {
2624 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2625 goto err_device_destroy;
2626 }
2627 /* If the interface was up before the reset bring it up */
2628 if (adapter->dev_up_before_reset) {
2629 rc = ena_up(adapter);
2630 if (rc) {
2631 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2632 goto err_disable_msix;
2633 }
2634 }
2635
2636 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2637 dev_err(&pdev->dev, "Device reset completed successfully\n");
2638
2639 return rc;
2640 err_disable_msix:
2641 ena_free_mgmnt_irq(adapter);
2642 ena_disable_msix(adapter);
2643 err_device_destroy:
2644 ena_com_admin_destroy(ena_dev);
2645 err:
2646 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2647 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2648 dev_err(&pdev->dev,
2649 "Reset attempt failed. Can not reset the device\n");
2650
2651 return rc;
2652 }
2653
2654 static void ena_fw_reset_device(struct work_struct *work)
2655 {
2656 struct ena_adapter *adapter =
2657 container_of(work, struct ena_adapter, reset_task);
2658 struct pci_dev *pdev = adapter->pdev;
2659
2660 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2661 dev_err(&pdev->dev,
2662 "device reset schedule while reset bit is off\n");
2663 return;
2664 }
2665 rtnl_lock();
2666 ena_destroy_device(adapter);
2667 ena_restore_device(adapter);
2668 rtnl_unlock();
2669 }
2670
2671 static int check_for_rx_interrupt_queue(struct ena_adapter *adapter,
2672 struct ena_ring *rx_ring)
2673 {
2674 if (likely(rx_ring->first_interrupt))
2675 return 0;
2676
2677 if (ena_com_cq_empty(rx_ring->ena_com_io_cq))
2678 return 0;
2679
2680 rx_ring->no_interrupt_event_cnt++;
2681
2682 if (rx_ring->no_interrupt_event_cnt == ENA_MAX_NO_INTERRUPT_ITERATIONS) {
2683 netif_err(adapter, rx_err, adapter->netdev,
2684 "Potential MSIX issue on Rx side Queue = %d. Reset the device\n",
2685 rx_ring->qid);
2686 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2687 smp_mb__before_atomic();
2688 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2689 return -EIO;
2690 }
2691
2692 return 0;
2693 }
2694
2695 static int check_missing_comp_in_tx_queue(struct ena_adapter *adapter,
2696 struct ena_ring *tx_ring)
2697 {
2698 struct ena_tx_buffer *tx_buf;
2699 unsigned long last_jiffies;
2700 u32 missed_tx = 0;
2701 int i, rc = 0;
2702
2703 for (i = 0; i < tx_ring->ring_size; i++) {
2704 tx_buf = &tx_ring->tx_buffer_info[i];
2705 last_jiffies = tx_buf->last_jiffies;
2706
2707 if (last_jiffies == 0)
2708 /* no pending Tx at this location */
2709 continue;
2710
2711 if (unlikely(!tx_ring->first_interrupt && time_is_before_jiffies(last_jiffies +
2712 2 * adapter->missing_tx_completion_to))) {
2713 /* If after graceful period interrupt is still not
2714 * received, we schedule a reset
2715 */
2716 netif_err(adapter, tx_err, adapter->netdev,
2717 "Potential MSIX issue on Tx side Queue = %d. Reset the device\n",
2718 tx_ring->qid);
2719 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2720 smp_mb__before_atomic();
2721 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2722 return -EIO;
2723 }
2724
2725 if (unlikely(time_is_before_jiffies(last_jiffies +
2726 adapter->missing_tx_completion_to))) {
2727 if (!tx_buf->print_once)
2728 netif_notice(adapter, tx_err, adapter->netdev,
2729 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2730 tx_ring->qid, i);
2731
2732 tx_buf->print_once = 1;
2733 missed_tx++;
2734 }
2735 }
2736
2737 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) {
2738 netif_err(adapter, tx_err, adapter->netdev,
2739 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
2740 missed_tx,
2741 adapter->missing_tx_completion_threshold);
2742 adapter->reset_reason =
2743 ENA_REGS_RESET_MISS_TX_CMPL;
2744 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2745 rc = -EIO;
2746 }
2747
2748 u64_stats_update_begin(&tx_ring->syncp);
2749 tx_ring->tx_stats.missed_tx = missed_tx;
2750 u64_stats_update_end(&tx_ring->syncp);
2751
2752 return rc;
2753 }
2754
2755 static void check_for_missing_completions(struct ena_adapter *adapter)
2756 {
2757 struct ena_ring *tx_ring;
2758 struct ena_ring *rx_ring;
2759 int i, budget, rc;
2760
2761 /* Make sure the driver doesn't turn the device in other process */
2762 smp_rmb();
2763
2764 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2765 return;
2766
2767 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2768 return;
2769
2770 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
2771 return;
2772
2773 budget = ENA_MONITORED_TX_QUEUES;
2774
2775 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2776 tx_ring = &adapter->tx_ring[i];
2777 rx_ring = &adapter->rx_ring[i];
2778
2779 rc = check_missing_comp_in_tx_queue(adapter, tx_ring);
2780 if (unlikely(rc))
2781 return;
2782
2783 rc = check_for_rx_interrupt_queue(adapter, rx_ring);
2784 if (unlikely(rc))
2785 return;
2786
2787 budget--;
2788 if (!budget)
2789 break;
2790 }
2791
2792 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2793 }
2794
2795 /* trigger napi schedule after 2 consecutive detections */
2796 #define EMPTY_RX_REFILL 2
2797 /* For the rare case where the device runs out of Rx descriptors and the
2798 * napi handler failed to refill new Rx descriptors (due to a lack of memory
2799 * for example).
2800 * This case will lead to a deadlock:
2801 * The device won't send interrupts since all the new Rx packets will be dropped
2802 * The napi handler won't allocate new Rx descriptors so the device will be
2803 * able to send new packets.
2804 *
2805 * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
2806 * It is recommended to have at least 512MB, with a minimum of 128MB for
2807 * constrained environment).
2808 *
2809 * When such a situation is detected - Reschedule napi
2810 */
2811 static void check_for_empty_rx_ring(struct ena_adapter *adapter)
2812 {
2813 struct ena_ring *rx_ring;
2814 int i, refill_required;
2815
2816 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2817 return;
2818
2819 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2820 return;
2821
2822 for (i = 0; i < adapter->num_queues; i++) {
2823 rx_ring = &adapter->rx_ring[i];
2824
2825 refill_required =
2826 ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
2827 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
2828 rx_ring->empty_rx_queue++;
2829
2830 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
2831 u64_stats_update_begin(&rx_ring->syncp);
2832 rx_ring->rx_stats.empty_rx_ring++;
2833 u64_stats_update_end(&rx_ring->syncp);
2834
2835 netif_err(adapter, drv, adapter->netdev,
2836 "trigger refill for ring %d\n", i);
2837
2838 napi_schedule(rx_ring->napi);
2839 rx_ring->empty_rx_queue = 0;
2840 }
2841 } else {
2842 rx_ring->empty_rx_queue = 0;
2843 }
2844 }
2845 }
2846
2847 /* Check for keep alive expiration */
2848 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2849 {
2850 unsigned long keep_alive_expired;
2851
2852 if (!adapter->wd_state)
2853 return;
2854
2855 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2856 return;
2857
2858 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies +
2859 adapter->keep_alive_timeout);
2860 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2861 netif_err(adapter, drv, adapter->netdev,
2862 "Keep alive watchdog timeout.\n");
2863 u64_stats_update_begin(&adapter->syncp);
2864 adapter->dev_stats.wd_expired++;
2865 u64_stats_update_end(&adapter->syncp);
2866 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
2867 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2868 }
2869 }
2870
2871 static void check_for_admin_com_state(struct ena_adapter *adapter)
2872 {
2873 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2874 netif_err(adapter, drv, adapter->netdev,
2875 "ENA admin queue is not in running state!\n");
2876 u64_stats_update_begin(&adapter->syncp);
2877 adapter->dev_stats.admin_q_pause++;
2878 u64_stats_update_end(&adapter->syncp);
2879 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
2880 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2881 }
2882 }
2883
2884 static void ena_update_hints(struct ena_adapter *adapter,
2885 struct ena_admin_ena_hw_hints *hints)
2886 {
2887 struct net_device *netdev = adapter->netdev;
2888
2889 if (hints->admin_completion_tx_timeout)
2890 adapter->ena_dev->admin_queue.completion_timeout =
2891 hints->admin_completion_tx_timeout * 1000;
2892
2893 if (hints->mmio_read_timeout)
2894 /* convert to usec */
2895 adapter->ena_dev->mmio_read.reg_read_to =
2896 hints->mmio_read_timeout * 1000;
2897
2898 if (hints->missed_tx_completion_count_threshold_to_reset)
2899 adapter->missing_tx_completion_threshold =
2900 hints->missed_tx_completion_count_threshold_to_reset;
2901
2902 if (hints->missing_tx_completion_timeout) {
2903 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2904 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT;
2905 else
2906 adapter->missing_tx_completion_to =
2907 msecs_to_jiffies(hints->missing_tx_completion_timeout);
2908 }
2909
2910 if (hints->netdev_wd_timeout)
2911 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout);
2912
2913 if (hints->driver_watchdog_timeout) {
2914 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2915 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2916 else
2917 adapter->keep_alive_timeout =
2918 msecs_to_jiffies(hints->driver_watchdog_timeout);
2919 }
2920 }
2921
2922 static void ena_update_host_info(struct ena_admin_host_info *host_info,
2923 struct net_device *netdev)
2924 {
2925 host_info->supported_network_features[0] =
2926 netdev->features & GENMASK_ULL(31, 0);
2927 host_info->supported_network_features[1] =
2928 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2929 }
2930
2931 static void ena_timer_service(struct timer_list *t)
2932 {
2933 struct ena_adapter *adapter = from_timer(adapter, t, timer_service);
2934 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2935 struct ena_admin_host_info *host_info =
2936 adapter->ena_dev->host_attr.host_info;
2937
2938 check_for_missing_keep_alive(adapter);
2939
2940 check_for_admin_com_state(adapter);
2941
2942 check_for_missing_completions(adapter);
2943
2944 check_for_empty_rx_ring(adapter);
2945
2946 if (debug_area)
2947 ena_dump_stats_to_buf(adapter, debug_area);
2948
2949 if (host_info)
2950 ena_update_host_info(host_info, adapter->netdev);
2951
2952 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2953 netif_err(adapter, drv, adapter->netdev,
2954 "Trigger reset is on\n");
2955 ena_dump_stats_to_dmesg(adapter);
2956 queue_work(ena_wq, &adapter->reset_task);
2957 return;
2958 }
2959
2960 /* Reset the timer */
2961 mod_timer(&adapter->timer_service, jiffies + HZ);
2962 }
2963
2964 static int ena_calc_io_queue_num(struct pci_dev *pdev,
2965 struct ena_com_dev *ena_dev,
2966 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2967 {
2968 int io_sq_num, io_queue_num;
2969
2970 /* In case of LLQ use the llq number in the get feature cmd */
2971 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2972 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2973
2974 if (io_sq_num == 0) {
2975 dev_err(&pdev->dev,
2976 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2977
2978 ena_dev->tx_mem_queue_type =
2979 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2980 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2981 }
2982 } else {
2983 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2984 }
2985
2986 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
2987 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2988 io_queue_num = min_t(int, io_queue_num,
2989 get_feat_ctx->max_queues.max_cq_num);
2990 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2991 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2992 if (unlikely(!io_queue_num)) {
2993 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2994 return -EFAULT;
2995 }
2996
2997 return io_queue_num;
2998 }
2999
3000 static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
3001 struct ena_com_dev_get_features_ctx *get_feat_ctx)
3002 {
3003 bool has_mem_bar;
3004
3005 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
3006
3007 /* Enable push mode if device supports LLQ */
3008 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
3009 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
3010 else
3011 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3012 }
3013
3014 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
3015 struct net_device *netdev)
3016 {
3017 netdev_features_t dev_features = 0;
3018
3019 /* Set offload features */
3020 if (feat->offload.tx &
3021 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
3022 dev_features |= NETIF_F_IP_CSUM;
3023
3024 if (feat->offload.tx &
3025 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
3026 dev_features |= NETIF_F_IPV6_CSUM;
3027
3028 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
3029 dev_features |= NETIF_F_TSO;
3030
3031 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
3032 dev_features |= NETIF_F_TSO6;
3033
3034 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
3035 dev_features |= NETIF_F_TSO_ECN;
3036
3037 if (feat->offload.rx_supported &
3038 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
3039 dev_features |= NETIF_F_RXCSUM;
3040
3041 if (feat->offload.rx_supported &
3042 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
3043 dev_features |= NETIF_F_RXCSUM;
3044
3045 netdev->features =
3046 dev_features |
3047 NETIF_F_SG |
3048 NETIF_F_RXHASH |
3049 NETIF_F_HIGHDMA;
3050
3051 netdev->hw_features |= netdev->features;
3052 netdev->vlan_features |= netdev->features;
3053 }
3054
3055 static void ena_set_conf_feat_params(struct ena_adapter *adapter,
3056 struct ena_com_dev_get_features_ctx *feat)
3057 {
3058 struct net_device *netdev = adapter->netdev;
3059
3060 /* Copy mac address */
3061 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
3062 eth_hw_addr_random(netdev);
3063 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
3064 } else {
3065 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
3066 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
3067 }
3068
3069 /* Set offload features */
3070 ena_set_dev_offloads(feat, netdev);
3071
3072 adapter->max_mtu = feat->dev_attr.max_mtu;
3073 netdev->max_mtu = adapter->max_mtu;
3074 netdev->min_mtu = ENA_MIN_MTU;
3075 }
3076
3077 static int ena_rss_init_default(struct ena_adapter *adapter)
3078 {
3079 struct ena_com_dev *ena_dev = adapter->ena_dev;
3080 struct device *dev = &adapter->pdev->dev;
3081 int rc, i;
3082 u32 val;
3083
3084 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
3085 if (unlikely(rc)) {
3086 dev_err(dev, "Cannot init indirect table\n");
3087 goto err_rss_init;
3088 }
3089
3090 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
3091 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
3092 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
3093 ENA_IO_RXQ_IDX(val));
3094 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3095 dev_err(dev, "Cannot fill indirect table\n");
3096 goto err_fill_indir;
3097 }
3098 }
3099
3100 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
3101 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
3102 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3103 dev_err(dev, "Cannot fill hash function\n");
3104 goto err_fill_indir;
3105 }
3106
3107 rc = ena_com_set_default_hash_ctrl(ena_dev);
3108 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
3109 dev_err(dev, "Cannot fill hash control\n");
3110 goto err_fill_indir;
3111 }
3112
3113 return 0;
3114
3115 err_fill_indir:
3116 ena_com_rss_destroy(ena_dev);
3117 err_rss_init:
3118
3119 return rc;
3120 }
3121
3122 static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
3123 {
3124 int release_bars;
3125
3126 if (ena_dev->mem_bar)
3127 devm_iounmap(&pdev->dev, ena_dev->mem_bar);
3128
3129 if (ena_dev->reg_bar)
3130 devm_iounmap(&pdev->dev, ena_dev->reg_bar);
3131
3132 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3133 pci_release_selected_regions(pdev, release_bars);
3134 }
3135
3136 static int ena_calc_queue_size(struct pci_dev *pdev,
3137 struct ena_com_dev *ena_dev,
3138 u16 *max_tx_sgl_size,
3139 u16 *max_rx_sgl_size,
3140 struct ena_com_dev_get_features_ctx *get_feat_ctx)
3141 {
3142 u32 queue_size = ENA_DEFAULT_RING_SIZE;
3143
3144 queue_size = min_t(u32, queue_size,
3145 get_feat_ctx->max_queues.max_cq_depth);
3146 queue_size = min_t(u32, queue_size,
3147 get_feat_ctx->max_queues.max_sq_depth);
3148
3149 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3150 queue_size = min_t(u32, queue_size,
3151 get_feat_ctx->max_queues.max_llq_depth);
3152
3153 queue_size = rounddown_pow_of_two(queue_size);
3154
3155 if (unlikely(!queue_size)) {
3156 dev_err(&pdev->dev, "Invalid queue size\n");
3157 return -EFAULT;
3158 }
3159
3160 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3161 get_feat_ctx->max_queues.max_packet_tx_descs);
3162 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3163 get_feat_ctx->max_queues.max_packet_rx_descs);
3164
3165 return queue_size;
3166 }
3167
3168 /* ena_probe - Device Initialization Routine
3169 * @pdev: PCI device information struct
3170 * @ent: entry in ena_pci_tbl
3171 *
3172 * Returns 0 on success, negative on failure
3173 *
3174 * ena_probe initializes an adapter identified by a pci_dev structure.
3175 * The OS initialization, configuring of the adapter private structure,
3176 * and a hardware reset occur.
3177 */
3178 static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3179 {
3180 struct ena_com_dev_get_features_ctx get_feat_ctx;
3181 static int version_printed;
3182 struct net_device *netdev;
3183 struct ena_adapter *adapter;
3184 struct ena_com_dev *ena_dev = NULL;
3185 static int adapters_found;
3186 int io_queue_num, bars, rc;
3187 int queue_size;
3188 u16 tx_sgl_size = 0;
3189 u16 rx_sgl_size = 0;
3190 bool wd_state;
3191
3192 dev_dbg(&pdev->dev, "%s\n", __func__);
3193
3194 if (version_printed++ == 0)
3195 dev_info(&pdev->dev, "%s", version);
3196
3197 rc = pci_enable_device_mem(pdev);
3198 if (rc) {
3199 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
3200 return rc;
3201 }
3202
3203 pci_set_master(pdev);
3204
3205 ena_dev = vzalloc(sizeof(*ena_dev));
3206 if (!ena_dev) {
3207 rc = -ENOMEM;
3208 goto err_disable_device;
3209 }
3210
3211 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3212 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
3213 if (rc) {
3214 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3215 rc);
3216 goto err_free_ena_dev;
3217 }
3218
3219 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3220 pci_resource_start(pdev, ENA_REG_BAR),
3221 pci_resource_len(pdev, ENA_REG_BAR));
3222 if (!ena_dev->reg_bar) {
3223 dev_err(&pdev->dev, "failed to remap regs bar\n");
3224 rc = -EFAULT;
3225 goto err_free_region;
3226 }
3227
3228 ena_dev->dmadev = &pdev->dev;
3229
3230 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3231 if (rc) {
3232 dev_err(&pdev->dev, "ena device init failed\n");
3233 if (rc == -ETIME)
3234 rc = -EPROBE_DEFER;
3235 goto err_free_region;
3236 }
3237
3238 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
3239
3240 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
3241 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3242 pci_resource_start(pdev, ENA_MEM_BAR),
3243 pci_resource_len(pdev, ENA_MEM_BAR));
3244 if (!ena_dev->mem_bar) {
3245 rc = -EFAULT;
3246 goto err_device_destroy;
3247 }
3248 }
3249
3250 /* initial Tx interrupt delay, Assumes 1 usec granularity.
3251 * Updated during device initialization with the real granularity
3252 */
3253 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
3254 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
3255 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
3256 &rx_sgl_size, &get_feat_ctx);
3257 if ((queue_size <= 0) || (io_queue_num <= 0)) {
3258 rc = -EFAULT;
3259 goto err_device_destroy;
3260 }
3261
3262 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
3263 io_queue_num, queue_size);
3264
3265 /* dev zeroed in init_etherdev */
3266 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3267 if (!netdev) {
3268 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3269 rc = -ENOMEM;
3270 goto err_device_destroy;
3271 }
3272
3273 SET_NETDEV_DEV(netdev, &pdev->dev);
3274
3275 adapter = netdev_priv(netdev);
3276 pci_set_drvdata(pdev, adapter);
3277
3278 adapter->ena_dev = ena_dev;
3279 adapter->netdev = netdev;
3280 adapter->pdev = pdev;
3281
3282 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3283
3284 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3285 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
3286
3287 adapter->tx_ring_size = queue_size;
3288 adapter->rx_ring_size = queue_size;
3289
3290 adapter->max_tx_sgl_size = tx_sgl_size;
3291 adapter->max_rx_sgl_size = rx_sgl_size;
3292
3293 adapter->num_queues = io_queue_num;
3294 adapter->last_monitored_tx_qid = 0;
3295
3296 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3297 adapter->wd_state = wd_state;
3298
3299 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3300
3301 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3302 if (rc) {
3303 dev_err(&pdev->dev,
3304 "Failed to query interrupt moderation feature\n");
3305 goto err_netdev_destroy;
3306 }
3307 ena_init_io_rings(adapter);
3308
3309 netdev->netdev_ops = &ena_netdev_ops;
3310 netdev->watchdog_timeo = TX_TIMEOUT;
3311 ena_set_ethtool_ops(netdev);
3312
3313 netdev->priv_flags |= IFF_UNICAST_FLT;
3314
3315 u64_stats_init(&adapter->syncp);
3316
3317 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3318 if (rc) {
3319 dev_err(&pdev->dev,
3320 "Failed to enable and set the admin interrupts\n");
3321 goto err_worker_destroy;
3322 }
3323 rc = ena_rss_init_default(adapter);
3324 if (rc && (rc != -EOPNOTSUPP)) {
3325 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3326 goto err_free_msix;
3327 }
3328
3329 ena_config_debug_area(adapter);
3330
3331 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3332
3333 netif_carrier_off(netdev);
3334
3335 rc = register_netdev(netdev);
3336 if (rc) {
3337 dev_err(&pdev->dev, "Cannot register net device\n");
3338 goto err_rss;
3339 }
3340
3341 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3342
3343 adapter->last_keep_alive_jiffies = jiffies;
3344 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
3345 adapter->missing_tx_completion_to = TX_TIMEOUT;
3346 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS;
3347
3348 ena_update_hints(adapter, &get_feat_ctx.hw_hints);
3349
3350 timer_setup(&adapter->timer_service, ena_timer_service, 0);
3351 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
3352
3353 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3354 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3355 netdev->dev_addr, io_queue_num);
3356
3357 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3358
3359 adapters_found++;
3360
3361 return 0;
3362
3363 err_rss:
3364 ena_com_delete_debug_area(ena_dev);
3365 ena_com_rss_destroy(ena_dev);
3366 err_free_msix:
3367 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
3368 ena_free_mgmnt_irq(adapter);
3369 ena_disable_msix(adapter);
3370 err_worker_destroy:
3371 ena_com_destroy_interrupt_moderation(ena_dev);
3372 del_timer(&adapter->timer_service);
3373 err_netdev_destroy:
3374 free_netdev(netdev);
3375 err_device_destroy:
3376 ena_com_delete_host_info(ena_dev);
3377 ena_com_admin_destroy(ena_dev);
3378 err_free_region:
3379 ena_release_bars(ena_dev, pdev);
3380 err_free_ena_dev:
3381 vfree(ena_dev);
3382 err_disable_device:
3383 pci_disable_device(pdev);
3384 return rc;
3385 }
3386
3387 /*****************************************************************************/
3388 static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3389 {
3390 int rc;
3391
3392 if (numvfs > 0) {
3393 rc = pci_enable_sriov(dev, numvfs);
3394 if (rc != 0) {
3395 dev_err(&dev->dev,
3396 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3397 numvfs, rc);
3398 return rc;
3399 }
3400
3401 return numvfs;
3402 }
3403
3404 if (numvfs == 0) {
3405 pci_disable_sriov(dev);
3406 return 0;
3407 }
3408
3409 return -EINVAL;
3410 }
3411
3412 /*****************************************************************************/
3413 /*****************************************************************************/
3414
3415 /* ena_remove - Device Removal Routine
3416 * @pdev: PCI device information struct
3417 *
3418 * ena_remove is called by the PCI subsystem to alert the driver
3419 * that it should release a PCI device.
3420 */
3421 static void ena_remove(struct pci_dev *pdev)
3422 {
3423 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3424 struct ena_com_dev *ena_dev;
3425 struct net_device *netdev;
3426
3427 ena_dev = adapter->ena_dev;
3428 netdev = adapter->netdev;
3429
3430 #ifdef CONFIG_RFS_ACCEL
3431 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3432 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3433 netdev->rx_cpu_rmap = NULL;
3434 }
3435 #endif /* CONFIG_RFS_ACCEL */
3436
3437 unregister_netdev(netdev);
3438 del_timer_sync(&adapter->timer_service);
3439
3440 cancel_work_sync(&adapter->reset_task);
3441
3442 /* Reset the device only if the device is running. */
3443 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
3444 ena_com_dev_reset(ena_dev, adapter->reset_reason);
3445
3446 ena_free_mgmnt_irq(adapter);
3447
3448 ena_disable_msix(adapter);
3449
3450 free_netdev(netdev);
3451
3452 ena_com_mmio_reg_read_request_destroy(ena_dev);
3453
3454 ena_com_abort_admin_commands(ena_dev);
3455
3456 ena_com_wait_for_abort_completion(ena_dev);
3457
3458 ena_com_admin_destroy(ena_dev);
3459
3460 ena_com_rss_destroy(ena_dev);
3461
3462 ena_com_delete_debug_area(ena_dev);
3463
3464 ena_com_delete_host_info(ena_dev);
3465
3466 ena_release_bars(ena_dev, pdev);
3467
3468 pci_disable_device(pdev);
3469
3470 ena_com_destroy_interrupt_moderation(ena_dev);
3471
3472 vfree(ena_dev);
3473 }
3474
3475 #ifdef CONFIG_PM
3476 /* ena_suspend - PM suspend callback
3477 * @pdev: PCI device information struct
3478 * @state:power state
3479 */
3480 static int ena_suspend(struct pci_dev *pdev, pm_message_t state)
3481 {
3482 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3483
3484 u64_stats_update_begin(&adapter->syncp);
3485 adapter->dev_stats.suspend++;
3486 u64_stats_update_end(&adapter->syncp);
3487
3488 rtnl_lock();
3489 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
3490 dev_err(&pdev->dev,
3491 "ignoring device reset request as the device is being suspended\n");
3492 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3493 }
3494 ena_destroy_device(adapter);
3495 rtnl_unlock();
3496 return 0;
3497 }
3498
3499 /* ena_resume - PM resume callback
3500 * @pdev: PCI device information struct
3501 *
3502 */
3503 static int ena_resume(struct pci_dev *pdev)
3504 {
3505 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3506 int rc;
3507
3508 u64_stats_update_begin(&adapter->syncp);
3509 adapter->dev_stats.resume++;
3510 u64_stats_update_end(&adapter->syncp);
3511
3512 rtnl_lock();
3513 rc = ena_restore_device(adapter);
3514 rtnl_unlock();
3515 return rc;
3516 }
3517 #endif
3518
3519 static struct pci_driver ena_pci_driver = {
3520 .name = DRV_MODULE_NAME,
3521 .id_table = ena_pci_tbl,
3522 .probe = ena_probe,
3523 .remove = ena_remove,
3524 #ifdef CONFIG_PM
3525 .suspend = ena_suspend,
3526 .resume = ena_resume,
3527 #endif
3528 .sriov_configure = ena_sriov_configure,
3529 };
3530
3531 static int __init ena_init(void)
3532 {
3533 pr_info("%s", version);
3534
3535 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3536 if (!ena_wq) {
3537 pr_err("Failed to create workqueue\n");
3538 return -ENOMEM;
3539 }
3540
3541 return pci_register_driver(&ena_pci_driver);
3542 }
3543
3544 static void __exit ena_cleanup(void)
3545 {
3546 pci_unregister_driver(&ena_pci_driver);
3547
3548 if (ena_wq) {
3549 destroy_workqueue(ena_wq);
3550 ena_wq = NULL;
3551 }
3552 }
3553
3554 /******************************************************************************
3555 ******************************** AENQ Handlers *******************************
3556 *****************************************************************************/
3557 /* ena_update_on_link_change:
3558 * Notify the network interface about the change in link status
3559 */
3560 static void ena_update_on_link_change(void *adapter_data,
3561 struct ena_admin_aenq_entry *aenq_e)
3562 {
3563 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3564 struct ena_admin_aenq_link_change_desc *aenq_desc =
3565 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3566 int status = aenq_desc->flags &
3567 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3568
3569 if (status) {
3570 netdev_dbg(adapter->netdev, "%s\n", __func__);
3571 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3572 if (!test_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags))
3573 netif_carrier_on(adapter->netdev);
3574 } else {
3575 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3576 netif_carrier_off(adapter->netdev);
3577 }
3578 }
3579
3580 static void ena_keep_alive_wd(void *adapter_data,
3581 struct ena_admin_aenq_entry *aenq_e)
3582 {
3583 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3584 struct ena_admin_aenq_keep_alive_desc *desc;
3585 u64 rx_drops;
3586
3587 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3588 adapter->last_keep_alive_jiffies = jiffies;
3589
3590 rx_drops = ((u64)desc->rx_drops_high << 32) | desc->rx_drops_low;
3591
3592 u64_stats_update_begin(&adapter->syncp);
3593 adapter->dev_stats.rx_drops = rx_drops;
3594 u64_stats_update_end(&adapter->syncp);
3595 }
3596
3597 static void ena_notification(void *adapter_data,
3598 struct ena_admin_aenq_entry *aenq_e)
3599 {
3600 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3601 struct ena_admin_ena_hw_hints *hints;
3602
3603 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3604 "Invalid group(%x) expected %x\n",
3605 aenq_e->aenq_common_desc.group,
3606 ENA_ADMIN_NOTIFICATION);
3607
3608 switch (aenq_e->aenq_common_desc.syndrom) {
3609 case ENA_ADMIN_UPDATE_HINTS:
3610 hints = (struct ena_admin_ena_hw_hints *)
3611 (&aenq_e->inline_data_w4);
3612 ena_update_hints(adapter, hints);
3613 break;
3614 default:
3615 netif_err(adapter, drv, adapter->netdev,
3616 "Invalid aenq notification link state %d\n",
3617 aenq_e->aenq_common_desc.syndrom);
3618 }
3619 }
3620
3621 /* This handler will called for unknown event group or unimplemented handlers*/
3622 static void unimplemented_aenq_handler(void *data,
3623 struct ena_admin_aenq_entry *aenq_e)
3624 {
3625 struct ena_adapter *adapter = (struct ena_adapter *)data;
3626
3627 netif_err(adapter, drv, adapter->netdev,
3628 "Unknown event was received or event with unimplemented handler\n");
3629 }
3630
3631 static struct ena_aenq_handlers aenq_handlers = {
3632 .handlers = {
3633 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3634 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3635 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3636 },
3637 .unimplemented_handler = unimplemented_aenq_handler
3638 };
3639
3640 module_init(ena_init);
3641 module_exit(ena_cleanup);
CRIS linux kernel tree