drivers/net/ethernet/amazon/ena/ena_netdev.h

   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef ENA_H
  34 #define ENA_H
  35
  36 #include <linux/bitops.h>
  37 #include <linux/etherdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/skbuff.h>
  42
  43 #include "ena_com.h"
  44 #include "ena_eth_com.h"
  45
  46 #define DRV_MODULE_VER_MAJOR    1
  47 #define DRV_MODULE_VER_MINOR    5
  48 #define DRV_MODULE_VER_SUBMINOR 0
  49
  50 #define DRV_MODULE_NAME         "ena"
  51 #ifndef DRV_MODULE_VERSION
  52 #define DRV_MODULE_VERSION \
  53         __stringify(DRV_MODULE_VER_MAJOR) "."   \
  54         __stringify(DRV_MODULE_VER_MINOR) "."   \
  55         __stringify(DRV_MODULE_VER_SUBMINOR) "K"
  56 #endif
  57
  58 #define DEVICE_NAME     "Elastic Network Adapter (ENA)"
  59
  60 /* 1 for AENQ + ADMIN */
  61 #define ENA_ADMIN_MSIX_VEC              1
  62 #define ENA_MAX_MSIX_VEC(io_queues)     (ENA_ADMIN_MSIX_VEC + (io_queues))
  63
  64 #define ENA_MIN_MSIX_VEC                2
  65
  66 #define ENA_REG_BAR                     0
  67 #define ENA_MEM_BAR                     2
  68 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
  69
  70 #define ENA_DEFAULT_RING_SIZE   (1024)
  71
  72 #define ENA_TX_WAKEUP_THRESH            (MAX_SKB_FRAGS + 2)
  73 #define ENA_DEFAULT_RX_COPYBREAK        (128 - NET_IP_ALIGN)
  74
  75 /* limit the buffer size to 600 bytes to handle MTU changes from very
  76  * small to very large, in which case the number of buffers per packet
  77  * could exceed ENA_PKT_MAX_BUFS
  78  */
  79 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
  80
  81 #define ENA_MIN_MTU             128
  82
  83 #define ENA_NAME_MAX_LEN        20
  84 #define ENA_IRQNAME_SIZE        40
  85
  86 #define ENA_PKT_MAX_BUFS        19
  87
  88 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  89 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  90
  91 #define ENA_HASH_KEY_SIZE       40
  92
  93 /* The number of tx packet completions that will be handled each NAPI poll
  94  * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
  95  */
  96 #define ENA_TX_POLL_BUDGET_DIVIDER      4
  97
  98 /* Refill Rx queue when number of available descriptors is below
  99  * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
 100  */
 101 #define ENA_RX_REFILL_THRESH_DIVIDER    8
 102
 103 /* Number of queues to check for missing queues per timer service */
 104 #define ENA_MONITORED_TX_QUEUES 4
 105 /* Max timeout packets before device reset */
 106 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128
 107
 108 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 109
 110 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 111 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
 112         (((idx) + (n)) & ((ring_size) - 1))
 113
 114 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
 115 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
 116
 117 #define ENA_MGMNT_IRQ_IDX               0
 118 #define ENA_IO_IRQ_FIRST_IDX            1
 119 #define ENA_IO_IRQ_IDX(q)               (ENA_IO_IRQ_FIRST_IDX + (q))
 120
 121 /* ENA device should send keep alive msg every 1 sec.
 122  * We wait for 6 sec just to be on the safe side.
 123  */
 124 #define ENA_DEVICE_KALIVE_TIMEOUT       (6 * HZ)
 125 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
 126
 127 #define ENA_MMIO_DISABLE_REG_READ       BIT(0)
 128
 129 struct ena_irq {
 130         irq_handler_t handler;
 131         void *data;
 132         int cpu;
 133         u32 vector;
 134         cpumask_t affinity_hint_mask;
 135         char name[ENA_IRQNAME_SIZE];
 136 };
 137
 138 struct ena_napi {
 139         struct napi_struct napi ____cacheline_aligned;
 140         struct ena_ring *tx_ring;
 141         struct ena_ring *rx_ring;
 142         u32 qid;
 143 };
 144
 145 struct ena_tx_buffer {
 146         struct sk_buff *skb;
 147         /* num of ena desc for this specific skb
 148          * (includes data desc and metadata desc)
 149          */
 150         u32 tx_descs;
 151         /* num of buffers used by this skb */
 152         u32 num_of_bufs;
 153
 154         /* Used for detect missing tx packets to limit the number of prints */
 155         u32 print_once;
 156         /* Save the last jiffies to detect missing tx packets
 157          *
 158          * sets to non zero value on ena_start_xmit and set to zero on
 159          * napi and timer_Service_routine.
 160          *
 161          * while this value is not protected by lock,
 162          * a given packet is not expected to be handled by ena_start_xmit
 163          * and by napi/timer_service at the same time.
 164          */
 165         unsigned long last_jiffies;
 166         struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
 167 } ____cacheline_aligned;
 168
 169 struct ena_rx_buffer {
 170         struct sk_buff *skb;
 171         struct page *page;
 172         u32 page_offset;
 173         struct ena_com_buf ena_buf;
 174 } ____cacheline_aligned;
 175
 176 struct ena_stats_tx {
 177         u64 cnt;
 178         u64 bytes;
 179         u64 queue_stop;
 180         u64 prepare_ctx_err;
 181         u64 queue_wakeup;
 182         u64 dma_mapping_err;
 183         u64 linearize;
 184         u64 linearize_failed;
 185         u64 napi_comp;
 186         u64 tx_poll;
 187         u64 doorbells;
 188         u64 bad_req_id;
 189         u64 missed_tx;
 190 };
 191
 192 struct ena_stats_rx {
 193         u64 cnt;
 194         u64 bytes;
 195         u64 refil_partial;
 196         u64 bad_csum;
 197         u64 page_alloc_fail;
 198         u64 skb_alloc_fail;
 199         u64 dma_mapping_err;
 200         u64 bad_desc_num;
 201         u64 rx_copybreak_pkt;
 202         u64 bad_req_id;
 203         u64 empty_rx_ring;
 204 };
 205
 206 struct ena_ring {
 207         union {
 208                 /* Holds the empty requests for TX/RX
 209                  * out of order completions
 210                  */
 211                 u16 *free_tx_ids;
 212                 u16 *free_rx_ids;
 213         };
 214
 215         union {
 216                 struct ena_tx_buffer *tx_buffer_info;
 217                 struct ena_rx_buffer *rx_buffer_info;
 218         };
 219
 220         /* cache ptr to avoid using the adapter */
 221         struct device *dev;
 222         struct pci_dev *pdev;
 223         struct napi_struct *napi;
 224         struct net_device *netdev;
 225         struct ena_com_dev *ena_dev;
 226         struct ena_adapter *adapter;
 227         struct ena_com_io_cq *ena_com_io_cq;
 228         struct ena_com_io_sq *ena_com_io_sq;
 229
 230         u16 next_to_use;
 231         u16 next_to_clean;
 232         u16 rx_copybreak;
 233         u16 qid;
 234         u16 mtu;
 235         u16 sgl_size;
 236
 237         /* The maximum header length the device can handle */
 238         u8 tx_max_header_size;
 239
 240         bool first_interrupt;
 241         u16 no_interrupt_event_cnt;
 242
 243         /* cpu for TPH */
 244         int cpu;
 245          /* number of tx/rx_buffer_info's entries */
 246         int ring_size;
 247
 248         enum ena_admin_placement_policy_type tx_mem_queue_type;
 249
 250         struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
 251         u32  smoothed_interval;
 252         u32  per_napi_packets;
 253         u32  per_napi_bytes;
 254         enum ena_intr_moder_level moder_tbl_idx;
 255         struct u64_stats_sync syncp;
 256         union {
 257                 struct ena_stats_tx tx_stats;
 258                 struct ena_stats_rx rx_stats;
 259         };
 260         int empty_rx_queue;
 261 } ____cacheline_aligned;
 262
 263 struct ena_stats_dev {
 264         u64 tx_timeout;
 265         u64 suspend;
 266         u64 resume;
 267         u64 wd_expired;
 268         u64 interface_up;
 269         u64 interface_down;
 270         u64 admin_q_pause;
 271         u64 rx_drops;
 272 };
 273
 274 enum ena_flags_t {
 275         ENA_FLAG_DEVICE_RUNNING,
 276         ENA_FLAG_DEV_UP,
 277         ENA_FLAG_LINK_UP,
 278         ENA_FLAG_MSIX_ENABLED,
 279         ENA_FLAG_TRIGGER_RESET,
 280         ENA_FLAG_ONGOING_RESET
 281 };
 282
 283 /* adapter specific private data structure */
 284 struct ena_adapter {
 285         struct ena_com_dev *ena_dev;
 286         /* OS defined structs */
 287         struct net_device *netdev;
 288         struct pci_dev *pdev;
 289
 290         /* rx packets that shorter that this len will be copied to the skb
 291          * header
 292          */
 293         u32 rx_copybreak;
 294         u32 max_mtu;
 295
 296         int num_queues;
 297
 298         int msix_vecs;
 299
 300         u32 missing_tx_completion_threshold;
 301
 302         u32 tx_usecs, rx_usecs; /* interrupt moderation */
 303         u32 tx_frames, rx_frames; /* interrupt moderation */
 304
 305         u32 tx_ring_size;
 306         u32 rx_ring_size;
 307
 308         u32 msg_enable;
 309
 310         u16 max_tx_sgl_size;
 311         u16 max_rx_sgl_size;
 312
 313         u8 mac_addr[ETH_ALEN];
 314
 315         unsigned long keep_alive_timeout;
 316         unsigned long missing_tx_completion_to;
 317
 318         char name[ENA_NAME_MAX_LEN];
 319
 320         unsigned long flags;
 321         /* TX */
 322         struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
 323                 ____cacheline_aligned_in_smp;
 324
 325         /* RX */
 326         struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
 327                 ____cacheline_aligned_in_smp;
 328
 329         struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
 330
 331         struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
 332
 333         /* timer service */
 334         struct work_struct reset_task;
 335         struct timer_list timer_service;
 336
 337         bool wd_state;
 338         bool dev_up_before_reset;
 339         unsigned long last_keep_alive_jiffies;
 340
 341         struct u64_stats_sync syncp;
 342         struct ena_stats_dev dev_stats;
 343
 344         /* last queue index that was checked for uncompleted tx packets */
 345         u32 last_monitored_tx_qid;
 346
 347         enum ena_regs_reset_reason_types reset_reason;
 348 };
 349
 350 void ena_set_ethtool_ops(struct net_device *netdev);
 351
 352 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
 353
 354 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
 355
 356 int ena_get_sset_count(struct net_device *netdev, int sset);
 357
 358 #endif /* !(ENA_H) */