drivers/net/ethernet/cavium/thunder/nicvf_queues.h

   1 /*
   2  * Copyright (C) 2015 Cavium, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef NICVF_QUEUES_H
  10 #define NICVF_QUEUES_H
  11
  12 #include <linux/netdevice.h>
  13 #include <linux/iommu.h>
  14 #include <net/xdp.h>
  15 #include "q_struct.h"
  16
  17 #define MAX_QUEUE_SET                   128
  18 #define MAX_RCV_QUEUES_PER_QS           8
  19 #define MAX_RCV_BUF_DESC_RINGS_PER_QS   2
  20 #define MAX_SND_QUEUES_PER_QS           8
  21 #define MAX_CMP_QUEUES_PER_QS           8
  22
  23 /* VF's queue interrupt ranges */
  24 #define NICVF_INTR_ID_CQ                0
  25 #define NICVF_INTR_ID_SQ                8
  26 #define NICVF_INTR_ID_RBDR              16
  27 #define NICVF_INTR_ID_MISC              18
  28 #define NICVF_INTR_ID_QS_ERR            19
  29
  30 #define for_each_cq_irq(irq)    \
  31         for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++)
  32 #define for_each_sq_irq(irq)    \
  33         for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++)
  34 #define for_each_rbdr_irq(irq)  \
  35         for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++)
  36
  37 #define RBDR_SIZE0              0ULL /* 8K entries */
  38 #define RBDR_SIZE1              1ULL /* 16K entries */
  39 #define RBDR_SIZE2              2ULL /* 32K entries */
  40 #define RBDR_SIZE3              3ULL /* 64K entries */
  41 #define RBDR_SIZE4              4ULL /* 126K entries */
  42 #define RBDR_SIZE5              5ULL /* 256K entries */
  43 #define RBDR_SIZE6              6ULL /* 512K entries */
  44
  45 #define SND_QUEUE_SIZE0         0ULL /* 1K entries */
  46 #define SND_QUEUE_SIZE1         1ULL /* 2K entries */
  47 #define SND_QUEUE_SIZE2         2ULL /* 4K entries */
  48 #define SND_QUEUE_SIZE3         3ULL /* 8K entries */
  49 #define SND_QUEUE_SIZE4         4ULL /* 16K entries */
  50 #define SND_QUEUE_SIZE5         5ULL /* 32K entries */
  51 #define SND_QUEUE_SIZE6         6ULL /* 64K entries */
  52
  53 #define CMP_QUEUE_SIZE0         0ULL /* 1K entries */
  54 #define CMP_QUEUE_SIZE1         1ULL /* 2K entries */
  55 #define CMP_QUEUE_SIZE2         2ULL /* 4K entries */
  56 #define CMP_QUEUE_SIZE3         3ULL /* 8K entries */
  57 #define CMP_QUEUE_SIZE4         4ULL /* 16K entries */
  58 #define CMP_QUEUE_SIZE5         5ULL /* 32K entries */
  59 #define CMP_QUEUE_SIZE6         6ULL /* 64K entries */
  60
  61 /* Default queue count per QS, its lengths and threshold values */
  62 #define DEFAULT_RBDR_CNT        1
  63
  64 #define SND_QSIZE               SND_QUEUE_SIZE0
  65 #define SND_QUEUE_LEN           (1ULL << (SND_QSIZE + 10))
  66 #define MIN_SND_QUEUE_LEN       (1ULL << (SND_QUEUE_SIZE0 + 10))
  67 #define MAX_SND_QUEUE_LEN       (1ULL << (SND_QUEUE_SIZE6 + 10))
  68 #define SND_QUEUE_THRESH        2ULL
  69 #define MIN_SQ_DESC_PER_PKT_XMIT        2
  70 /* Since timestamp not enabled, otherwise 2 */
  71 #define MAX_CQE_PER_PKT_XMIT            1
  72
  73 /* Keep CQ and SQ sizes same, if timestamping
  74  * is enabled this equation will change.
  75  */
  76 #define CMP_QSIZE               CMP_QUEUE_SIZE0
  77 #define CMP_QUEUE_LEN           (1ULL << (CMP_QSIZE + 10))
  78 #define MIN_CMP_QUEUE_LEN       (1ULL << (CMP_QUEUE_SIZE0 + 10))
  79 #define MAX_CMP_QUEUE_LEN       (1ULL << (CMP_QUEUE_SIZE6 + 10))
  80 #define CMP_QUEUE_CQE_THRESH    (NAPI_POLL_WEIGHT / 2)
  81 #define CMP_QUEUE_TIMER_THRESH  80 /* ~2usec */
  82
  83 /* No of CQEs that might anyway gets used by HW due to pipelining
  84  * effects irrespective of PASS/DROP/LEVELS being configured
  85  */
  86 #define CMP_QUEUE_PIPELINE_RSVD 544
  87
  88 #define RBDR_SIZE               RBDR_SIZE0
  89 #define RCV_BUF_COUNT           (1ULL << (RBDR_SIZE + 13))
  90 #define MAX_RCV_BUF_COUNT       (1ULL << (RBDR_SIZE6 + 13))
  91 #define RBDR_THRESH             (RCV_BUF_COUNT / 2)
  92 #define DMA_BUFFER_LEN          1536 /* In multiples of 128bytes */
  93 #define RCV_FRAG_LEN     (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
  94                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
  95
  96 #define MAX_CQES_FOR_TX         ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
  97                                  MAX_CQE_PER_PKT_XMIT)
  98
  99 /* RED and Backpressure levels of CQ for pkt reception
 100  * For CQ, level is a measure of emptiness i.e 0x0 means full
 101  * eg: For CQ of size 4K, and for pass/drop levels of 160/144
 102  * HW accepts pkt if unused CQE >= 2560
 103  * RED accepts pkt if unused CQE < 2304 & >= 2560
 104  * DROPs pkts if unused CQE < 2304
 105  */
 106 #define RQ_PASS_CQ_LVL         192ULL
 107 #define RQ_DROP_CQ_LVL         184ULL
 108
 109 /* RED and Backpressure levels of RBDR for pkt reception
 110  * For RBDR, level is a measure of fullness i.e 0x0 means empty
 111  * eg: For RBDR of size 8K, and for pass/drop levels of 4/0
 112  * HW accepts pkt if unused RBs >= 256
 113  * RED accepts pkt if unused RBs < 256 & >= 0
 114  * DROPs pkts if unused RBs < 0
 115  */
 116 #define RQ_PASS_RBDR_LVL        8ULL
 117 #define RQ_DROP_RBDR_LVL        0ULL
 118
 119 /* Descriptor size in bytes */
 120 #define SND_QUEUE_DESC_SIZE     16
 121 #define CMP_QUEUE_DESC_SIZE     512
 122
 123 /* Buffer / descriptor alignments */
 124 #define NICVF_RCV_BUF_ALIGN             7
 125 #define NICVF_RCV_BUF_ALIGN_BYTES       (1ULL << NICVF_RCV_BUF_ALIGN)
 126 #define NICVF_CQ_BASE_ALIGN_BYTES       512  /* 9 bits */
 127 #define NICVF_SQ_BASE_ALIGN_BYTES       128  /* 7 bits */
 128
 129 #define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES)   ALIGN(ADDR, ALIGN_BYTES)
 130
 131 /* Queue enable/disable */
 132 #define NICVF_SQ_EN             BIT_ULL(19)
 133
 134 /* Queue reset */
 135 #define NICVF_CQ_RESET          BIT_ULL(41)
 136 #define NICVF_SQ_RESET          BIT_ULL(17)
 137 #define NICVF_RBDR_RESET        BIT_ULL(43)
 138
 139 enum CQ_RX_ERRLVL_E {
 140         CQ_ERRLVL_MAC,
 141         CQ_ERRLVL_L2,
 142         CQ_ERRLVL_L3,
 143         CQ_ERRLVL_L4,
 144 };
 145
 146 enum CQ_RX_ERROP_E {
 147         CQ_RX_ERROP_RE_NONE = 0x0,
 148         CQ_RX_ERROP_RE_PARTIAL = 0x1,
 149         CQ_RX_ERROP_RE_JABBER = 0x2,
 150         CQ_RX_ERROP_RE_FCS = 0x7,
 151         CQ_RX_ERROP_RE_TERMINATE = 0x9,
 152         CQ_RX_ERROP_RE_RX_CTL = 0xb,
 153         CQ_RX_ERROP_PREL2_ERR = 0x1f,
 154         CQ_RX_ERROP_L2_FRAGMENT = 0x20,
 155         CQ_RX_ERROP_L2_OVERRUN = 0x21,
 156         CQ_RX_ERROP_L2_PFCS = 0x22,
 157         CQ_RX_ERROP_L2_PUNY = 0x23,
 158         CQ_RX_ERROP_L2_MAL = 0x24,
 159         CQ_RX_ERROP_L2_OVERSIZE = 0x25,
 160         CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
 161         CQ_RX_ERROP_L2_LENMISM = 0x27,
 162         CQ_RX_ERROP_L2_PCLP = 0x28,
 163         CQ_RX_ERROP_IP_NOT = 0x41,
 164         CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
 165         CQ_RX_ERROP_IP_MAL = 0x43,
 166         CQ_RX_ERROP_IP_MALD = 0x44,
 167         CQ_RX_ERROP_IP_HOP = 0x45,
 168         CQ_RX_ERROP_L3_ICRC = 0x46,
 169         CQ_RX_ERROP_L3_PCLP = 0x47,
 170         CQ_RX_ERROP_L4_MAL = 0x61,
 171         CQ_RX_ERROP_L4_CHK = 0x62,
 172         CQ_RX_ERROP_UDP_LEN = 0x63,
 173         CQ_RX_ERROP_L4_PORT = 0x64,
 174         CQ_RX_ERROP_TCP_FLAG = 0x65,
 175         CQ_RX_ERROP_TCP_OFFSET = 0x66,
 176         CQ_RX_ERROP_L4_PCLP = 0x67,
 177         CQ_RX_ERROP_RBDR_TRUNC = 0x70,
 178 };
 179
 180 enum CQ_TX_ERROP_E {
 181         CQ_TX_ERROP_GOOD = 0x0,
 182         CQ_TX_ERROP_DESC_FAULT = 0x10,
 183         CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
 184         CQ_TX_ERROP_SUBDC_ERR = 0x12,
 185         CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13,
 186         CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
 187         CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
 188         CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
 189         CQ_TX_ERROP_LOCK_VIOL = 0x83,
 190         CQ_TX_ERROP_DATA_FAULT = 0x84,
 191         CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
 192         CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
 193         CQ_TX_ERROP_MEM_FAULT = 0x87,
 194         CQ_TX_ERROP_CK_OVERLAP = 0x88,
 195         CQ_TX_ERROP_CK_OFLOW = 0x89,
 196         CQ_TX_ERROP_ENUM_LAST = 0x8a,
 197 };
 198
 199 enum RQ_SQ_STATS {
 200         RQ_SQ_STATS_OCTS,
 201         RQ_SQ_STATS_PKTS,
 202 };
 203
 204 struct rx_tx_queue_stats {
 205         u64     bytes;
 206         u64     pkts;
 207 } ____cacheline_aligned_in_smp;
 208
 209 struct q_desc_mem {
 210         dma_addr_t      dma;
 211         u64             size;
 212         u32             q_len;
 213         dma_addr_t      phys_base;
 214         void            *base;
 215         void            *unalign_base;
 216 };
 217
 218 struct pgcache {
 219         struct page     *page;
 220         int             ref_count;
 221         u64             dma_addr;
 222 };
 223
 224 struct rbdr {
 225         bool            enable;
 226         u32             dma_size;
 227         u32             frag_len;
 228         u32             thresh;         /* Threshold level for interrupt */
 229         void            *desc;
 230         u32             head;
 231         u32             tail;
 232         struct q_desc_mem   dmem;
 233         bool            is_xdp;
 234
 235         /* For page recycling */
 236         int             pgidx;
 237         int             pgcnt;
 238         int             pgalloc;
 239         struct pgcache  *pgcache;
 240 } ____cacheline_aligned_in_smp;
 241
 242 struct rcv_queue {
 243         bool            enable;
 244         struct  rbdr    *rbdr_start;
 245         struct  rbdr    *rbdr_cont;
 246         bool            en_tcp_reassembly;
 247         u8              cq_qs;  /* CQ's QS to which this RQ is assigned */
 248         u8              cq_idx; /* CQ index (0 to 7) in the QS */
 249         u8              cont_rbdr_qs;      /* Continue buffer ptrs - QS num */
 250         u8              cont_qs_rbdr_idx;  /* RBDR idx in the cont QS */
 251         u8              start_rbdr_qs;     /* First buffer ptrs - QS num */
 252         u8              start_qs_rbdr_idx; /* RBDR idx in the above QS */
 253         u8              caching;
 254         struct          rx_tx_queue_stats stats;
 255         struct xdp_rxq_info xdp_rxq;
 256 } ____cacheline_aligned_in_smp;
 257
 258 struct cmp_queue {
 259         bool            enable;
 260         u16             thresh;
 261         spinlock_t      lock;  /* lock to serialize processing CQEs */
 262         void            *desc;
 263         struct q_desc_mem   dmem;
 264         int             irq;
 265 } ____cacheline_aligned_in_smp;
 266
 267 struct snd_queue {
 268         bool            enable;
 269         u8              cq_qs;  /* CQ's QS to which this SQ is pointing */
 270         u8              cq_idx; /* CQ index (0 to 7) in the above QS */
 271         u16             thresh;
 272         atomic_t        free_cnt;
 273         u32             head;
 274         u32             tail;
 275         u64             *skbuff;
 276         void            *desc;
 277         u64             *xdp_page;
 278         u16             xdp_desc_cnt;
 279         u16             xdp_free_cnt;
 280         bool            is_xdp;
 281
 282         /* For TSO segment's header */
 283         char            *tso_hdrs;
 284         dma_addr_t      tso_hdrs_phys;
 285
 286         cpumask_t       affinity_mask;
 287         struct q_desc_mem   dmem;
 288         struct rx_tx_queue_stats stats;
 289 } ____cacheline_aligned_in_smp;
 290
 291 struct queue_set {
 292         bool            enable;
 293         bool            be_en;
 294         u8              vnic_id;
 295         u8              rq_cnt;
 296         u8              cq_cnt;
 297         u64             cq_len;
 298         u8              sq_cnt;
 299         u64             sq_len;
 300         u8              rbdr_cnt;
 301         u64             rbdr_len;
 302         struct  rcv_queue       rq[MAX_RCV_QUEUES_PER_QS];
 303         struct  cmp_queue       cq[MAX_CMP_QUEUES_PER_QS];
 304         struct  snd_queue       sq[MAX_SND_QUEUES_PER_QS];
 305         struct  rbdr            rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS];
 306 } ____cacheline_aligned_in_smp;
 307
 308 #define GET_RBDR_DESC(RING, idx)\
 309                 (&(((struct rbdr_entry_t *)((RING)->desc))[idx]))
 310 #define GET_SQ_DESC(RING, idx)\
 311                 (&(((struct sq_hdr_subdesc *)((RING)->desc))[idx]))
 312 #define GET_CQ_DESC(RING, idx)\
 313                 (&(((union cq_desc_t *)((RING)->desc))[idx]))
 314
 315 /* CQ status bits */
 316 #define CQ_WR_FULL      BIT(26)
 317 #define CQ_WR_DISABLE   BIT(25)
 318 #define CQ_WR_FAULT     BIT(24)
 319 #define CQ_CQE_COUNT    (0xFFFF << 0)
 320
 321 #define CQ_ERR_MASK     (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
 322
 323 static inline u64 nicvf_iova_to_phys(struct nicvf *nic, dma_addr_t dma_addr)
 324 {
 325         /* Translation is installed only when IOMMU is present */
 326         if (nic->iommu_domain)
 327                 return iommu_iova_to_phys(nic->iommu_domain, dma_addr);
 328         return dma_addr;
 329 }
 330
 331 void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
 332                               int hdr_sqe, u8 subdesc_cnt);
 333 void nicvf_config_vlan_stripping(struct nicvf *nic,
 334                                  netdev_features_t features);
 335 int nicvf_set_qset_resources(struct nicvf *nic);
 336 int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
 337 void nicvf_qset_config(struct nicvf *nic, bool enable);
 338 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
 339                             int qidx, bool enable);
 340
 341 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx);
 342 void nicvf_sq_disable(struct nicvf *nic, int qidx);
 343 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
 344 void nicvf_sq_free_used_descs(struct net_device *netdev,
 345                               struct snd_queue *sq, int qidx);
 346 int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
 347                         struct sk_buff *skb, u8 sq_num);
 348 int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
 349                             u64 bufaddr, u64 dma_addr, u16 len);
 350 void nicvf_xdp_sq_doorbell(struct nicvf *nic, struct snd_queue *sq, int sq_num);
 351
 352 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic,
 353                                   struct cqe_rx_t *cqe_rx, bool xdp);
 354 void nicvf_rbdr_task(unsigned long data);
 355 void nicvf_rbdr_work(struct work_struct *work);
 356
 357 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx);
 358 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx);
 359 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx);
 360 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx);
 361
 362 /* Register access APIs */
 363 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val);
 364 u64  nicvf_reg_read(struct nicvf *nic, u64 offset);
 365 void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val);
 366 u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset);
 367 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
 368                            u64 qidx, u64 val);
 369 u64  nicvf_queue_reg_read(struct nicvf *nic,
 370                           u64 offset, u64 qidx);
 371
 372 /* Stats */
 373 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
 374 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
 375 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
 376 int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx);
 377 #endif /* NICVF_QUEUES_H */