drivers/net/ethernet/ibm/emac/core.h

   1 /*
   2  * drivers/net/ethernet/ibm/emac/core.h
   3  *
   4  * Driver for PowerPC 4xx on-chip ethernet controller.
   5  *
   6  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   7  *                <benh@kernel.crashing.org>
   8  *
   9  * Based on the arch/ppc version of the driver:
  10  *
  11  * Copyright (c) 2004, 2005 Zultys Technologies.
  12  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  13  *
  14  * Based on original work by
  15  *      Armin Kuster <akuster@mvista.com>
  16  *      Johnnie Peters <jpeters@mvista.com>
  17  *      Copyright 2000, 2001 MontaVista Softare Inc.
  18  *
  19  * This program is free software; you can redistribute  it and/or modify it
  20  * under  the terms of  the GNU General  Public License as published by the
  21  * Free Software Foundation;  either version 2 of the  License, or (at your
  22  * option) any later version.
  23  *
  24  */
  25 #ifndef __IBM_NEWEMAC_CORE_H
  26 #define __IBM_NEWEMAC_CORE_H
  27
  28 #include <linux/module.h>
  29 #include <linux/list.h>
  30 #include <linux/kernel.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/dcr.h>
  40
  41 #include "emac.h"
  42 #include "phy.h"
  43 #include "zmii.h"
  44 #include "rgmii.h"
  45 #include "mal.h"
  46 #include "tah.h"
  47 #include "debug.h"
  48
  49 #define NUM_TX_BUFF                     CONFIG_IBM_EMAC_TXB
  50 #define NUM_RX_BUFF                     CONFIG_IBM_EMAC_RXB
  51
  52 /* Simple sanity check */
  53 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
  54 #error Invalid number of buffer descriptors (greater than 256)
  55 #endif
  56
  57 #define EMAC_MIN_MTU                    46
  58
  59 /* Maximum L2 header length (VLAN tagged, no FCS) */
  60 #define EMAC_MTU_OVERHEAD               (6 * 2 + 2 + 4)
  61
  62 /* RX BD size for the given MTU */
  63 static inline int emac_rx_size(int mtu)
  64 {
  65         if (mtu > ETH_DATA_LEN)
  66                 return MAL_MAX_RX_SIZE;
  67         else
  68                 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
  69 }
  70
  71 #define EMAC_DMA_ALIGN(x)               ALIGN((x), dma_get_cache_alignment())
  72
  73 #define EMAC_RX_SKB_HEADROOM            \
  74         EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM)
  75
  76 /* Size of RX skb for the given MTU */
  77 static inline int emac_rx_skb_size(int mtu)
  78 {
  79         int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
  80         return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
  81 }
  82
  83 /* RX DMA sync size */
  84 static inline int emac_rx_sync_size(int mtu)
  85 {
  86         return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
  87 }
  88
  89 /* Driver statistcs is split into two parts to make it more cache friendly:
  90  *   - normal statistics (packet count, etc)
  91  *   - error statistics
  92  *
  93  * When statistics is requested by ethtool, these parts are concatenated,
  94  * normal one goes first.
  95  *
  96  * Please, keep these structures in sync with emac_stats_keys.
  97  */
  98
  99 /* Normal TX/RX Statistics */
 100 struct emac_stats {
 101         u64 rx_packets;
 102         u64 rx_bytes;
 103         u64 tx_packets;
 104         u64 tx_bytes;
 105         u64 rx_packets_csum;
 106         u64 tx_packets_csum;
 107 };
 108
 109 /* Error statistics */
 110 struct emac_error_stats {
 111         u64 tx_undo;
 112
 113         /* Software RX Errors */
 114         u64 rx_dropped_stack;
 115         u64 rx_dropped_oom;
 116         u64 rx_dropped_error;
 117         u64 rx_dropped_resize;
 118         u64 rx_dropped_mtu;
 119         u64 rx_stopped;
 120         /* BD reported RX errors */
 121         u64 rx_bd_errors;
 122         u64 rx_bd_overrun;
 123         u64 rx_bd_bad_packet;
 124         u64 rx_bd_runt_packet;
 125         u64 rx_bd_short_event;
 126         u64 rx_bd_alignment_error;
 127         u64 rx_bd_bad_fcs;
 128         u64 rx_bd_packet_too_long;
 129         u64 rx_bd_out_of_range;
 130         u64 rx_bd_in_range;
 131         /* EMAC IRQ reported RX errors */
 132         u64 rx_parity;
 133         u64 rx_fifo_overrun;
 134         u64 rx_overrun;
 135         u64 rx_bad_packet;
 136         u64 rx_runt_packet;
 137         u64 rx_short_event;
 138         u64 rx_alignment_error;
 139         u64 rx_bad_fcs;
 140         u64 rx_packet_too_long;
 141         u64 rx_out_of_range;
 142         u64 rx_in_range;
 143
 144         /* Software TX Errors */
 145         u64 tx_dropped;
 146         /* BD reported TX errors */
 147         u64 tx_bd_errors;
 148         u64 tx_bd_bad_fcs;
 149         u64 tx_bd_carrier_loss;
 150         u64 tx_bd_excessive_deferral;
 151         u64 tx_bd_excessive_collisions;
 152         u64 tx_bd_late_collision;
 153         u64 tx_bd_multple_collisions;
 154         u64 tx_bd_single_collision;
 155         u64 tx_bd_underrun;
 156         u64 tx_bd_sqe;
 157         /* EMAC IRQ reported TX errors */
 158         u64 tx_parity;
 159         u64 tx_underrun;
 160         u64 tx_sqe;
 161         u64 tx_errors;
 162 };
 163
 164 #define EMAC_ETHTOOL_STATS_COUNT        ((sizeof(struct emac_stats) + \
 165                                           sizeof(struct emac_error_stats)) \
 166                                          / sizeof(u64))
 167
 168 struct emac_instance {
 169         struct net_device               *ndev;
 170         struct emac_regs                __iomem *emacp;
 171         struct platform_device          *ofdev;
 172         struct device_node              **blist; /* bootlist entry */
 173
 174         /* MAL linkage */
 175         u32                             mal_ph;
 176         struct platform_device          *mal_dev;
 177         u32                             mal_rx_chan;
 178         u32                             mal_tx_chan;
 179         struct mal_instance             *mal;
 180         struct mal_commac               commac;
 181
 182         /* PHY infos */
 183         int                             phy_mode;
 184         u32                             phy_map;
 185         u32                             phy_address;
 186         u32                             phy_feat_exc;
 187         struct mii_phy                  phy;
 188         struct mutex                    link_lock;
 189         struct delayed_work             link_work;
 190         int                             link_polling;
 191
 192         /* GPCS PHY infos */
 193         u32                             gpcs_address;
 194
 195         /* Shared MDIO if any */
 196         u32                             mdio_ph;
 197         struct platform_device          *mdio_dev;
 198         struct emac_instance            *mdio_instance;
 199         struct mutex                    mdio_lock;
 200
 201         /* Device-tree based phy configuration */
 202         struct mii_bus                  *mii_bus;
 203         struct phy_device               *phy_dev;
 204
 205         /* ZMII infos if any */
 206         u32                             zmii_ph;
 207         u32                             zmii_port;
 208         struct platform_device          *zmii_dev;
 209
 210         /* RGMII infos if any */
 211         u32                             rgmii_ph;
 212         u32                             rgmii_port;
 213         struct platform_device          *rgmii_dev;
 214
 215         /* TAH infos if any */
 216         u32                             tah_ph;
 217         u32                             tah_port;
 218         struct platform_device          *tah_dev;
 219
 220         /* IRQs */
 221         int                             wol_irq;
 222         int                             emac_irq;
 223
 224         /* OPB bus frequency in Mhz */
 225         u32                             opb_bus_freq;
 226
 227         /* Cell index within an ASIC (for clk mgmnt) */
 228         u32                             cell_index;
 229
 230         /* Max supported MTU */
 231         u32                             max_mtu;
 232
 233         /* Feature bits (from probe table) */
 234         unsigned int                    features;
 235
 236         /* Tx and Rx fifo sizes & other infos in bytes */
 237         u32                             tx_fifo_size;
 238         u32                             tx_fifo_size_gige;
 239         u32                             rx_fifo_size;
 240         u32                             rx_fifo_size_gige;
 241         u32                             fifo_entry_size;
 242         u32                             mal_burst_size; /* move to MAL ? */
 243
 244         /* IAHT and GAHT filter parameterization */
 245         u32                             xaht_slots_shift;
 246         u32                             xaht_width_shift;
 247
 248         /* Descriptor management
 249          */
 250         struct mal_descriptor           *tx_desc;
 251         int                             tx_cnt;
 252         int                             tx_slot;
 253         int                             ack_slot;
 254
 255         struct mal_descriptor           *rx_desc;
 256         int                             rx_slot;
 257         struct sk_buff                  *rx_sg_skb;     /* 1 */
 258         int                             rx_skb_size;
 259         int                             rx_sync_size;
 260
 261         struct sk_buff                  *tx_skb[NUM_TX_BUFF];
 262         struct sk_buff                  *rx_skb[NUM_RX_BUFF];
 263
 264         /* Stats
 265          */
 266         struct emac_error_stats         estats;
 267         struct emac_stats               stats;
 268
 269         /* Misc
 270          */
 271         int                             reset_failed;
 272         int                             stop_timeout;   /* in us */
 273         int                             no_mcast;
 274         int                             mcast_pending;
 275         int                             opened;
 276         struct work_struct              reset_work;
 277         spinlock_t                      lock;
 278 };
 279
 280 /*
 281  * Features of various EMAC implementations
 282  */
 283
 284 /*
 285  * No flow control on 40x according to the original driver
 286  */
 287 #define EMAC_FTR_NO_FLOW_CONTROL_40x    0x00000001
 288 /*
 289  * Cell is an EMAC4
 290  */
 291 #define EMAC_FTR_EMAC4                  0x00000002
 292 /*
 293  * For the 440SPe, AMCC inexplicably changed the polarity of
 294  * the "operation complete" bit in the MII control register.
 295  */
 296 #define EMAC_FTR_STACR_OC_INVERT        0x00000004
 297 /*
 298  * Set if we have a TAH.
 299  */
 300 #define EMAC_FTR_HAS_TAH                0x00000008
 301 /*
 302  * Set if we have a ZMII.
 303  */
 304 #define EMAC_FTR_HAS_ZMII               0x00000010
 305 /*
 306  * Set if we have a RGMII.
 307  */
 308 #define EMAC_FTR_HAS_RGMII              0x00000020
 309 /*
 310  * Set if we have new type STACR with STAOPC
 311  */
 312 #define EMAC_FTR_HAS_NEW_STACR          0x00000040
 313 /*
 314  * Set if we need phy clock workaround for 440gx
 315  */
 316 #define EMAC_FTR_440GX_PHY_CLK_FIX      0x00000080
 317 /*
 318  * Set if we need phy clock workaround for 440ep or 440gr
 319  */
 320 #define EMAC_FTR_440EP_PHY_CLK_FIX      0x00000100
 321 /*
 322  * The 405EX and 460EX contain the EMAC4SYNC core
 323  */
 324 #define EMAC_FTR_EMAC4SYNC              0x00000200
 325 /*
 326  * Set if we need phy clock workaround for 460ex or 460gt
 327  */
 328 #define EMAC_FTR_460EX_PHY_CLK_FIX      0x00000400
 329 /*
 330  * APM821xx requires Jumbo frame size set explicitly
 331  */
 332 #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE      0x00000800
 333 /*
 334  * APM821xx does not support Half Duplex mode
 335  */
 336 #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX        0x00001000
 337
 338 /* Right now, we don't quite handle the always/possible masks on the
 339  * most optimal way as we don't have a way to say something like
 340  * always EMAC4. Patches welcome.
 341  */
 342 enum {
 343         EMAC_FTRS_ALWAYS        = 0,
 344
 345         EMAC_FTRS_POSSIBLE      =
 346 #ifdef CONFIG_IBM_EMAC_EMAC4
 347             EMAC_FTR_EMAC4      | EMAC_FTR_EMAC4SYNC    |
 348             EMAC_FTR_HAS_NEW_STACR      |
 349             EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
 350 #endif
 351 #ifdef CONFIG_IBM_EMAC_TAH
 352             EMAC_FTR_HAS_TAH    |
 353 #endif
 354 #ifdef CONFIG_IBM_EMAC_ZMII
 355             EMAC_FTR_HAS_ZMII   |
 356 #endif
 357 #ifdef CONFIG_IBM_EMAC_RGMII
 358             EMAC_FTR_HAS_RGMII  |
 359 #endif
 360 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
 361             EMAC_FTR_NO_FLOW_CONTROL_40x |
 362 #endif
 363         EMAC_FTR_460EX_PHY_CLK_FIX |
 364         EMAC_FTR_440EP_PHY_CLK_FIX |
 365         EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
 366         EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
 367 };
 368
 369 static inline int emac_has_feature(struct emac_instance *dev,
 370                                    unsigned long feature)
 371 {
 372         return (EMAC_FTRS_ALWAYS & feature) ||
 373                (EMAC_FTRS_POSSIBLE & dev->features & feature);
 374 }
 375
 376 /*
 377  * Various instances of the EMAC core have varying 1) number of
 378  * address match slots, 2) width of the registers for handling address
 379  * match slots, 3) number of registers for handling address match
 380  * slots and 4) base offset for those registers.
 381  *
 382  * These macros and inlines handle these differences based on
 383  * parameters supplied by the device structure which are, in turn,
 384  * initialized based on the "compatible" entry in the device tree.
 385  */
 386
 387 #define EMAC4_XAHT_SLOTS_SHIFT          6
 388 #define EMAC4_XAHT_WIDTH_SHIFT          4
 389
 390 #define EMAC4SYNC_XAHT_SLOTS_SHIFT      8
 391 #define EMAC4SYNC_XAHT_WIDTH_SHIFT      5
 392
 393 #define EMAC_XAHT_SLOTS(dev)            (1 << (dev)->xaht_slots_shift)
 394 #define EMAC_XAHT_WIDTH(dev)            (1 << (dev)->xaht_width_shift)
 395 #define EMAC_XAHT_REGS(dev)             (1 << ((dev)->xaht_slots_shift - \
 396                                                (dev)->xaht_width_shift))
 397
 398 #define EMAC_XAHT_CRC_TO_SLOT(dev, crc)                 \
 399         ((EMAC_XAHT_SLOTS(dev) - 1) -                   \
 400          ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) -    \
 401                     (dev)->xaht_slots_shift)))
 402
 403 #define EMAC_XAHT_SLOT_TO_REG(dev, slot)                \
 404         ((slot) >> (dev)->xaht_width_shift)
 405
 406 #define EMAC_XAHT_SLOT_TO_MASK(dev, slot)               \
 407         ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >>      \
 408          ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
 409
 410 static inline u32 *emac_xaht_base(struct emac_instance *dev)
 411 {
 412         struct emac_regs __iomem *p = dev->emacp;
 413         int offset;
 414
 415         /* The first IAHT entry always is the base of the block of
 416          * IAHT and GAHT registers.
 417          */
 418         if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
 419                 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
 420         else
 421                 offset = offsetof(struct emac_regs, u0.emac4.iaht1);
 422
 423         return (u32 *)((ptrdiff_t)p + offset);
 424 }
 425
 426 static inline u32 *emac_gaht_base(struct emac_instance *dev)
 427 {
 428         /* GAHT registers always come after an identical number of
 429          * IAHT registers.
 430          */
 431         return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev);
 432 }
 433
 434 static inline u32 *emac_iaht_base(struct emac_instance *dev)
 435 {
 436         /* IAHT registers always come before an identical number of
 437          * GAHT registers.
 438          */
 439         return emac_xaht_base(dev);
 440 }
 441
 442 /* Ethtool get_regs complex data.
 443  * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
 444  * when available.
 445  *
 446  * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
 447  * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
 448  * Each register component is preceded with emac_ethtool_regs_subhdr.
 449  * Order of the optional headers follows their relative bit posititions
 450  * in emac_ethtool_regs_hdr.components
 451  */
 452 #define EMAC_ETHTOOL_REGS_ZMII          0x00000001
 453 #define EMAC_ETHTOOL_REGS_RGMII         0x00000002
 454 #define EMAC_ETHTOOL_REGS_TAH           0x00000004
 455
 456 struct emac_ethtool_regs_hdr {
 457         u32 components;
 458 };
 459
 460 struct emac_ethtool_regs_subhdr {
 461         u32 version;
 462         u32 index;
 463 };
 464
 465 #define EMAC_ETHTOOL_REGS_VER           3
 466 #define EMAC4_ETHTOOL_REGS_VER          4
 467 #define EMAC4SYNC_ETHTOOL_REGS_VER      5
 468
 469 #endif /* __IBM_NEWEMAC_CORE_H */