| blob | 1298b69f990b40628ef1fbb353e6d9f1bfafdd76 |
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/interrupt.h>
33 #include <linux/tcp.h>
34 #include <linux/ipv6.h>
35 #include <linux/slab.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/cpu.h>
41 #include <linux/smp.h>
42 #include <linux/pm_qos.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/aer.h>
45 #include <linux/prefetch.h>
55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
75 };
78 u32 ofs;
80 };
83 /* General Registers */
88 /* Interrupt Registers */
91 /* Rx Registers */
107 /* Tx Registers */
124 /* List Terminator */
126 };
128 /**
129 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
130 * @hw: pointer to the HW structure
131 *
132 * When updating the MAC CSR registers, the Manageability Engine (ME) could
133 * be accessing the registers at the same time. Normally, this is handled in
134 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
135 * accesses later than it should which could result in the register to have
136 * an incorrect value. Workaround this by checking the FWSM register which
137 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
138 * and try again a number of times.
139 **/
141 {
148 }
151 {
156 }
158 /**
159 * e1000_regdump - register printout routine
160 * @hw: pointer to the HW structure
161 * @reginfo: pointer to the register info table
162 **/
164 {
186 }
190 }
194 {
206 }
207 }
208 }
210 /**
211 * e1000e_dump - Print registers, Tx-ring and Rx-ring
212 * @adapter: board private structure
213 **/
215 {
222 __le64 a;
223 __le64 b;
230 __le64 a;
231 __le64 b;
232 __le64 c;
233 __le64 d;
235 u32 staterr;
241 /* Print netdevice Info */
247 }
249 /* Print Registers */
255 }
257 /* Print Tx Ring Summary */
271 /* Print Tx Ring */
277 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
278 *
279 * Legacy Transmit Descriptor
280 * +--------------------------------------------------------------+
281 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
282 * +--------------------------------------------------------------+
283 * 8 | Special | CSS | Status | CMD | CSO | Length |
284 * +--------------------------------------------------------------+
285 * 63 48 47 36 35 32 31 24 23 16 15 0
286 *
287 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
288 * 63 48 47 40 39 32 31 16 15 8 7 0
289 * +----------------------------------------------------------------+
290 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
291 * +----------------------------------------------------------------+
292 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
293 * +----------------------------------------------------------------+
294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
295 *
296 * Extended Data Descriptor (DTYP=0x1)
297 * +----------------------------------------------------------------+
298 * 0 | Buffer Address [63:0] |
299 * +----------------------------------------------------------------+
300 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
301 * +----------------------------------------------------------------+
302 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
303 */
304 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
305 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
306 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
318 else
323 i,
335 }
337 /* Print Rx Ring Summary */
338 rx_ring_summary:
344 /* Print Rx Ring */
353 /* [Extended] Packet Split Receive Descriptor Format
354 *
355 * +-----------------------------------------------------+
356 * 0 | Buffer Address 0 [63:0] |
357 * +-----------------------------------------------------+
358 * 8 | Buffer Address 1 [63:0] |
359 * +-----------------------------------------------------+
360 * 16 | Buffer Address 2 [63:0] |
361 * +-----------------------------------------------------+
362 * 24 | Buffer Address 3 [63:0] |
363 * +-----------------------------------------------------+
364 */
365 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
366 /* [Extended] Receive Descriptor (Write-Back) Format
367 *
368 * 63 48 47 32 31 13 12 8 7 4 3 0
369 * +------------------------------------------------------+
370 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
371 * | Checksum | Ident | | Queue | | Type |
372 * +------------------------------------------------------+
373 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
374 * +------------------------------------------------------+
375 * 63 48 47 32 31 20 19 0
376 */
377 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
383 staterr =
390 else
394 /* Descriptor Done */
414 buffer_info);
415 }
416 }
420 /* Extended Receive Descriptor (Read) Format
421 *
422 * +-----------------------------------------------------+
423 * 0 | Buffer Address [63:0] |
424 * +-----------------------------------------------------+
425 * 8 | Reserved |
426 * +-----------------------------------------------------+
427 */
428 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
429 /* Extended Receive Descriptor (Write-Back) Format
430 *
431 * 63 48 47 32 31 24 23 4 3 0
432 * +------------------------------------------------------+
433 * | RSS Hash | | | |
434 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
435 * | Packet | IP | | | Type |
436 * | Checksum | Ident | | | |
437 * +------------------------------------------------------+
438 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
439 * +------------------------------------------------------+
440 * 63 48 47 32 31 20 19 0
441 */
456 else
460 /* Descriptor Done */
482 }
483 }
484 }
485 }
487 /**
488 * e1000_desc_unused - calculate if we have unused descriptors
489 **/
491 {
496 }
498 /**
499 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
500 * @adapter: board private structure
501 * @hwtstamps: time stamp structure to update
502 * @systim: unsigned 64bit system time value.
503 *
504 * Convert the system time value stored in the RX/TXSTMP registers into a
505 * hwtstamp which can be used by the upper level time stamping functions.
506 *
507 * The 'systim_lock' spinlock is used to protect the consistency of the
508 * system time value. This is needed because reading the 64 bit time
509 * value involves reading two 32 bit registers. The first read latches the
510 * value.
511 **/
514 u64 systim)
515 {
516 u64 ns;
525 }
527 /**
528 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
529 * @adapter: board private structure
530 * @status: descriptor extended error and status field
531 * @skb: particular skb to include time stamp
532 *
533 * If the time stamp is valid, convert it into the timecounter ns value
534 * and store that result into the shhwtstamps structure which is passed
535 * up the network stack.
536 **/
539 {
541 u64 rxstmp;
548 /* The Rx time stamp registers contain the time stamp. No other
549 * received packet will be time stamped until the Rx time stamp
550 * registers are read. Because only one packet can be time stamped
551 * at a time, the register values must belong to this packet and
552 * therefore none of the other additional attributes need to be
553 * compared.
554 */
560 }
562 /**
563 * e1000_receive_skb - helper function to handle Rx indications
564 * @adapter: board private structure
565 * @staterr: descriptor extended error and status field as written by hardware
566 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
567 * @skb: pointer to sk_buff to be indicated to stack
568 **/
572 {
583 }
585 /**
586 * e1000_rx_checksum - Receive Checksum Offload
587 * @adapter: board private structure
588 * @status_err: receive descriptor status and error fields
589 * @csum: receive descriptor csum field
590 * @sk_buff: socket buffer with received data
591 **/
594 {
600 /* Rx checksum disabled */
604 /* Ignore Checksum bit is set */
608 /* TCP/UDP checksum error bit or IP checksum error bit is set */
610 /* let the stack verify checksum errors */
613 }
615 /* TCP/UDP Checksum has not been calculated */
619 /* It must be a TCP or UDP packet with a valid checksum */
622 }
625 {
638 }
639 }
642 {
655 }
656 }
658 /**
659 * e1000_alloc_rx_buffers - Replace used receive buffers
660 * @rx_ring: Rx descriptor ring
661 **/
664 {
682 }
686 /* Better luck next round */
689 }
692 map_skb:
695 DMA_FROM_DEVICE);
700 }
706 /* Force memory writes to complete before letting h/w
707 * know there are new descriptors to fetch. (Only
708 * applicable for weak-ordered memory model archs,
709 * such as IA-64).
710 */
714 else
716 }
717 i++;
721 }
724 }
726 /**
727 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
728 * @rx_ring: Rx descriptor ring
729 **/
732 {
751 /* all unused desc entries get hw null ptr */
755 }
761 }
765 DMA_FROM_DEVICE);
772 }
773 }
774 /* Refresh the desc even if buffer_addrs
775 * didn't change because each write-back
776 * erases this info.
777 */
780 }
783 gfp);
788 }
793 DMA_FROM_DEVICE);
797 /* cleanup skb */
801 }
806 /* Force memory writes to complete before letting h/w
807 * know there are new descriptors to fetch. (Only
808 * applicable for weak-ordered memory model archs,
809 * such as IA-64).
810 */
814 else
816 }
818 i++;
822 }
824 no_buffers:
826 }
828 /**
829 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
830 * @rx_ring: Rx descriptor ring
831 * @cleaned_count: number of buffers to allocate this pass
832 **/
836 {
854 }
858 /* Better luck next round */
861 }
864 check_page:
865 /* allocate a new page if necessary */
871 }
872 }
877 PAGE_SIZE,
878 DMA_FROM_DEVICE);
882 }
883 }
891 }
898 /* Force memory writes to complete before letting h/w
899 * know there are new descriptors to fetch. (Only
900 * applicable for weak-ordered memory model archs,
901 * such as IA-64).
902 */
906 else
908 }
909 }
913 {
916 }
918 /**
919 * e1000_clean_rx_irq - Send received data up the network stack
920 * @rx_ring: Rx descriptor ring
921 *
922 * the return value indicates whether actual cleaning was done, there
923 * is no guarantee that everything was cleaned
924 **/
927 {
958 i++;
967 cleaned_count++;
974 /* !EOP means multiple descriptors were used to store a single
975 * packet, if that's the case we need to toss it. In fact, we
976 * need to toss every packet with the EOP bit clear and the
977 * next frame that _does_ have the EOP bit set, as it is by
978 * definition only a frame fragment
979 */
984 /* All receives must fit into a single buffer */
986 /* recycle */
991 }
995 /* recycle */
998 }
1000 /* adjust length to remove Ethernet CRC */
1002 /* If configured to store CRC, don't subtract FCS,
1003 * but keep the FCS bytes out of the total_rx_bytes
1004 * counter
1005 */
1008 else
1010 }
1013 total_rx_packets++;
1015 /* code added for copybreak, this should improve
1016 * performance for small packets with large amounts
1017 * of reassembly being done in the stack
1018 */
1026 NET_IP_ALIGN),
1028 NET_IP_ALIGN));
1029 /* save the skb in buffer_info as good */
1032 }
1033 /* else just continue with the old one */
1034 }
1035 /* end copybreak code */
1038 /* Receive Checksum Offload */
1046 next_desc:
1049 /* return some buffers to hardware, one at a time is too slow */
1052 GFP_ATOMIC);
1054 }
1056 /* use prefetched values */
1061 }
1071 }
1076 {
1083 else
1087 }
1091 else
1094 }
1096 }
1099 {
1102 print_hang_task);
1110 u16 pci_status;
1116 /* May be block on write-back, flush and detect again
1117 * flush pending descriptor writebacks to memory
1118 */
1120 /* execute the writes immediately */
1122 /* Due to rare timing issues, write to TIDV again to ensure
1123 * the write is successful
1124 */
1126 /* execute the writes immediately */
1130 }
1136 }
1138 /* Real hang detected */
1147 /* detected Hardware unit hang */
1170 /* Suggest workaround for known h/w issue */
1173 }
1175 /**
1176 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1177 * @work: pointer to work struct
1178 *
1179 * This work function polls the TSYNCTXCTL valid bit to determine when a
1180 * timestamp has been taken for the current stored skb. The timestamp must
1181 * be for this skb because only one such packet is allowed in the queue.
1182 */
1184 {
1186 tx_hwtstamp_work);
1192 u64 txstmp;
1199 /* Clear the global tx_hwtstamp_skb pointer and force writes
1200 * prior to notifying the stack of a Tx timestamp.
1201 */
1214 /* reschedule to check later */
1216 }
1217 }
1219 /**
1220 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1221 * @tx_ring: Tx descriptor ring
1222 *
1223 * the return value indicates whether actual cleaning was done, there
1224 * is no guarantee that everything was cleaned
1225 **/
1227 {
1257 pkts_compl++;
1258 }
1259 }
1264 i++;
1267 }
1273 }
1279 #define TX_WAKE_THRESHOLD 32
1282 /* Make sure that anybody stopping the queue after this
1283 * sees the new next_to_clean.
1284 */
1291 }
1292 }
1295 /* Detect a transmit hang in hardware, this serializes the
1296 * check with the clearing of time_stamp and movement of i
1297 */
1304 else
1306 }
1310 }
1312 /**
1313 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1314 * @rx_ring: Rx descriptor ring
1315 *
1316 * the return value indicates whether actual cleaning was done, there
1317 * is no guarantee that everything was cleaned
1318 **/
1321 {
1348 /* in the packet split case this is header only */
1351 i++;
1360 cleaned_count++;
1365 /* see !EOP comment in other Rx routine */
1375 }
1381 }
1389 }
1391 /* Good Receive */
1394 {
1395 /* this looks ugly, but it seems compiler issues make
1396 * it more efficient than reusing j
1397 */
1400 /* page alloc/put takes too long and effects small
1401 * packet throughput, so unsplit small packets and
1402 * save the alloc/put only valid in softirq (napi)
1403 * context to call kmap_*
1404 */
1411 /* there is no documentation about how to call
1412 * kmap_atomic, so we can't hold the mapping
1413 * very long
1414 */
1417 PAGE_SIZE,
1418 DMA_FROM_DEVICE);
1424 PAGE_SIZE,
1425 DMA_FROM_DEVICE);
1427 /* remove the CRC */
1431 }
1436 }
1445 DMA_FROM_DEVICE);
1452 }
1454 /* strip the ethernet crc, problem is we're using pages now so
1455 * this whole operation can get a little cpu intensive
1456 */
1460 }
1462 copydone:
1464 total_rx_packets++;
1477 next_desc:
1481 /* return some buffers to hardware, one at a time is too slow */
1484 GFP_ATOMIC);
1486 }
1488 /* use prefetched values */
1493 }
1503 }
1505 /**
1506 * e1000_consume_page - helper function
1507 **/
1509 u16 length)
1510 {
1515 }
1517 /**
1518 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1519 * @adapter: board private structure
1520 *
1521 * the return value indicates whether actual cleaning was done, there
1522 * is no guarantee that everything was cleaned
1523 **/
1526 {
1564 cleaned_count++;
1566 DMA_FROM_DEVICE);
1571 /* errors is only valid for DD + EOP descriptors */
1575 /* recycle both page and skb */
1577 /* an error means any chain goes out the window too */
1582 }
1583 #define rxtop (rx_ring->rx_skb_top)
1585 /* this descriptor is only the beginning (or middle) */
1587 /* this is the beginning of a chain */
1592 /* this is the middle of a chain */
1596 length);
1597 /* re-use the skb, only consumed the page */
1599 }
1604 /* end of the chain */
1608 length);
1609 /* re-use the current skb, we only consumed the
1610 * page
1611 */
1617 /* no chain, got EOP, this buf is the packet
1618 * copybreak to save the put_page/alloc_page
1619 */
1625 length);
1627 /* re-use the page, so don't erase
1628 * buffer_info->page
1629 */
1634 length);
1636 length);
1637 }
1638 }
1639 }
1641 /* Receive Checksum Offload */
1646 /* probably a little skewed due to removing CRC */
1648 total_rx_packets++;
1650 /* eth type trans needs skb->data to point to something */
1655 }
1660 next_desc:
1663 /* return some buffers to hardware, one at a time is too slow */
1666 GFP_ATOMIC);
1668 }
1670 /* use prefetched values */
1675 }
1685 }
1687 /**
1688 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1689 * @rx_ring: Rx descriptor ring
1690 **/
1692 {
1699 /* Free all the Rx ring sk_buffs */
1706 DMA_FROM_DEVICE);
1713 DMA_FROM_DEVICE);
1715 }
1720 }
1725 }
1732 DMA_FROM_DEVICE);
1736 }
1737 }
1739 /* there also may be some cached data from a chained receive */
1743 }
1745 /* Zero out the descriptor ring */
1751 }
1754 {
1757 downshift_task);
1763 }
1765 /**
1766 * e1000_intr_msi - Interrupt Handler
1767 * @irq: interrupt number
1768 * @data: pointer to a network interface device structure
1769 **/
1771 {
1777 /* read ICR disables interrupts using IAM */
1780 /* ICH8 workaround-- Call gig speed drop workaround on cable
1781 * disconnect (LSC) before accessing any PHY registers
1782 */
1787 /* 80003ES2LAN workaround-- For packet buffer work-around on
1788 * link down event; disable receives here in the ISR and reset
1789 * adapter in watchdog
1790 */
1793 /* disable receives */
1798 }
1799 /* guard against interrupt when we're going down */
1802 }
1804 /* Reset on uncorrectable ECC error */
1812 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1814 /* Do the reset outside of interrupt context */
1817 /* return immediately since reset is imminent */
1819 }
1827 }
1830 }
1832 /**
1833 * e1000_intr - Interrupt Handler
1834 * @irq: interrupt number
1835 * @data: pointer to a network interface device structure
1836 **/
1838 {
1847 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1848 * not set, then the adapter didn't send an interrupt
1849 */
1853 /* Interrupt Auto-Mask...upon reading ICR,
1854 * interrupts are masked. No need for the
1855 * IMC write
1856 */
1860 /* ICH8 workaround-- Call gig speed drop workaround on cable
1861 * disconnect (LSC) before accessing any PHY registers
1862 */
1867 /* 80003ES2LAN workaround--
1868 * For packet buffer work-around on link down event;
1869 * disable receives here in the ISR and
1870 * reset adapter in watchdog
1871 */
1874 /* disable receives */
1878 }
1879 /* guard against interrupt when we're going down */
1882 }
1884 /* Reset on uncorrectable ECC error */
1892 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1894 /* Do the reset outside of interrupt context */
1897 /* return immediately since reset is imminent */
1899 }
1907 }
1910 }
1913 {
1917 u32 icr;
1924 /* napi poll will re-enable Other, make sure it runs */
1929 }
1930 }
1934 /* guard against interrupt when we're going down */
1937 }
1943 }
1946 {
1956 /* Ring was not completely cleaned, so fire another interrupt */
1963 }
1966 {
1971 /* Write the ITR value calculated at the end of the
1972 * previous interrupt.
1973 */
1980 }
1986 }
1988 }
1990 /**
1991 * e1000_configure_msix - Configure MSI-X hardware
1992 *
1993 * e1000_configure_msix sets up the hardware to properly
1994 * generate MSI-X interrupts.
1995 **/
1997 {
2006 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
2012 }
2014 /* Configure Rx vector */
2020 else
2024 /* Configure Tx vector */
2026 vector++;
2030 else
2035 /* set vector for Other Causes, e.g. link changes */
2036 vector++;
2041 else
2045 /* Cause Tx interrupts on every write back */
2050 /* enable MSI-X PBA support */
2055 }
2058 {
2066 }
2067 }
2069 /**
2070 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2071 *
2072 * Attempt to configure interrupts using the best available
2073 * capabilities of the hardware and kernel.
2074 **/
2076 {
2086 msix_entry),
2087 GFP_KERNEL);
2100 }
2101 /* MSI-X failed, so fall through and try MSI */
2104 }
2106 /* Fall through */
2113 }
2114 /* Fall through */
2116 /* Don't do anything; this is the system default */
2118 }
2120 /* store the number of vectors being used */
2122 }
2124 /**
2125 * e1000_request_msix - Initialize MSI-X interrupts
2126 *
2127 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2128 * kernel.
2129 **/
2131 {
2139 else
2143 netdev);
2149 vector++;
2155 else
2159 netdev);
2165 vector++;
2175 }
2177 /**
2178 * e1000_request_irq - initialize interrupts
2179 *
2180 * Attempts to configure interrupts using the best available
2181 * capabilities of the hardware and kernel.
2182 **/
2184 {
2192 /* fall back to MSI */
2196 }
2203 /* fall back to legacy interrupt */
2206 }
2214 }
2217 {
2224 vector++;
2227 vector++;
2229 /* Other Causes interrupt vector */
2232 }
2235 }
2237 /**
2238 * e1000_irq_disable - Mask off interrupt generation on the NIC
2239 **/
2241 {
2256 }
2257 }
2259 /**
2260 * e1000_irq_enable - Enable default interrupt generation settings
2261 **/
2263 {
2273 }
2275 }
2277 /**
2278 * e1000e_get_hw_control - get control of the h/w from f/w
2279 * @adapter: address of board private structure
2280 *
2281 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2282 * For ASF and Pass Through versions of f/w this means that
2283 * the driver is loaded. For AMT version (only with 82573)
2284 * of the f/w this means that the network i/f is open.
2285 **/
2287 {
2289 u32 ctrl_ext;
2290 u32 swsm;
2292 /* Let firmware know the driver has taken over */
2299 }
2300 }
2302 /**
2303 * e1000e_release_hw_control - release control of the h/w to f/w
2304 * @adapter: address of board private structure
2305 *
2306 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2307 * For ASF and Pass Through versions of f/w this means that the
2308 * driver is no longer loaded. For AMT version (only with 82573) i
2309 * of the f/w this means that the network i/f is closed.
2310 *
2311 **/
2313 {
2315 u32 ctrl_ext;
2316 u32 swsm;
2318 /* Let firmware taken over control of h/w */
2325 }
2326 }
2328 /**
2329 * e1000_alloc_ring_dma - allocate memory for a ring structure
2330 **/
2333 {
2337 GFP_KERNEL);
2342 }
2344 /**
2345 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2346 * @tx_ring: Tx descriptor ring
2347 *
2348 * Return 0 on success, negative on failure
2349 **/
2351 {
2360 /* round up to nearest 4K */
2372 err:
2376 }
2378 /**
2379 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2380 * @rx_ring: Rx descriptor ring
2381 *
2382 * Returns 0 on success, negative on failure
2383 **/
2385 {
2399 GFP_KERNEL);
2402 }
2406 /* Round up to nearest 4K */
2420 err_pages:
2424 }
2425 err:
2429 }
2431 /**
2432 * e1000_clean_tx_ring - Free Tx Buffers
2433 * @tx_ring: Tx descriptor ring
2434 **/
2436 {
2445 }
2455 }
2457 /**
2458 * e1000e_free_tx_resources - Free Tx Resources per Queue
2459 * @tx_ring: Tx descriptor ring
2460 *
2461 * Free all transmit software resources
2462 **/
2464 {
2476 }
2478 /**
2479 * e1000e_free_rx_resources - Free Rx Resources
2480 * @rx_ring: Rx descriptor ring
2481 *
2482 * Free all receive software resources
2483 **/
2485 {
2501 }
2503 /**
2504 * e1000_update_itr - update the dynamic ITR value based on statistics
2505 * @adapter: pointer to adapter
2506 * @itr_setting: current adapter->itr
2507 * @packets: the number of packets during this measurement interval
2508 * @bytes: the number of bytes during this measurement interval
2509 *
2510 * Stores a new ITR value based on packets and byte
2511 * counts during the last interrupt. The advantage of per interrupt
2512 * computation is faster updates and more accurate ITR for the current
2513 * traffic pattern. Constants in this function were computed
2514 * based on theoretical maximum wire speed and thresholds were set based
2515 * on testing data as well as attempting to minimize response time
2516 * while increasing bulk throughput. This functionality is controlled
2517 * by the InterruptThrottleRate module parameter.
2518 **/
2520 {
2528 /* handle TSO and jumbo frames */
2536 /* this if handles the TSO accounting */
2547 }
2555 }
2557 }
2560 }
2563 {
2564 u16 current_itr;
2567 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2572 }
2577 }
2582 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2589 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2595 /* counts and packets in update_itr are dependent on these numbers */
2608 }
2610 set_itr_now:
2612 /* this attempts to bias the interrupt rate towards Bulk
2613 * by adding intermediate steps when interrupt rate is
2614 * increasing
2615 */
2622 else
2624 }
2625 }
2627 /**
2628 * e1000e_write_itr - write the ITR value to the appropriate registers
2629 * @adapter: address of board private structure
2630 * @itr: new ITR value to program
2631 *
2632 * e1000e_write_itr determines if the adapter is in MSI-X mode
2633 * and, if so, writes the EITR registers with the ITR value.
2634 * Otherwise, it writes the ITR value into the ITR register.
2635 **/
2637 {
2648 }
2649 }
2651 /**
2652 * e1000_alloc_queues - Allocate memory for all rings
2653 * @adapter: board private structure to initialize
2654 **/
2656 {
2672 err:
2677 }
2679 /**
2680 * e1000e_poll - NAPI Rx polling callback
2681 * @napi: struct associated with this polling callback
2682 * @weight: number of packets driver is allowed to process this poll
2683 **/
2685 {
2687 napi);
2703 /* If weight not fully consumed, exit the polling mode */
2711 E1000_IMS_OTHER);
2712 else
2714 }
2715 }
2718 }
2722 {
2727 /* don't update vlan cookie if already programmed */
2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2733 /* add VID to filter table */
2739 }
2744 }
2748 {
2754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2756 /* release control to f/w */
2759 }
2761 /* remove VID from filter table */
2767 }
2772 }
2774 /**
2775 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2776 * @adapter: board private structure to initialize
2777 **/
2779 {
2782 u32 rctl;
2785 /* disable VLAN receive filtering */
2794 }
2795 }
2796 }
2798 /**
2799 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2800 * @adapter: board private structure to initialize
2801 **/
2803 {
2805 u32 rctl;
2808 /* enable VLAN receive filtering */
2813 }
2814 }
2816 /**
2817 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2818 * @adapter: board private structure to initialize
2819 **/
2821 {
2823 u32 ctrl;
2825 /* disable VLAN tag insert/strip */
2829 }
2831 /**
2832 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2833 * @adapter: board private structure to initialize
2834 **/
2836 {
2838 u32 ctrl;
2840 /* enable VLAN tag insert/strip */
2844 }
2847 {
2855 }
2859 }
2862 {
2863 u16 vid;
2869 }
2872 {
2881 /* enable receiving management packets to the host. this will probably
2882 * generate destination unreachable messages from the host OS, but
2883 * the packets will be handled on SMBUS
2884 */
2894 /* Check if IPMI pass-through decision filter already exists;
2895 * if so, enable it.
2896 */
2900 /* Ignore filters with anything other than IPMI ports */
2904 /* Enable this decision filter in MANC2H */
2909 }
2914 /* Create new decision filter in an empty filter */
2918 E1000_MDEF_PORT_664));
2920 j++;
2922 }
2927 }
2931 }
2933 /**
2934 * e1000_configure_tx - Configure Transmit Unit after Reset
2935 * @adapter: board private structure
2936 *
2937 * Configure the Tx unit of the MAC after a reset.
2938 **/
2940 {
2943 u64 tdba;
2946 /* Setup the HW Tx Head and Tail descriptor pointers */
2960 else
2963 /* Set the Tx Interrupt Delay register */
2965 /* Tx irq moderation */
2972 E1000_TXDCTL_WTHRESH);
2973 /* set up some performance related parameters to encourage the
2974 * hardware to use the bus more efficiently in bursts, depends
2975 * on the tx_int_delay to be enabled,
2976 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2977 * hthresh = 1 ==> prefetch when one or more available
2978 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2979 * BEWARE: this seems to work but should be considered first if
2980 * there are Tx hangs or other Tx related bugs
2981 */
2984 }
2985 /* erratum work around: set txdctl the same for both queues */
2988 /* Program the Transmit Control Register */
2996 /* set the speed mode bit, we'll clear it if we're not at
2997 * gigabit link later
2998 */
2999 #define SPEED_MODE_BIT BIT(21)
3002 }
3004 /* errata: program both queues to unweighted RR */
3012 }
3014 /* Setup Transmit Descriptor Settings for eop descriptor */
3017 /* only set IDE if we are delaying interrupts using the timers */
3021 /* enable Report Status bit */
3028 /* SPT and KBL Si errata workaround to avoid data corruption */
3030 u32 reg_val;
3037 /* SPT and KBL Si errata workaround to avoid Tx hang.
3038 * Dropping the number of outstanding requests from
3039 * 3 to 2 in order to avoid a buffer overrun.
3040 */
3044 }
3045 }
3047 /**
3048 * e1000_setup_rctl - configure the receive control registers
3049 * @adapter: Board private structure
3050 **/
3051 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3052 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3054 {
3059 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3060 * If jumbo frames not set, program related MAC/PHY registers
3061 * to h/w defaults
3062 */
3064 s32 ret_val;
3068 else
3073 }
3075 /* Program MC offset vector base */
3082 /* Do not Store bad packets */
3085 /* Enable Long Packet receive */
3088 else
3091 /* Some systems expect that the CRC is included in SMBUS traffic. The
3092 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3093 * host memory when this is enabled
3094 */
3098 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3100 u16 phy_data;
3113 }
3115 /* Setup buffer sizes */
3133 }
3135 /* Enable Extended Status in all Receive Descriptors */
3140 /* 82571 and greater support packet-split where the protocol
3141 * header is placed in skb->data and the packet data is
3142 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3143 * In the case of a non-split, skb->data is linearly filled,
3144 * followed by the page buffers. Therefore, skb->data is
3145 * sized to hold the largest protocol header.
3146 *
3147 * allocations using alloc_page take too long for regular MTU
3148 * so only enable packet split for jumbo frames
3149 *
3150 * Using pages when the page size is greater than 16k wastes
3151 * a lot of memory, since we allocate 3 pages at all times
3152 * per packet.
3153 */
3157 else
3163 /* Enable Packet split descriptors */
3171 /* fall-through */
3174 /* fall-through */
3178 }
3181 }
3183 /* This is useful for sniffing bad packets. */
3185 /* UPE and MPE will be handled by normal PROMISC logic
3186 * in e1000e_set_rx_mode
3187 */
3195 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3196 * and that breaks VLANs.
3197 */
3198 }
3201 /* just started the receive unit, no need to restart */
3203 }
3205 /**
3206 * e1000_configure_rx - Configure Receive Unit after Reset
3207 * @adapter: board private structure
3208 *
3209 * Configure the Rx unit of the MAC after a reset.
3210 **/
3212 {
3215 u64 rdba;
3219 /* this is a 32 byte descriptor */
3232 }
3234 /* disable receives while setting up the descriptors */
3242 /* set the writeback threshold (only takes effect if the RDTR
3243 * is set). set GRAN=1 and write back up to 0x4 worth, and
3244 * enable prefetching of 0x20 Rx descriptors
3245 * granularity = 01
3246 * wthresh = 04,
3247 * hthresh = 04,
3248 * pthresh = 0x20
3249 */
3252 }
3254 /* set the Receive Delay Timer Register */
3257 /* irq moderation */
3263 /* Auto-Mask interrupts upon ICR access */
3269 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3270 * the Base and Length of the Rx Descriptor Ring
3271 */
3284 else
3287 /* Enable Receive Checksum Offload for TCP and UDP */
3291 else
3295 /* With jumbo frames, excessive C-state transition latencies result
3296 * in dropped transactions.
3297 */
3299 u32 lat =
3307 }
3314 PM_QOS_DEFAULT_VALUE);
3315 }
3317 /* Enable Receives */
3319 }
3321 /**
3322 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3323 * @netdev: network interface device structure
3324 *
3325 * Writes multicast address list to the MTA hash table.
3326 * Returns: -ENOMEM on failure
3327 * 0 on no addresses written
3328 * X on writing X addresses to MTA
3329 */
3331 {
3339 /* nothing to program, so clear mc list */
3342 }
3348 /* update_mc_addr_list expects a packed array of only addresses. */
3357 }
3359 /**
3360 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3361 * @netdev: network interface device structure
3362 *
3363 * Writes unicast address list to the RAR table.
3364 * Returns: -ENOMEM on failure/insufficient address space
3365 * 0 on no addresses written
3366 * X on writing X addresses to the RAR table
3367 **/
3369 {
3377 /* save a rar entry for our hardware address */
3378 rar_entries--;
3380 /* save a rar entry for the LAA workaround */
3382 rar_entries--;
3384 /* return ENOMEM indicating insufficient memory for addresses */
3391 /* write the addresses in reverse order to avoid write
3392 * combining
3393 */
3402 count++;
3403 }
3404 }
3406 /* zero out the remaining RAR entries not used above */
3410 }
3414 }
3416 /**
3417 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3418 * @netdev: network interface device structure
3419 *
3420 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3421 * address list or the network interface flags are updated. This routine is
3422 * responsible for configuring the hardware for proper unicast, multicast,
3423 * promiscuous mode, and all-multi behavior.
3424 **/
3426 {
3429 u32 rctl;
3434 /* Check for Promiscuous and All Multicast modes */
3437 /* clear the affected bits */
3442 /* Do not hardware filter VLANs in promisc mode */
3450 /* Write addresses to the MTA, if the attempt fails
3451 * then we should just turn on promiscuous mode so
3452 * that we can at least receive multicast traffic
3453 */
3457 }
3459 /* Write addresses to available RAR registers, if there is not
3460 * sufficient space to store all the addresses then enable
3461 * unicast promiscuous mode
3462 */
3466 }
3472 else
3474 }
3477 {
3487 /* Direct all traffic to queue 0 */
3491 /* Disable raw packet checksumming so that RSS hash is placed in
3492 * descriptor on writeback.
3493 */
3500 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3501 E1000_MRQC_RSS_FIELD_IPV6 |
3502 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3503 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3506 }
3508 /**
3509 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3510 * @adapter: board private structure
3511 * @timinca: pointer to returned time increment attributes
3512 *
3513 * Get attributes for incrementing the System Time Register SYSTIML/H at
3514 * the default base frequency, and set the cyclecounter shift value.
3515 **/
3517 {
3521 /* Make sure clock is enabled on I217/I218/I219 before checking
3522 * the frequency
3523 */
3532 }
3533 }
3537 /* Stable 96MHz frequency */
3545 /* Stable 96MHz frequency */
3551 /* Stable 25MHz frequency */
3556 }
3560 /* Stable 24MHz frequency */
3566 }
3570 /* Stable 24MHz frequency */
3576 /* Stable 38400KHz frequency */
3581 }
3585 /* Stable 25MHz frequency */
3593 }
3599 }
3601 /**
3602 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3603 * @adapter: board private structure
3604 *
3605 * Outgoing time stamping can be enabled and disabled. Play nice and
3606 * disable it when requested, although it shouldn't cause any overhead
3607 * when no packet needs it. At most one packet in the queue may be
3608 * marked for time stamping, otherwise it would be impossible to tell
3609 * for sure to which packet the hardware time stamp belongs.
3610 *
3611 * Incoming time stamping has to be configured via the hardware filters.
3612 * Not all combinations are supported, in particular event type has to be
3613 * specified. Matching the kind of event packet is not supported, with the
3614 * exception of "all V2 events regardless of level 2 or 4".
3615 **/
3618 {
3626 u32 regval;
3631 /* flags reserved for future extensions - must be zero */
3643 }
3660 /* Also time stamps V2 L2 Path Delay Request/Response */
3666 /* Also time stamps V2 L2 Path Delay Request/Response. */
3672 /* Hardware cannot filter just V2 L4 Sync messages;
3673 * fall-through to V2 (both L2 and L4) Sync.
3674 */
3676 /* Also time stamps V2 Path Delay Request/Response. */
3683 /* Hardware cannot filter just V2 L4 Delay Request messages;
3684 * fall-through to V2 (both L2 and L4) Delay Request.
3685 */
3687 /* Also time stamps V2 Path Delay Request/Response. */
3695 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3696 * fall-through to all V2 (both L2 and L4) Events.
3697 */
3705 /* For V1, the hardware can only filter Sync messages or
3706 * Delay Request messages but not both so fall-through to
3707 * time stamp all packets.
3708 */
3718 }
3722 /* enable/disable Tx h/w time stamping */
3731 }
3733 /* enable/disable Rx h/w time stamping */
3739 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3741 E1000_TSYNCRXCTL_TYPE_MASK))) {
3744 }
3746 /* L2: define ethertype filter for time stamped packets */
3750 /* define which PTP packets get time stamped */
3753 /* Filter by destination port */
3757 }
3762 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3767 }
3769 /**
3770 * e1000_configure - configure the hardware for Rx and Tx
3771 * @adapter: private board structure
3772 **/
3774 {
3789 }
3791 /**
3792 * e1000e_power_up_phy - restore link in case the phy was powered down
3793 * @adapter: address of board private structure
3794 *
3795 * The phy may be powered down to save power and turn off link when the
3796 * driver is unloaded and wake on lan is not enabled (among others)
3797 * *** this routine MUST be followed by a call to e1000e_reset ***
3798 **/
3800 {
3805 }
3807 /**
3808 * e1000_power_down_phy - Power down the PHY
3809 *
3810 * Power down the PHY so no link is implied when interface is down.
3811 * The PHY cannot be powered down if management or WoL is active.
3812 */
3814 {
3817 }
3819 /**
3820 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3821 *
3822 * We want to clear all pending descriptors from the TX ring.
3823 * zeroing happens when the HW reads the regs. We assign the ring itself as
3824 * the data of the next descriptor. We don't care about the data we are about
3825 * to reset the HW.
3826 */
3828 {
3844 /* flush descriptors to memory before notifying the HW */
3852 }
3854 /**
3855 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3856 *
3857 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3858 */
3860 {
3870 /* zero the lower 14 bits (prefetch and host thresholds) */
3873 /* update thresholds: prefetch threshold to 31, host threshold to 1
3874 * and make sure the granularity is "descriptors" and not "cache lines"
3875 */
3879 /* momentarily enable the RX ring for the changes to take effect */
3884 }
3886 /**
3887 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3888 *
3889 * In i219, the descriptor rings must be emptied before resetting the HW
3890 * or before changing the device state to D3 during runtime (runtime PM).
3891 *
3892 * Failure to do this will cause the HW to enter a unit hang state which can
3893 * only be released by PCI reset on the device
3894 *
3895 */
3898 {
3899 u16 hang_state;
3903 /* First, disable MULR fix in FEXTNVM11 */
3907 /* do nothing if we're not in faulty state, or if the queue is empty */
3914 /* recheck, maybe the fault is caused by the rx ring */
3919 }
3921 /**
3922 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3923 * @adapter: board private structure
3924 *
3925 * When the MAC is reset, all hardware bits for timesync will be reset to the
3926 * default values. This function will restore the settings last in place.
3927 * Since the clock SYSTIME registers are reset, we will simply restore the
3928 * cyclecounter to the kernel real clock time.
3929 **/
3931 {
3935 u32 timinca;
3936 s32 ret_val;
3942 /* restore the previous ptp frequency delta */
3945 /* set the default base frequency if no adjustment possible */
3949 }
3954 ret_val);
3956 }
3958 /* reset the systim ns time counter */
3964 /* restore the previous hwtstamp configuration settings */
3966 }
3968 /**
3969 * e1000e_reset - bring the hardware into a known good state
3970 *
3971 * This function boots the hardware and enables some settings that
3972 * require a configuration cycle of the hardware - those cannot be
3973 * set/changed during runtime. After reset the device needs to be
3974 * properly configured for Rx, Tx etc.
3975 */
3977 {
3983 u16 hwm;
3985 /* reset Packet Buffer Allocation to default */
3989 /* To maintain wire speed transmits, the Tx FIFO should be
3990 * large enough to accommodate two full transmit packets,
3991 * rounded up to the next 1KB and expressed in KB. Likewise,
3992 * the Rx FIFO should be large enough to accommodate at least
3993 * one full receive packet and is similarly rounded up and
3994 * expressed in KB.
3995 */
3997 /* upper 16 bits has Tx packet buffer allocation size in KB */
3999 /* lower 16 bits has Rx packet buffer allocation size in KB */
4001 /* the Tx fifo also stores 16 bytes of information about the Tx
4002 * but don't include ethernet FCS because hardware appends it
4003 */
4008 /* software strips receive CRC, so leave room for it */
4013 /* If current Tx allocation is less than the min Tx FIFO size,
4014 * and the min Tx FIFO size is less than the current Rx FIFO
4015 * allocation, take space away from current Rx allocation
4016 */
4021 /* if short on Rx space, Rx wins and must trump Tx
4022 * adjustment
4023 */
4026 }
4029 }
4031 /* flow control settings
4032 *
4033 * The high water mark must be low enough to fit one full frame
4034 * (or the size used for early receive) above it in the Rx FIFO.
4035 * Set it to the lower of:
4036 * - 90% of the Rx FIFO size, and
4037 * - the full Rx FIFO size minus one full frame
4038 */
4041 else
4055 }
4056 /* fall-through */
4065 /* Workaround PCH LOM adapter hangs with certain network
4066 * loads. If hangs persist, try disabling Tx flow control.
4067 */
4074 }
4088 }
4095 }
4097 /* Alignment of Tx data is on an arbitrary byte boundary with the
4098 * maximum size per Tx descriptor limited only to the transmit
4099 * allocation of the packet buffer minus 96 bytes with an upper
4100 * limit of 24KB due to receive synchronization limitations.
4101 */
4105 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4106 * fit in receive buffer.
4107 */
4115 }
4122 }
4123 }
4127 /* Allow time for pending master requests to run */
4130 /* For parts with AMT enabled, let the firmware know
4131 * that the network interface is in control
4132 */
4143 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4148 /* restore systim and hwtstamp settings */
4151 /* Set EEE advertisement as appropriate */
4153 s32 ret_val;
4154 u16 adv_addr;
4167 }
4174 }
4181 }
4192 /* speed up time to link by disabling smart power down, ignore
4193 * the return value of this function because there is nothing
4194 * different we would do if it failed
4195 */
4199 }
4201 u32 reg;
4203 /* Fextnvm7 @ 0xe4[2] = 1 */
4207 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4210 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4212 }
4214 }
4216 /**
4217 * e1000e_trigger_lsc - trigger an LSC interrupt
4218 * @adapter:
4219 *
4220 * Fire a link status change interrupt to start the watchdog.
4221 **/
4223 {
4228 else
4230 }
4233 {
4234 /* hardware has been reset, we need to reload some things */
4246 }
4249 {
4255 /* flush pending descriptor writebacks to memory */
4259 /* execute the writes immediately */
4262 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4263 * write is successful
4264 */
4268 /* execute the writes immediately */
4270 }
4274 /**
4275 * e1000e_down - quiesce the device and optionally reset the hardware
4276 * @adapter: board private structure
4277 * @reset: boolean flag to reset the hardware or not
4278 */
4280 {
4285 /* signal that we're down so the interrupt handler does not
4286 * reschedule our watchdog timer
4287 */
4292 /* disable receives in the hardware */
4296 /* flush and sleep below */
4300 /* disable transmits in the hardware */
4305 /* flush both disables and wait for them to finish */
4325 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4336 }
4339 }
4342 {
4349 }
4351 /**
4352 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4353 * @hw: pointer to the HW structure
4354 * @systim: time value read, sanitized and returned
4355 *
4356 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4357 * check to see that the time is incrementing at a reasonable
4358 * rate and is a multiple of incvalue.
4359 **/
4361 {
4363 u64 systim_next;
4364 u32 incvalue;
4369 /* latch SYSTIMH on read of SYSTIML */
4375 /* VMWare users have seen incvalue of zero, don't div / 0 */
4382 }
4385 }
4387 /**
4388 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4389 * @cc: cyclecounter structure
4390 **/
4392 {
4394 cc);
4397 u64 systim;
4398 /* SYSTIMH latching upon SYSTIML read does not work well.
4399 * This means that if SYSTIML overflows after we read it but before
4400 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4401 * will experience a huge non linear increment in the systime value
4402 * to fix that we test for overflow and if true, we re-read systime.
4403 */
4406 /* Is systimel is so large that overflow is possible? */
4410 /* There was an overflow, read again SYSTIMH, and use
4411 * systimel_2
4412 */
4415 }
4416 }
4424 }
4426 /**
4427 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4428 * @adapter: board private structure to initialize
4429 *
4430 * e1000_sw_init initializes the Adapter private data structure.
4431 * Fields are initialized based on PCI device information and
4432 * OS network device settings (MTU size).
4433 **/
4435 {
4452 /* Setup hardware time stamping cyclecounter */
4457 /* cc.shift set in e1000e_get_base_tininca() */
4461 }
4463 /* Explicitly disable IRQ since the NIC can be in any state. */
4468 }
4470 /**
4471 * e1000_intr_msi_test - Interrupt Handler
4472 * @irq: interrupt number
4473 * @data: pointer to a network interface device structure
4474 **/
4476 {
4485 /* Force memory writes to complete before acknowledging the
4486 * interrupt is handled.
4487 */
4489 }
4492 }
4494 /**
4495 * e1000_test_msi_interrupt - Returns 0 for successful test
4496 * @adapter: board private struct
4497 *
4498 * code flow taken from tg3.c
4499 **/
4501 {
4506 /* poll_enable hasn't been called yet, so don't need disable */
4507 /* clear any pending events */
4510 /* free the real vector and request a test handler */
4514 /* Assume that the test fails, if it succeeds then the test
4515 * MSI irq handler will unset this flag
4516 */
4528 }
4530 /* Force memory writes to complete before enabling and firing an
4531 * interrupt.
4532 */
4537 /* fire an unusual interrupt on the test handler */
4551 }
4556 msi_test_failed:
4559 }
4561 /**
4562 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4563 * @adapter: board private struct
4564 *
4565 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4566 **/
4568 {
4570 u16 pci_cmd;
4575 /* disable SERR in case the MSI write causes a master abort */
4583 /* re-enable SERR */
4588 }
4591 }
4593 /**
4594 * e1000e_open - Called when a network interface is made active
4595 * @netdev: network interface device structure
4596 *
4597 * Returns 0 on success, negative value on failure
4598 *
4599 * The open entry point is called when a network interface is made
4600 * active by the system (IFF_UP). At this point all resources needed
4601 * for transmit and receive operations are allocated, the interrupt
4602 * handler is registered with the OS, the watchdog timer is started,
4603 * and the stack is notified that the interface is ready.
4604 **/
4606 {
4612 /* disallow open during test */
4620 /* allocate transmit descriptors */
4625 /* allocate receive descriptors */
4630 /* If AMT is enabled, let the firmware know that the network
4631 * interface is now open and reset the part to a known state.
4632 */
4636 }
4644 /* DMA latency requirement to workaround jumbo issue */
4646 PM_QOS_DEFAULT_VALUE);
4648 /* before we allocate an interrupt, we must be ready to handle it.
4649 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4650 * as soon as we call pci_request_irq, so we have to setup our
4651 * clean_rx handler before we do so.
4652 */
4659 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4660 * ignore e1000e MSI messages, which means we need to test our MSI
4661 * interrupt now
4662 */
4668 }
4669 }
4671 /* From here on the code is the same as e1000e_up() */
4688 err_req_irq:
4693 err_setup_rx:
4695 err_setup_tx:
4700 }
4702 /**
4703 * e1000e_close - Disables a network interface
4704 * @netdev: network interface device structure
4705 *
4706 * Returns 0, this is not allowed to fail
4707 *
4708 * The close entry point is called when an interface is de-activated
4709 * by the OS. The hardware is still under the drivers control, but
4710 * needs to be disabled. A global MAC reset is issued to stop the
4711 * hardware, and all transmit and receive resources are freed.
4712 **/
4714 {
4730 /* Link status message must follow this format */
4732 }
4739 /* kill manageability vlan ID if supported, but not if a vlan with
4740 * the same ID is registered on the host OS (let 8021q kill it)
4741 */
4746 /* If AMT is enabled, let the firmware know that the network
4747 * interface is now closed
4748 */
4758 }
4760 /**
4761 * e1000_set_mac - Change the Ethernet Address of the NIC
4762 * @netdev: network interface device structure
4763 * @p: pointer to an address structure
4764 *
4765 * Returns 0 on success, negative on failure
4766 **/
4768 {
4782 /* activate the work around */
4785 /* Hold a copy of the LAA in RAR[14] This is done so that
4786 * between the time RAR[0] gets clobbered and the time it
4787 * gets fixed (in e1000_watchdog), the actual LAA is in one
4788 * of the RARs and no incoming packets directed to this port
4789 * are dropped. Eventually the LAA will be in RAR[0] and
4790 * RAR[14]
4791 */
4794 }
4797 }
4799 /**
4800 * e1000e_update_phy_task - work thread to update phy
4801 * @work: pointer to our work struct
4802 *
4803 * this worker thread exists because we must acquire a
4804 * semaphore to read the phy, which we could msleep while
4805 * waiting for it, and we can't msleep in a timer.
4806 **/
4808 {
4811 update_phy_task);
4819 /* Enable EEE on 82579 after link up */
4822 }
4824 /**
4825 * e1000_update_phy_info - timre call-back to update PHY info
4826 * @data: pointer to adapter cast into an unsigned long
4827 *
4828 * Need to wait a few seconds after link up to get diagnostic information from
4829 * the phy
4830 **/
4832 {
4839 }
4841 /**
4842 * e1000e_update_phy_stats - Update the PHY statistics counters
4843 * @adapter: board private structure
4844 *
4845 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4846 **/
4848 {
4850 s32 ret_val;
4851 u16 phy_data;
4857 /* A page set is expensive so check if already on desired page.
4858 * If not, set to the page with the PHY status registers.
4859 */
4870 }
4872 /* Single Collision Count */
4878 /* Excessive Collision Count */
4884 /* Multiple Collision Count */
4890 /* Late Collision Count */
4896 /* Collision Count - also used for adaptive IFS */
4902 /* Defer Count */
4908 /* Transmit with no CRS */
4914 release:
4916 }
4918 /**
4919 * e1000e_update_stats - Update the board statistics counters
4920 * @adapter: board private structure
4921 **/
4923 {
4928 /* Prevent stats update while adapter is being reset, or if the pci
4929 * connection is down.
4930 */
4946 /* Half-duplex statistics */
4962 }
4964 }
4979 /* used for adaptive IFS */
4990 /* Fill out the OS statistics structure */
4994 /* Rx Errors */
4996 /* RLEC on some newer hardware can be incorrect so build
4997 * our own version based on RUC and ROC
4998 */
5008 /* Tx Errors */
5014 /* Tx Dropped needs to be maintained elsewhere */
5016 /* Management Stats */
5021 /* Correctable ECC Errors */
5029 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5030 }
5031 }
5033 /**
5034 * e1000_phy_read_status - Update the PHY register status snapshot
5035 * @adapter: board private structure
5036 **/
5038 {
5058 /* Do not read PHY registers if link is not up
5059 * Set values to typical power-on defaults
5060 */
5064 BMSR_ERCAP);
5072 }
5073 }
5076 {
5080 /* Link status message must follow this format for user tools */
5087 }
5090 {
5095 /* get_link_status is set on LSC (link status) interrupt or
5096 * Rx sequence error interrupt. get_link_status will stay
5097 * true until the check_for_link establishes link
5098 * for copper adapters ONLY
5099 */
5107 }
5120 }
5124 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5126 }
5129 }
5132 {
5133 /* make sure the receive unit is started */
5141 }
5142 }
5145 {
5148 /* With 82574 controllers, PHY needs to be checked periodically
5149 * for hung state and reset, if two calls return true
5150 */
5153 else
5160 }
5161 }
5163 /**
5164 * e1000_watchdog - Timer Call-back
5165 * @data: pointer to adapter cast into an unsigned long
5166 **/
5168 {
5171 /* Do the rest outside of interrupt context */
5174 /* TODO: make this use queue_delayed_work() */
5175 }
5178 {
5181 watchdog_task);
5194 /* Cancel scheduled suspend requests. */
5199 }
5209 /* Cancel scheduled suspend requests. */
5212 /* update snapshot of PHY registers on LSC */
5219 /* check if SmartSpeed worked */
5225 /* On supported PHYs, check for duplex mismatch only
5226 * if link has autonegotiated at 10/100 half
5227 */
5234 u16 autoneg_exp;
5239 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5240 }
5242 /* adjust timeout factor according to speed/duplex */
5253 }
5255 /* workaround: re-program speed mode bit after
5256 * link-up event
5257 */
5260 u32 tarc0;
5265 }
5267 /* disable TSO for pcie and 10/100 speeds, to avoid
5268 * some hardware issues
5269 */
5283 /* oops */
5285 }
5286 }
5288 /* enable transmits in the hardware, need to do this
5289 * after setting TARC(0)
5290 */
5295 /* Perform any post-link-up configuration before
5296 * reporting link up.
5297 */
5306 }
5311 /* Link status message must follow this format */
5318 /* 8000ES2LAN requires a Rx packet buffer work-around
5319 * on link down event; reset the controller to flush
5320 * the Rx packet buffer.
5321 */
5324 else
5326 LINK_TIMEOUT);
5327 }
5328 }
5330 link_up:
5345 /* If the link is lost the controller stops DMA, but
5346 * if there is queued Tx work it cannot be done. So
5347 * reset the controller to flush the Tx packet buffers.
5348 */
5353 /* If reset is necessary, do it outside of interrupt context. */
5356 /* return immediately since reset is imminent */
5358 }
5362 /* Simple mode for Interrupt Throttle Rate (ITR) */
5364 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5365 * Total asymmetrical Tx or Rx gets ITR=8000;
5366 * everyone else is between 2000-8000.
5367 */
5375 }
5377 /* Cause software interrupt to ensure Rx ring is cleaned */
5380 else
5383 /* flush pending descriptors to memory before detecting Tx hang */
5386 /* Force detection of hung controller every watchdog period */
5389 /* With 82571 controllers, LAA may be overwritten due to controller
5390 * reset from the other port. Set the appropriate LAA in RAR[0]
5391 */
5398 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5406 }
5407 }
5409 /* Reset the timer */
5413 }
5415 #define E1000_TX_FLAGS_CSUM 0x00000001
5416 #define E1000_TX_FLAGS_VLAN 0x00000002
5417 #define E1000_TX_FLAGS_TSO 0x00000004
5418 #define E1000_TX_FLAGS_IPV4 0x00000008
5419 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5420 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5421 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5422 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5425 __be16 protocol)
5426 {
5458 }
5484 i++;
5490 }
5493 __be16 protocol)
5494 {
5499 u8 css;
5511 /* XXX not handling all IPV6 headers */
5520 }
5538 i++;
5544 }
5549 {
5575 count++;
5578 i++;
5581 }
5582 }
5592 i++;
5604 DMA_TO_DEVICE);
5611 count++;
5612 }
5613 }
5616 /* multiply data chunks by size of headers */
5626 dma_error:
5630 count--;
5635 i--;
5638 }
5641 }
5644 {
5653 E1000_TXD_CMD_TSE;
5658 }
5663 }
5668 }
5676 }
5688 i++;
5695 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5699 /* Force memory writes to complete before letting h/w
5700 * know there are new descriptors to fetch. (Only
5701 * applicable for weak-ordered memory model archs,
5702 * such as IA-64).
5703 */
5707 }
5709 #define MINIMUM_DHCP_PACKET_SIZE 282
5712 {
5719 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5728 {
5742 }
5745 }
5748 {
5752 /* Herbert's original patch had:
5753 * smp_mb__after_netif_stop_queue();
5754 * but since that doesn't exist yet, just open code it.
5755 */
5758 /* We need to check again in a case another CPU has just
5759 * made room available.
5760 */
5764 /* A reprieve! */
5768 }
5771 {
5777 }
5781 {
5797 }
5802 }
5804 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5805 * pad skb in order to meet this minimum size requirement
5806 */
5812 u8 hdr_len;
5814 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5815 * points to just header, pull a few bytes of payload from
5816 * frags into skb->data
5817 */
5819 /* we do this workaround for ES2LAN, but it is un-necessary,
5820 * avoiding it could save a lot of cycles
5821 */
5830 }
5832 }
5833 }
5835 /* reserve a descriptor for the offload context */
5837 count++;
5838 count++;
5850 /* need: count + 2 desc gap to keep tail from touching
5851 * head, otherwise try next time
5852 */
5859 E1000_TX_FLAGS_VLAN_SHIFT);
5860 }
5868 }
5875 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5876 * 82571 hardware supports TSO capabilities for IPv6 as well...
5877 * no longer assume, we must.
5878 */
5885 /* if count is 0 then mapping error has occurred */
5887 nr_frags);
5899 }
5900 }
5906 /* Make sure there is space in the ring for the next send. */
5917 else
5920 /* we need this if more than one processor can write
5921 * to our tail at a time, it synchronizes IO on
5922 *IA64/Altix systems
5923 */
5925 }
5930 }
5933 }
5935 /**
5936 * e1000_tx_timeout - Respond to a Tx Hang
5937 * @netdev: network interface device structure
5938 **/
5940 {
5943 /* Do the reset outside of interrupt context */
5946 }
5949 {
5953 /* don't run the task if already down */
5960 }
5962 }
5964 /**
5965 * e1000_get_stats64 - Get System Network Statistics
5966 * @netdev: network interface device structure
5967 * @stats: rtnl_link_stats64 pointer
5968 *
5969 * Returns the address of the device statistics structure.
5970 **/
5973 {
5978 /* Fill out the OS statistics structure */
5986 /* Rx Errors */
5988 /* RLEC on some newer hardware can be incorrect so build
5989 * our own version based on RUC and ROC
5990 */
5999 /* Tx Errors */
6005 /* Tx Dropped needs to be maintained elsewhere */
6008 }
6010 /**
6011 * e1000_change_mtu - Change the Maximum Transfer Unit
6012 * @netdev: network interface device structure
6013 * @new_mtu: new value for maximum frame size
6014 *
6015 * Returns 0 on success, negative on failure
6016 **/
6018 {
6022 /* Jumbo frame support */
6027 }
6029 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6035 }
6039 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6049 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6050 * means we reserve 2 more, this pushes us to allocate from the next
6051 * larger slab size.
6052 * i.e. RXBUFFER_2048 --> size-4096 slab
6053 * However with the new *_jumbo_rx* routines, jumbo receives will use
6054 * fragmented skbs
6055 */
6059 else
6062 /* adjust allocation if LPE protects us, and we aren't using SBP */
6068 else
6076 }
6080 {
6127 }
6132 }
6134 }
6136 /**
6137 * e1000e_hwtstamp_ioctl - control hardware time stamping
6138 * @netdev: network interface device structure
6139 * @ifreq: interface request
6140 *
6141 * Outgoing time stamping can be enabled and disabled. Play nice and
6142 * disable it when requested, although it shouldn't cause any overhead
6143 * when no packet needs it. At most one packet in the queue may be
6144 * marked for time stamping, otherwise it would be impossible to tell
6145 * for sure to which packet the hardware time stamp belongs.
6146 *
6147 * Incoming time stamping has to be configured via the hardware filters.
6148 * Not all combinations are supported, in particular event type has to be
6149 * specified. Matching the kind of event packet is not supported, with the
6150 * exception of "all V2 events regardless of level 2 or 4".
6151 **/
6153 {
6172 /* With V2 type filters which specify a Sync or Delay Request,
6173 * Path Delay Request/Response messages are also time stamped
6174 * by hardware so notify the caller the requested packets plus
6175 * some others are time stamped.
6176 */
6181 }
6185 }
6188 {
6193 }
6196 {
6208 }
6209 }
6212 {
6218 /* copy MAC RARs to PHY RARs */
6225 }
6227 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6232 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6239 }
6241 /* configure PHY Rx Control register */
6265 /* enable PHY wakeup in MAC register */
6270 /* configure and enable PHY wakeup in PHY registers */
6274 /* activate PHY wakeup */
6279 release:
6283 }
6286 {
6290 u32 ret_val;
6303 fl_out:
6305 }
6308 {
6322 /* Quiesce the device without resetting the hardware */
6325 }
6328 /* Allow time for pending master requests to run */
6332 }
6335 {
6340 /* Runtime suspend should only enable wakeup for link changes */
6352 /* turn on all-multi mode if wake on multicast is enabled */
6357 }
6367 e1000_media_type_internal_serdes) {
6368 /* keep the laser running in D3 */
6372 }
6381 /* enable wakeup by the PHY */
6386 /* enable wakeup by the MAC */
6389 }
6395 }
6401 /* ULP does not support wake from unicast, multicast
6402 * or broadcast.
6403 */
6408 }
6410 /* Ensure that the appropriate bits are set in LPI_CTRL
6411 * for EEE in Sx
6412 */
6424 I82579_EEE_100_SUPPORTED)
6428 I82579_EEE_1000_SUPPORTED)
6432 lpi_ctrl);
6433 }
6434 }
6436 }
6438 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6439 * would have already happened in close and is redundant.
6440 */
6445 /* The pci-e switch on some quad port adapters will report a
6446 * correctable error when the MAC transitions from D0 to D3. To
6447 * prevent this we need to mask off the correctable errors on the
6448 * downstream port of the pci-e switch.
6449 *
6450 * We don't have the associated upstream bridge while assigning
6451 * the PCI device into guest. For example, the KVM on power is
6452 * one of the cases.
6453 */
6456 u16 devctl;
6469 }
6472 }
6474 /**
6475 * __e1000e_disable_aspm - Disable ASPM states
6476 * @pdev: pointer to PCI device struct
6477 * @state: bit-mask of ASPM states to disable
6478 * @locked: indication if this context holds pci_bus_sem locked.
6479 *
6480 * Some devices *must* have certain ASPM states disabled per hardware errata.
6481 **/
6483 {
6492 /* fall-through - can't have L1 without L0s */
6498 }
6507 }
6509 /* Nothing to do if the ASPM states to be disabled already are */
6520 #ifdef CONFIG_PCIEASPM
6523 else
6526 /* Double-check ASPM control. If not disabled by the above, the
6527 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6528 * not enabled); override by writing PCI config space directly.
6529 */
6535 #endif
6537 /* Both device and parent should have the same ASPM setting.
6538 * Disable ASPM in downstream component first and then upstream.
6539 */
6544 aspm_dis_mask);
6545 }
6547 /**
6548 * e1000e_disable_aspm - Disable ASPM states.
6549 * @pdev: pointer to PCI device struct
6550 * @state: bit-mask of ASPM states to disable
6551 *
6552 * This function acquires the pci_bus_sem!
6553 * Some devices *must* have certain ASPM states disabled per hardware errata.
6554 **/
6556 {
6558 }
6560 /**
6561 * e1000e_disable_aspm_locked Disable ASPM states.
6562 * @pdev: pointer to PCI device struct
6563 * @state: bit-mask of ASPM states to disable
6564 *
6565 * This function must be called with pci_bus_sem acquired!
6566 * Some devices *must* have certain ASPM states disabled per hardware errata.
6567 **/
6569 {
6571 }
6573 #ifdef CONFIG_PM
6575 {
6595 /* report the system wakeup cause from S3/S4 */
6597 u16 phy_data;
6608 }
6621 }
6623 }
6629 /* If the controller has AMT, do not set DRV_LOAD until the interface
6630 * is up. For all other cases, let the f/w know that the h/w is now
6631 * under the control of the driver.
6632 */
6637 }
6639 #ifdef CONFIG_PM_SLEEP
6641 {
6653 }
6658 }
6661 {
6674 }
6677 {
6686 }
6690 {
6694 u16 eee_lp;
6701 }
6704 }
6707 {
6721 }
6724 {
6737 /* Down the device without resetting the hardware */
6739 }
6744 }
6747 }
6751 {
6757 }
6759 #ifdef CONFIG_NET_POLL_CONTROLLER
6762 {
6775 vector++;
6781 vector++;
6786 }
6789 }
6791 /**
6792 * e1000_netpoll
6793 * @netdev: network interface device structure
6794 *
6795 * Polling 'interrupt' - used by things like netconsole to send skbs
6796 * without having to re-enable interrupts. It's not called while
6797 * the interrupt routine is executing.
6798 */
6800 {
6817 }
6818 }
6819 #endif
6821 /**
6822 * e1000_io_error_detected - called when PCI error is detected
6823 * @pdev: Pointer to PCI device
6824 * @state: The current pci connection state
6825 *
6826 * This function is called after a PCI bus error affecting
6827 * this device has been detected.
6828 */
6830 pci_channel_state_t state)
6831 {
6844 /* Request a slot slot reset. */
6846 }
6848 /**
6849 * e1000_io_slot_reset - called after the pci bus has been reset.
6850 * @pdev: Pointer to PCI device
6851 *
6852 * Restart the card from scratch, as if from a cold-boot. Implementation
6853 * resembles the first-half of the e1000e_pm_resume routine.
6854 */
6856 {
6862 pci_ers_result_t result;
6887 }
6892 }
6894 /**
6895 * e1000_io_resume - called when traffic can start flowing again.
6896 * @pdev: Pointer to PCI device
6897 *
6898 * This callback is called when the error recovery driver tells us that
6899 * its OK to resume normal operation. Implementation resembles the
6900 * second-half of the e1000e_pm_resume routine.
6901 */
6903 {
6914 /* If the controller has AMT, do not set DRV_LOAD until the interface
6915 * is up. For all other cases, let the f/w know that the h/w is now
6916 * under the control of the driver.
6917 */
6920 }
6923 {
6926 u32 ret_val;
6929 /* print bus type/speed/width info */
6931 /* bus width */
6934 /* MAC address */
6939 E1000_PBANUM_LENGTH);
6944 }
6947 {
6958 /* Deep Smart Power Down (DSPD) */
6961 }
6962 }
6965 netdev_features_t features)
6966 {
6970 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6974 /* Since there is no support for separate Rx/Tx vlan accel
6975 * enable/disable make sure Tx flag is always in same state as Rx.
6976 */
6979 else
6983 }
6986 netdev_features_t features)
6987 {
6996 NETIF_F_RXALL)))
7003 /* We need to take it back to defaults, which might mean
7004 * stripping is still disabled at the adapter level.
7005 */
7008 else
7010 }
7011 }
7017 else
7021 }
7037 #ifdef CONFIG_NET_POLL_CONTROLLER
7039 #endif
7043 };
7045 /**
7046 * e1000_probe - Device Initialization Routine
7047 * @pdev: PCI device information struct
7048 * @ent: entry in e1000_pci_tbl
7049 *
7050 * Returns 0 on success, negative on failure
7051 *
7052 * e1000_probe initializes an adapter identified by a pci_dev structure.
7053 * The OS initialization, configuring of the adapter private structure,
7054 * and a hardware reset occur.
7055 **/
7057 {
7092 }
7093 }
7097 e1000e_driver_name);
7101 /* AER (Advanced Error Reporting) hooks */
7105 /* PCI config space info */
7149 }
7151 /* Set default EEE advertisement */
7155 /* construct the net_device struct */
7169 /* setup adapter struct */
7191 /* Copper options */
7196 }
7202 /* Set initial default active device features */
7204 NETIF_F_HW_VLAN_CTAG_RX |
7205 NETIF_F_HW_VLAN_CTAG_TX |
7206 NETIF_F_TSO |
7207 NETIF_F_TSO6 |
7208 NETIF_F_RXHASH |
7209 NETIF_F_RXCSUM |
7210 NETIF_F_HW_CSUM);
7212 /* Set user-changeable features (subset of all device features) */
7222 NETIF_F_TSO |
7223 NETIF_F_TSO6 |
7224 NETIF_F_HW_CSUM);
7231 }
7233 /* MTU range: 68 - max_hw_frame_size */
7241 /* before reading the NVM, reset the controller to
7242 * put the device in a known good starting state
7243 */
7246 /* systems with ASPM and others may see the checksum fail on the first
7247 * attempt. Let's give it a few tries
7248 */
7256 }
7257 }
7261 /* copy the MAC address */
7273 }
7284 /* Initialize link parameters. User can change them with ethtool */
7291 /* Initial Wake on LAN setting - If APM wake is enabled in
7292 * the EEPROM, enable the ACPI Magic Packet filter
7293 */
7295 /* APME bit in EEPROM is mapped to WUC.APME */
7305 NVM_INIT_CONTROL3_PORT_B,
7307 else
7309 NVM_INIT_CONTROL3_PORT_A,
7311 }
7313 /* fetch WoL from EEPROM */
7319 /* now that we have the eeprom settings, apply the special cases
7320 * where the eeprom may be wrong or the board simply won't support
7321 * wake on lan on a particular port
7322 */
7326 /* initialize the wol settings based on the eeprom settings */
7329 /* make sure adapter isn't asleep if manageability is enabled */
7334 /* save off EEPROM version number */
7340 }
7342 /* init PTP hardware clock */
7345 /* reset the hardware with the new settings */
7348 /* If the controller has AMT, do not set DRV_LOAD until the interface
7349 * is up. For all other cases, let the f/w know that the h/w is now
7350 * under the control of the driver.
7351 */
7360 /* carrier off reporting is important to ethtool even BEFORE open */
7370 err_register:
7373 err_eeprom:
7376 err_hw_init:
7379 err_sw_init:
7383 err_flashmap:
7385 err_ioremap:
7387 err_alloc_etherdev:
7389 err_pci_reg:
7390 err_dma:
7393 }
7395 /**
7396 * e1000_remove - Device Removal Routine
7397 * @pdev: PCI device information struct
7398 *
7399 * e1000_remove is called by the PCI subsystem to alert the driver
7400 * that it should release a PCI device. The could be caused by a
7401 * Hot-Plug event, or because the driver is going to be removed from
7402 * memory.
7403 **/
7405 {
7412 /* The timers may be rescheduled, so explicitly disable them
7413 * from being rescheduled.
7414 */
7431 }
7432 }
7434 /* Don't lie to e1000_close() down the road. */
7442 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7443 * would have already happened in close and is redundant.
7444 */
7459 /* AER disable */
7463 }
7465 /* PCI Error Recovery (ERS) */
7470 };
7477 board_82571 },
7498 board_80003es2lan },
7500 board_80003es2lan },
7502 board_80003es2lan },
7504 board_80003es2lan },
7568 };
7572 #ifdef CONFIG_PM_SLEEP
7579 #endif
7581 e1000e_pm_runtime_idle)
7582 };
7584 /* PCI Device API Driver */
7592 },
7595 };
7597 /**
7598 * e1000_init_module - Driver Registration Routine
7599 *
7600 * e1000_init_module is the first routine called when the driver is
7601 * loaded. All it does is register with the PCI subsystem.
7602 **/
7604 {
7606 e1000e_driver_version);
7610 }
7613 /**
7614 * e1000_exit_module - Driver Exit Cleanup Routine
7615 *
7616 * e1000_exit_module is called just before the driver is removed
7617 * from memory.
7618 **/
7620 {
7622 }
7630 /* netdev.c */