drivers/net/ethernet/intel/igb/e1000_defines.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 #ifndef _E1000_DEFINES_H_
  25 #define _E1000_DEFINES_H_
  26
  27 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  28 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  29 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  30
  31 /* Definitions for power management and wakeup registers */
  32 /* Wake Up Control */
  33 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  34
  35 /* Wake Up Filter Control */
  36 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  37 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  38 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  39 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  40 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  41
  42 /* Wake Up Status */
  43 #define E1000_WUS_EX    0x00000004 /* Directed Exact */
  44 #define E1000_WUS_ARPD  0x00000020 /* Directed ARP Request */
  45 #define E1000_WUS_IPV4  0x00000040 /* Directed IPv4 */
  46 #define E1000_WUS_IPV6  0x00000080 /* Directed IPv6 */
  47 #define E1000_WUS_NSD   0x00000400 /* Directed IPv6 Neighbor Solicitation */
  48
  49 /* Packet types that are enabled for wake packet delivery */
  50 #define WAKE_PKT_WUS ( \
  51         E1000_WUS_EX   | \
  52         E1000_WUS_ARPD | \
  53         E1000_WUS_IPV4 | \
  54         E1000_WUS_IPV6 | \
  55         E1000_WUS_NSD)
  56
  57 /* Wake Up Packet Length */
  58 #define E1000_WUPL_MASK 0x00000FFF
  59
  60 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
  61 #define E1000_WUPM_BYTES        128
  62
  63 /* Extended Device Control */
  64 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
  65 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
  66 #define E1000_CTRL_EXT_SDP2_DIR  0x00000400 /* SDP2 Data direction */
  67 #define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* SDP3 Data direction */
  68
  69 /* Physical Func Reset Done Indication */
  70 #define E1000_CTRL_EXT_PFRSTD   0x00004000
  71 #define E1000_CTRL_EXT_SDLPE    0X00040000  /* SerDes Low Power Enable */
  72 #define E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000
  73 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES    0x00C00000
  74 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX    0x00400000
  75 #define E1000_CTRL_EXT_LINK_MODE_SGMII  0x00800000
  76 #define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
  77 #define E1000_CTRL_EXT_EIAME    0x01000000
  78 #define E1000_CTRL_EXT_IRCA             0x00000001
  79 /* Interrupt delay cancellation */
  80 /* Driver loaded bit for FW */
  81 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000
  82 /* Interrupt acknowledge Auto-mask */
  83 /* Clear Interrupt timers after IMS clear */
  84 /* packet buffer parity error detection enabled */
  85 /* descriptor FIFO parity error detection enable */
  86 #define E1000_CTRL_EXT_PBA_CLR          0x80000000 /* PBA Clear */
  87 #define E1000_CTRL_EXT_PHYPDEN          0x00100000
  88 #define E1000_I2CCMD_REG_ADDR_SHIFT     16
  89 #define E1000_I2CCMD_PHY_ADDR_SHIFT     24
  90 #define E1000_I2CCMD_OPCODE_READ        0x08000000
  91 #define E1000_I2CCMD_OPCODE_WRITE       0x00000000
  92 #define E1000_I2CCMD_READY              0x20000000
  93 #define E1000_I2CCMD_ERROR              0x80000000
  94 #define E1000_I2CCMD_SFP_DATA_ADDR(a)   (0x0000 + (a))
  95 #define E1000_I2CCMD_SFP_DIAG_ADDR(a)   (0x0100 + (a))
  96 #define E1000_MAX_SGMII_PHY_REG_ADDR    255
  97 #define E1000_I2CCMD_PHY_TIMEOUT        200
  98 #define E1000_IVAR_VALID                0x80
  99 #define E1000_GPIE_NSICR                0x00000001
 100 #define E1000_GPIE_MSIX_MODE            0x00000010
 101 #define E1000_GPIE_EIAME                0x40000000
 102 #define E1000_GPIE_PBA                  0x80000000
 103
 104 /* Receive Descriptor bit definitions */
 105 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 106 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 107 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 108 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 109 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 110 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 111 #define E1000_RXD_STAT_TS       0x10000 /* Pkt was time stamped */
 112
 113 #define E1000_RXDEXT_STATERR_LB    0x00040000
 114 #define E1000_RXDEXT_STATERR_CE    0x01000000
 115 #define E1000_RXDEXT_STATERR_SE    0x02000000
 116 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
 117 #define E1000_RXDEXT_STATERR_CXE   0x10000000
 118 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
 119 #define E1000_RXDEXT_STATERR_IPE   0x40000000
 120 #define E1000_RXDEXT_STATERR_RXE   0x80000000
 121
 122 /* Same mask, but for extended and packet split descriptors */
 123 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 124         E1000_RXDEXT_STATERR_CE  |            \
 125         E1000_RXDEXT_STATERR_SE  |            \
 126         E1000_RXDEXT_STATERR_SEQ |            \
 127         E1000_RXDEXT_STATERR_CXE |            \
 128         E1000_RXDEXT_STATERR_RXE)
 129
 130 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 131 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 132 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 133 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 134 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 135
 136
 137 /* Management Control */
 138 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 139 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 140 #define E1000_MANC_EN_BMC2OS     0x10000000 /* OSBMC is Enabled or not */
 141 /* Enable Neighbor Discovery Filtering */
 142 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 143 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 144 /* Enable MAC address filtering */
 145 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 146
 147 /* Receive Control */
 148 #define E1000_RCTL_EN             0x00000002    /* enable */
 149 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 150 #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
 151 #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
 152 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 153 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 154 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 155 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
 156 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 157 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 158 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
 159 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 160 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 161 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 162 #define E1000_RCTL_DPF            0x00400000    /* Discard Pause Frames */
 163 #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
 164 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 165
 166 /* Use byte values for the following shift parameters
 167  * Usage:
 168  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 169  *                  E1000_PSRCTL_BSIZE0_MASK) |
 170  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 171  *                  E1000_PSRCTL_BSIZE1_MASK) |
 172  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 173  *                  E1000_PSRCTL_BSIZE2_MASK) |
 174  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 175  *                  E1000_PSRCTL_BSIZE3_MASK))
 176  * where value0 = [128..16256],  default=256
 177  *       value1 = [1024..64512], default=4096
 178  *       value2 = [0..64512],    default=4096
 179  *       value3 = [0..64512],    default=0
 180  */
 181
 182 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 183 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 184 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 185 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 186
 187 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 188 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 189 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 190 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 191
 192 /* SWFW_SYNC Definitions */
 193 #define E1000_SWFW_EEP_SM   0x1
 194 #define E1000_SWFW_PHY0_SM  0x2
 195 #define E1000_SWFW_PHY1_SM  0x4
 196 #define E1000_SWFW_PHY2_SM  0x20
 197 #define E1000_SWFW_PHY3_SM  0x40
 198
 199 /* FACTPS Definitions */
 200 /* Device Control */
 201 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 202 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
 203 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 204 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 205 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 206 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 207 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 208 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 209 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 210 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 211 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 212 /* Defined polarity of Dock/Undock indication in SDP[0] */
 213 /* Reset both PHY ports, through PHYRST_N pin */
 214 /* enable link status from external LINK_0 and LINK_1 pins */
 215 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 216 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 217 #define E1000_CTRL_SDP0_DIR 0x00400000  /* SDP0 Data direction */
 218 #define E1000_CTRL_SDP1_DIR 0x00800000  /* SDP1 Data direction */
 219 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 220 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 221 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 222 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 223 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 224 /* Initiate an interrupt to manageability engine */
 225 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
 226
 227 /* Bit definitions for the Management Data IO (MDIO) and Management Data
 228  * Clock (MDC) pins in the Device Control Register.
 229  */
 230
 231 #define E1000_CONNSW_ENRGSRC             0x4
 232 #define E1000_CONNSW_PHYSD              0x400
 233 #define E1000_CONNSW_PHY_PDN            0x800
 234 #define E1000_CONNSW_SERDESD            0x200
 235 #define E1000_CONNSW_AUTOSENSE_CONF     0x2
 236 #define E1000_CONNSW_AUTOSENSE_EN       0x1
 237 #define E1000_PCS_CFG_PCS_EN             8
 238 #define E1000_PCS_LCTL_FLV_LINK_UP       1
 239 #define E1000_PCS_LCTL_FSV_100           2
 240 #define E1000_PCS_LCTL_FSV_1000          4
 241 #define E1000_PCS_LCTL_FDV_FULL          8
 242 #define E1000_PCS_LCTL_FSD               0x10
 243 #define E1000_PCS_LCTL_FORCE_LINK        0x20
 244 #define E1000_PCS_LCTL_FORCE_FCTRL       0x80
 245 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
 246 #define E1000_PCS_LCTL_AN_RESTART        0x20000
 247 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
 248 #define E1000_ENABLE_SERDES_LOOPBACK     0x0410
 249
 250 #define E1000_PCS_LSTS_LINK_OK           1
 251 #define E1000_PCS_LSTS_SPEED_100         2
 252 #define E1000_PCS_LSTS_SPEED_1000        4
 253 #define E1000_PCS_LSTS_DUPLEX_FULL       8
 254 #define E1000_PCS_LSTS_SYNK_OK           0x10
 255
 256 /* Device Status */
 257 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 258 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 259 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 260 #define E1000_STATUS_FUNC_SHIFT 2
 261 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 262 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 263 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 264 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 265 /* Change in Dock/Undock state. Clear on write '0'. */
 266 /* Status of Master requests. */
 267 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
 268 /* BMC external code execution disabled */
 269
 270 #define E1000_STATUS_2P5_SKU            0x00001000 /* Val of 2.5GBE SKU strap */
 271 #define E1000_STATUS_2P5_SKU_OVER       0x00002000 /* Val of 2.5GBE SKU Over */
 272 /* Constants used to intrepret the masked PCI-X bus speed. */
 273
 274 #define SPEED_10    10
 275 #define SPEED_100   100
 276 #define SPEED_1000  1000
 277 #define SPEED_2500  2500
 278 #define HALF_DUPLEX 1
 279 #define FULL_DUPLEX 2
 280
 281
 282 #define ADVERTISE_10_HALF                 0x0001
 283 #define ADVERTISE_10_FULL                 0x0002
 284 #define ADVERTISE_100_HALF                0x0004
 285 #define ADVERTISE_100_FULL                0x0008
 286 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 287 #define ADVERTISE_1000_FULL               0x0020
 288
 289 /* 1000/H is not supported, nor spec-compliant. */
 290 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 291                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
 292                                                       ADVERTISE_1000_FULL)
 293 #define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 294                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 295 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 296 #define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)
 297 #define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
 298                                                       ADVERTISE_1000_FULL)
 299 #define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)
 300
 301 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 302
 303 /* LED Control */
 304 #define E1000_LEDCTL_LED0_MODE_SHIFT    0
 305 #define E1000_LEDCTL_LED0_BLINK         0x00000080
 306 #define E1000_LEDCTL_LED0_MODE_MASK     0x0000000F
 307 #define E1000_LEDCTL_LED0_IVRT          0x00000040
 308
 309 #define E1000_LEDCTL_MODE_LED_ON        0xE
 310 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 311
 312 /* Transmit Descriptor bit definitions */
 313 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 314 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 315 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 316 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 317 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 318 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 319 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 320 /* Extended desc bits for Linksec and timesync */
 321
 322 /* Transmit Control */
 323 #define E1000_TCTL_EN     0x00000002    /* enable tx */
 324 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 325 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 326 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 327 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 328
 329 /* DMA Coalescing register fields */
 330 #define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coal Watchdog Timer */
 331 #define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coal Rx Threshold */
 332 #define E1000_DMACR_DMACTHR_SHIFT       16
 333 #define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe trans */
 334 #define E1000_DMACR_DMAC_LX_SHIFT       28
 335 #define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
 336 /* DMA Coalescing BMC-to-OS Watchdog Enable */
 337 #define E1000_DMACR_DC_BMC2OSW_EN       0x00008000
 338
 339 #define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coal Tx Threshold */
 340
 341 #define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
 342
 343 #define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate Thresh */
 344 #define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx pkt rate curr window */
 345
 346 #define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Current Cnt */
 347
 348 #define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* FC Rx Thresh High val */
 349 #define E1000_FCRTC_RTH_COAL_SHIFT      4
 350 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision */
 351
 352 /* Timestamp in Rx buffer */
 353 #define E1000_RXPBS_CFG_TS_EN           0x80000000
 354
 355 #define I210_RXPBSIZE_DEFAULT           0x000000A2 /* RXPBSIZE default */
 356 #define I210_RXPBSIZE_MASK              0x0000003F
 357 #define I210_RXPBSIZE_PB_32KB           0x00000020
 358 #define I210_TXPBSIZE_DEFAULT           0x04000014 /* TXPBSIZE default */
 359 #define I210_TXPBSIZE_MASK              0xC0FFFFFF
 360 #define I210_TXPBSIZE_PB0_8KB           (8 << 0)
 361 #define I210_TXPBSIZE_PB1_8KB           (8 << 6)
 362 #define I210_TXPBSIZE_PB2_4KB           (4 << 12)
 363 #define I210_TXPBSIZE_PB3_4KB           (4 << 18)
 364
 365 #define I210_DTXMXPKTSZ_DEFAULT         0x00000098
 366
 367 #define I210_SR_QUEUES_NUM              2
 368
 369 /* SerDes Control */
 370 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 371
 372 /* Receive Checksum Control */
 373 #define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
 374 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 375 #define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
 376 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 377
 378 /* Header split receive */
 379 #define E1000_RFCTL_IPV6_EX_DIS         0x00010000
 380 #define E1000_RFCTL_LEF                 0x00040000
 381
 382 /* Collision related configuration parameters */
 383 #define E1000_COLLISION_THRESHOLD       15
 384 #define E1000_CT_SHIFT                  4
 385 #define E1000_COLLISION_DISTANCE        63
 386 #define E1000_COLD_SHIFT                12
 387
 388 /* Ethertype field values */
 389 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 390
 391 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
 392 #define MAX_JUMBO_FRAME_SIZE            0x2600
 393 #define MAX_STD_JUMBO_FRAME_SIZE        9216
 394
 395 /* PBA constants */
 396 #define E1000_PBA_34K 0x0022
 397 #define E1000_PBA_64K 0x0040    /* 64KB */
 398
 399 /* SW Semaphore Register */
 400 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 401 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 402
 403 /* Interrupt Cause Read */
 404 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 405 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 406 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
 407 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
 408 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
 409 #define E1000_ICR_VMMB          0x00000100 /* VM MB event */
 410 #define E1000_ICR_TS            0x00080000 /* Time Sync Interrupt */
 411 #define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */
 412 /* If this bit asserted, the driver should claim the interrupt */
 413 #define E1000_ICR_INT_ASSERTED  0x80000000
 414 /* LAN connected device generates an interrupt */
 415 #define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
 416
 417 /* Extended Interrupt Cause Read */
 418 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
 419 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
 420 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
 421 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
 422 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
 423 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
 424 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
 425 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
 426 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 427 /* TCP Timer */
 428
 429 /* This defines the bits that are set in the Interrupt Mask
 430  * Set/Read Register.  Each bit is documented below:
 431  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 432  *   o TXDW   = Transmit Descriptor Written Back
 433  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 434  *   o RXSEQ  = Receive Sequence Error
 435  *   o LSC    = Link Status Change
 436  */
 437 #define IMS_ENABLE_MASK ( \
 438         E1000_IMS_RXT0   |    \
 439         E1000_IMS_TXDW   |    \
 440         E1000_IMS_RXDMT0 |    \
 441         E1000_IMS_RXSEQ  |    \
 442         E1000_IMS_LSC    |    \
 443         E1000_IMS_DOUTSYNC)
 444
 445 /* Interrupt Mask Set */
 446 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 447 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 448 #define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
 449 #define E1000_IMS_TS        E1000_ICR_TS        /* Time Sync Interrupt */
 450 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 451 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 452 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 453 #define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */
 454 #define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 455
 456 /* Extended Interrupt Mask Set */
 457 #define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 458
 459 /* Interrupt Cause Set */
 460 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 461 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 462 #define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */
 463
 464 /* Extended Interrupt Cause Set */
 465 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
 466 #define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
 467
 468
 469 /* Transmit Descriptor Control */
 470 /* Enable the counting of descriptors still to be processed. */
 471
 472 /* Flow Control Constants */
 473 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 474 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 475 #define FLOW_CONTROL_TYPE         0x8808
 476
 477 /* Transmit Config Word */
 478 #define E1000_TXCW_ASM_DIR      0x00000100 /* TXCW astm pause direction */
 479 #define E1000_TXCW_PAUSE        0x00000080 /* TXCW sym pause request */
 480
 481 /* 802.1q VLAN Packet Size */
 482 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 483 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 484
 485 /* Receive Address */
 486 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
 487  * Registers) holds the directed and multicast addresses that we monitor.
 488  * Technically, we have 16 spots.  However, we reserve one of these spots
 489  * (RAR[15]) for our directed address used by controllers with
 490  * manageability enabled, allowing us room for 15 multicast addresses.
 491  */
 492 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 493 #define E1000_RAL_MAC_ADDR_LEN 4
 494 #define E1000_RAH_MAC_ADDR_LEN 2
 495 #define E1000_RAH_POOL_MASK 0x03FC0000
 496 #define E1000_RAH_POOL_1 0x00040000
 497
 498 /* Error Codes */
 499 #define E1000_ERR_NVM      1
 500 #define E1000_ERR_PHY      2
 501 #define E1000_ERR_CONFIG   3
 502 #define E1000_ERR_PARAM    4
 503 #define E1000_ERR_MAC_INIT 5
 504 #define E1000_ERR_RESET   9
 505 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 506 #define E1000_BLK_PHY_RESET   12
 507 #define E1000_ERR_SWFW_SYNC 13
 508 #define E1000_NOT_IMPLEMENTED 14
 509 #define E1000_ERR_MBX      15
 510 #define E1000_ERR_INVALID_ARGUMENT  16
 511 #define E1000_ERR_NO_SPACE          17
 512 #define E1000_ERR_NVM_PBA_SECTION   18
 513 #define E1000_ERR_INVM_VALUE_NOT_FOUND  19
 514 #define E1000_ERR_I2C               20
 515
 516 /* Loop limit on how long we wait for auto-negotiation to complete */
 517 #define COPPER_LINK_UP_LIMIT              10
 518 #define PHY_AUTO_NEG_LIMIT                45
 519 #define PHY_FORCE_LIMIT                   20
 520 /* Number of 100 microseconds we wait for PCI Express master disable */
 521 #define MASTER_DISABLE_TIMEOUT      800
 522 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 523 #define PHY_CFG_TIMEOUT             100
 524 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 525 /* Number of milliseconds for NVM auto read done after MAC reset. */
 526 #define AUTO_READ_DONE_TIMEOUT      10
 527
 528 /* Flow Control */
 529 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 530
 531 #define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
 532 #define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
 533
 534 #define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */
 535 #define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */
 536 #define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
 537 #define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
 538 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
 539 #define E1000_TSYNCRXCTL_TYPE_ALL         0x08
 540 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
 541 #define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */
 542
 543 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
 544 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
 545 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
 546 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
 547 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
 548 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
 549
 550 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
 551 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
 552 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
 553 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
 554 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
 555 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
 556 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
 557 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
 558 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
 559 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
 560 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
 561
 562 #define E1000_TIMINCA_16NS_SHIFT 24
 563
 564 /* Time Sync Interrupt Cause/Mask Register Bits */
 565
 566 #define TSINTR_SYS_WRAP  BIT(0) /* SYSTIM Wrap around. */
 567 #define TSINTR_TXTS      BIT(1) /* Transmit Timestamp. */
 568 #define TSINTR_RXTS      BIT(2) /* Receive Timestamp. */
 569 #define TSINTR_TT0       BIT(3) /* Target Time 0 Trigger. */
 570 #define TSINTR_TT1       BIT(4) /* Target Time 1 Trigger. */
 571 #define TSINTR_AUTT0     BIT(5) /* Auxiliary Timestamp 0 Taken. */
 572 #define TSINTR_AUTT1     BIT(6) /* Auxiliary Timestamp 1 Taken. */
 573 #define TSINTR_TADJ      BIT(7) /* Time Adjust Done. */
 574
 575 #define TSYNC_INTERRUPTS TSINTR_TXTS
 576 #define E1000_TSICR_TXTS TSINTR_TXTS
 577
 578 /* TSAUXC Configuration Bits */
 579 #define TSAUXC_EN_TT0    BIT(0)  /* Enable target time 0. */
 580 #define TSAUXC_EN_TT1    BIT(1)  /* Enable target time 1. */
 581 #define TSAUXC_EN_CLK0   BIT(2)  /* Enable Configurable Frequency Clock 0. */
 582 #define TSAUXC_SAMP_AUT0 BIT(3)  /* Latch SYSTIML/H into AUXSTMPL/0. */
 583 #define TSAUXC_ST0       BIT(4)  /* Start Clock 0 Toggle on Target Time 0. */
 584 #define TSAUXC_EN_CLK1   BIT(5)  /* Enable Configurable Frequency Clock 1. */
 585 #define TSAUXC_SAMP_AUT1 BIT(6)  /* Latch SYSTIML/H into AUXSTMPL/1. */
 586 #define TSAUXC_ST1       BIT(7)  /* Start Clock 1 Toggle on Target Time 1. */
 587 #define TSAUXC_EN_TS0    BIT(8)  /* Enable hardware timestamp 0. */
 588 #define TSAUXC_AUTT0     BIT(9)  /* Auxiliary Timestamp Taken. */
 589 #define TSAUXC_EN_TS1    BIT(10) /* Enable hardware timestamp 0. */
 590 #define TSAUXC_AUTT1     BIT(11) /* Auxiliary Timestamp Taken. */
 591 #define TSAUXC_PLSG      BIT(17) /* Generate a pulse. */
 592 #define TSAUXC_DISABLE   BIT(31) /* Disable SYSTIM Count Operation. */
 593
 594 /* SDP Configuration Bits */
 595 #define AUX0_SEL_SDP0    (0u << 0)  /* Assign SDP0 to auxiliary time stamp 0. */
 596 #define AUX0_SEL_SDP1    (1u << 0)  /* Assign SDP1 to auxiliary time stamp 0. */
 597 #define AUX0_SEL_SDP2    (2u << 0)  /* Assign SDP2 to auxiliary time stamp 0. */
 598 #define AUX0_SEL_SDP3    (3u << 0)  /* Assign SDP3 to auxiliary time stamp 0. */
 599 #define AUX0_TS_SDP_EN   (1u << 2)  /* Enable auxiliary time stamp trigger 0. */
 600 #define AUX1_SEL_SDP0    (0u << 3)  /* Assign SDP0 to auxiliary time stamp 1. */
 601 #define AUX1_SEL_SDP1    (1u << 3)  /* Assign SDP1 to auxiliary time stamp 1. */
 602 #define AUX1_SEL_SDP2    (2u << 3)  /* Assign SDP2 to auxiliary time stamp 1. */
 603 #define AUX1_SEL_SDP3    (3u << 3)  /* Assign SDP3 to auxiliary time stamp 1. */
 604 #define AUX1_TS_SDP_EN   (1u << 5)  /* Enable auxiliary time stamp trigger 1. */
 605 #define TS_SDP0_SEL_TT0  (0u << 6)  /* Target time 0 is output on SDP0. */
 606 #define TS_SDP0_SEL_TT1  (1u << 6)  /* Target time 1 is output on SDP0. */
 607 #define TS_SDP0_SEL_FC0  (2u << 6)  /* Freq clock  0 is output on SDP0. */
 608 #define TS_SDP0_SEL_FC1  (3u << 6)  /* Freq clock  1 is output on SDP0. */
 609 #define TS_SDP0_EN       (1u << 8)  /* SDP0 is assigned to Tsync. */
 610 #define TS_SDP1_SEL_TT0  (0u << 9)  /* Target time 0 is output on SDP1. */
 611 #define TS_SDP1_SEL_TT1  (1u << 9)  /* Target time 1 is output on SDP1. */
 612 #define TS_SDP1_SEL_FC0  (2u << 9)  /* Freq clock  0 is output on SDP1. */
 613 #define TS_SDP1_SEL_FC1  (3u << 9)  /* Freq clock  1 is output on SDP1. */
 614 #define TS_SDP1_EN       (1u << 11) /* SDP1 is assigned to Tsync. */
 615 #define TS_SDP2_SEL_TT0  (0u << 12) /* Target time 0 is output on SDP2. */
 616 #define TS_SDP2_SEL_TT1  (1u << 12) /* Target time 1 is output on SDP2. */
 617 #define TS_SDP2_SEL_FC0  (2u << 12) /* Freq clock  0 is output on SDP2. */
 618 #define TS_SDP2_SEL_FC1  (3u << 12) /* Freq clock  1 is output on SDP2. */
 619 #define TS_SDP2_EN       (1u << 14) /* SDP2 is assigned to Tsync. */
 620 #define TS_SDP3_SEL_TT0  (0u << 15) /* Target time 0 is output on SDP3. */
 621 #define TS_SDP3_SEL_TT1  (1u << 15) /* Target time 1 is output on SDP3. */
 622 #define TS_SDP3_SEL_FC0  (2u << 15) /* Freq clock  0 is output on SDP3. */
 623 #define TS_SDP3_SEL_FC1  (3u << 15) /* Freq clock  1 is output on SDP3. */
 624 #define TS_SDP3_EN       (1u << 17) /* SDP3 is assigned to Tsync. */
 625
 626 #define E1000_MDICNFG_EXT_MDIO    0x80000000      /* MDI ext/int destination */
 627 #define E1000_MDICNFG_COM_MDIO    0x40000000      /* MDI shared w/ lan 0 */
 628 #define E1000_MDICNFG_PHY_MASK    0x03E00000
 629 #define E1000_MDICNFG_PHY_SHIFT   21
 630
 631 #define E1000_MEDIA_PORT_COPPER                 1
 632 #define E1000_MEDIA_PORT_OTHER                  2
 633 #define E1000_M88E1112_AUTO_COPPER_SGMII        0x2
 634 #define E1000_M88E1112_AUTO_COPPER_BASEX        0x3
 635 #define E1000_M88E1112_STATUS_LINK              0x0004 /* Interface Link Bit */
 636 #define E1000_M88E1112_MAC_CTRL_1               0x10
 637 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK     0x0380 /* Mode Select */
 638 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT    7
 639 #define E1000_M88E1112_PAGE_ADDR                0x16
 640 #define E1000_M88E1112_STATUS                   0x01
 641 #define E1000_M88E1512_CFG_REG_1                0x0010
 642 #define E1000_M88E1512_CFG_REG_2                0x0011
 643 #define E1000_M88E1512_CFG_REG_3                0x0007
 644 #define E1000_M88E1512_MODE                     0x0014
 645
 646 /* PCI Express Control */
 647 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
 648 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
 649 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
 650 #define E1000_GCR_CAP_VER2              0x00040000
 651
 652 /* mPHY Address Control and Data Registers */
 653 #define E1000_MPHY_ADDR_CTL          0x0024 /* mPHY Address Control Register */
 654 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
 655 #define E1000_MPHY_DATA                 0x0E10 /* mPHY Data Register */
 656
 657 /* mPHY PCS CLK Register */
 658 #define E1000_MPHY_PCS_CLK_REG_OFFSET  0x0004 /* mPHY PCS CLK AFE CSR Offset */
 659 /* mPHY Near End Digital Loopback Override Bit */
 660 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
 661
 662 #define E1000_PCS_LCTL_FORCE_FCTRL      0x80
 663 #define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 664
 665 /* PHY Control Register */
 666 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 667 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 668 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 669 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 670 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 671 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 672 #define MII_CR_SPEED_1000       0x0040
 673 #define MII_CR_SPEED_100        0x2000
 674 #define MII_CR_SPEED_10         0x0000
 675
 676 /* PHY Status Register */
 677 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
 678 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
 679
 680 /* Autoneg Advertisement Register */
 681 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
 682 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
 683 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
 684 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
 685 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
 686 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
 687
 688 /* Link Partner Ability Register (Base Page) */
 689 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
 690 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
 691
 692 /* Autoneg Expansion Register */
 693
 694 /* 1000BASE-T Control Register */
 695 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
 696 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
 697 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
 698                                         /* 0=Configure PHY as Slave */
 699 #define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
 700                                         /* 0=Automatic Master/Slave config */
 701
 702 /* 1000BASE-T Status Register */
 703 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 704 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
 705
 706
 707 /* PHY 1000 MII Register/Bit Definitions */
 708 /* PHY Registers defined by IEEE */
 709 #define PHY_CONTROL      0x00 /* Control Register */
 710 #define PHY_STATUS       0x01 /* Status Register */
 711 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
 712 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
 713 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
 714 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
 715 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
 716 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 717
 718 /* NVM Control */
 719 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 720 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 721 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
 722 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
 723 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
 724 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
 725 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
 726 /* NVM Addressing bits based on type 0=small, 1=large */
 727 #define E1000_EECD_ADDR_BITS 0x00000400
 728 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
 729 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
 730 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
 731 #define E1000_EECD_SIZE_EX_SHIFT     11
 732 #define E1000_EECD_FLUPD_I210           0x00800000 /* Update FLASH */
 733 #define E1000_EECD_FLUDONE_I210         0x04000000 /* Update FLASH done*/
 734 #define E1000_EECD_FLASH_DETECTED_I210  0x00080000 /* FLASH detected */
 735 #define E1000_FLUDONE_ATTEMPTS          20000
 736 #define E1000_EERD_EEWR_MAX_COUNT       512 /* buffered EEPROM words rw */
 737 #define E1000_I210_FIFO_SEL_RX          0x00
 738 #define E1000_I210_FIFO_SEL_TX_QAV(_i)  (0x02 + (_i))
 739 #define E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)
 740 #define E1000_I210_FIFO_SEL_BMC2OS_TX   0x06
 741 #define E1000_I210_FIFO_SEL_BMC2OS_RX   0x01
 742 #define E1000_I210_FLASH_SECTOR_SIZE    0x1000 /* 4KB FLASH sector unit size */
 743 /* Secure FLASH mode requires removing MSb */
 744 #define E1000_I210_FW_PTR_MASK          0x7FFF
 745 /* Firmware code revision field word offset*/
 746 #define E1000_I210_FW_VER_OFFSET        328
 747 #define E1000_EECD_FLUPD_I210           0x00800000 /* Update FLASH */
 748 #define E1000_EECD_FLUDONE_I210         0x04000000 /* Update FLASH done*/
 749 #define E1000_FLUDONE_ATTEMPTS          20000
 750 #define E1000_EERD_EEWR_MAX_COUNT       512 /* buffered EEPROM words rw */
 751 #define E1000_I210_FIFO_SEL_RX          0x00
 752 #define E1000_I210_FIFO_SEL_TX_QAV(_i)  (0x02 + (_i))
 753 #define E1000_I210_FIFO_SEL_TX_LEGACY   E1000_I210_FIFO_SEL_TX_QAV(0)
 754 #define E1000_I210_FIFO_SEL_BMC2OS_TX   0x06
 755 #define E1000_I210_FIFO_SEL_BMC2OS_RX   0x01
 756
 757
 758 /* Offset to data in NVM read/write registers */
 759 #define E1000_NVM_RW_REG_DATA   16
 760 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
 761 #define E1000_NVM_RW_REG_START  1    /* Start operation */
 762 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
 763 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
 764
 765 /* NVM Word Offsets */
 766 #define NVM_COMPAT                 0x0003
 767 #define NVM_ID_LED_SETTINGS        0x0004 /* SERDES output amplitude */
 768 #define NVM_VERSION                0x0005
 769 #define NVM_INIT_CONTROL2_REG      0x000F
 770 #define NVM_INIT_CONTROL3_PORT_B   0x0014
 771 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 772 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 773 #define NVM_CHECKSUM_REG           0x003F
 774 #define NVM_COMPATIBILITY_REG_3    0x0003
 775 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
 776 #define NVM_MAC_ADDR               0x0000
 777 #define NVM_SUB_DEV_ID             0x000B
 778 #define NVM_SUB_VEN_ID             0x000C
 779 #define NVM_DEV_ID                 0x000D
 780 #define NVM_VEN_ID                 0x000E
 781 #define NVM_INIT_CTRL_2            0x000F
 782 #define NVM_INIT_CTRL_4            0x0013
 783 #define NVM_LED_1_CFG              0x001C
 784 #define NVM_LED_0_2_CFG            0x001F
 785 #define NVM_ETRACK_WORD            0x0042
 786 #define NVM_ETRACK_HIWORD          0x0043
 787 #define NVM_COMB_VER_OFF           0x0083
 788 #define NVM_COMB_VER_PTR           0x003d
 789
 790 /* NVM version defines */
 791 #define NVM_MAJOR_MASK                  0xF000
 792 #define NVM_MINOR_MASK                  0x0FF0
 793 #define NVM_IMAGE_ID_MASK               0x000F
 794 #define NVM_COMB_VER_MASK               0x00FF
 795 #define NVM_MAJOR_SHIFT                 12
 796 #define NVM_MINOR_SHIFT                 4
 797 #define NVM_COMB_VER_SHFT               8
 798 #define NVM_VER_INVALID                 0xFFFF
 799 #define NVM_ETRACK_SHIFT                16
 800 #define NVM_ETRACK_VALID                0x8000
 801 #define NVM_NEW_DEC_MASK                0x0F00
 802 #define NVM_HEX_CONV                    16
 803 #define NVM_HEX_TENS                    10
 804
 805 #define NVM_ETS_CFG                     0x003E
 806 #define NVM_ETS_LTHRES_DELTA_MASK       0x07C0
 807 #define NVM_ETS_LTHRES_DELTA_SHIFT      6
 808 #define NVM_ETS_TYPE_MASK               0x0038
 809 #define NVM_ETS_TYPE_SHIFT              3
 810 #define NVM_ETS_TYPE_EMC                0x000
 811 #define NVM_ETS_NUM_SENSORS_MASK        0x0007
 812 #define NVM_ETS_DATA_LOC_MASK           0x3C00
 813 #define NVM_ETS_DATA_LOC_SHIFT          10
 814 #define NVM_ETS_DATA_INDEX_MASK         0x0300
 815 #define NVM_ETS_DATA_INDEX_SHIFT        8
 816 #define NVM_ETS_DATA_HTHRESH_MASK       0x00FF
 817
 818 #define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
 819 #define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
 820 #define E1000_NVM_CFG_DONE_PORT_2  0x100000 /* ...for third port */
 821 #define E1000_NVM_CFG_DONE_PORT_3  0x200000 /* ...for fourth port */
 822
 823 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
 824
 825 /* Mask bits for fields in Word 0x24 of the NVM */
 826 #define NVM_WORD24_COM_MDIO         0x0008 /* MDIO interface shared */
 827 #define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
 828
 829 /* Mask bits for fields in Word 0x0f of the NVM */
 830 #define NVM_WORD0F_PAUSE_MASK       0x3000
 831 #define NVM_WORD0F_ASM_DIR          0x2000
 832
 833 /* Mask bits for fields in Word 0x1a of the NVM */
 834
 835 /* length of string needed to store part num */
 836 #define E1000_PBANUM_LENGTH         11
 837
 838 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 839 #define NVM_SUM                    0xBABA
 840
 841 #define NVM_PBA_OFFSET_0           8
 842 #define NVM_PBA_OFFSET_1           9
 843 #define NVM_RESERVED_WORD               0xFFFF
 844 #define NVM_PBA_PTR_GUARD          0xFAFA
 845 #define NVM_WORD_SIZE_BASE_SHIFT   6
 846
 847 /* NVM Commands - Microwire */
 848
 849 /* NVM Commands - SPI */
 850 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 851 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
 852 #define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
 853 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 854 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 855 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
 856
 857 /* SPI NVM Status Register */
 858 #define NVM_STATUS_RDY_SPI         0x01
 859
 860 /* Word definitions for ID LED Settings */
 861 #define ID_LED_RESERVED_0000 0x0000
 862 #define ID_LED_RESERVED_FFFF 0xFFFF
 863 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
 864                               (ID_LED_OFF1_OFF2 <<  8) | \
 865                               (ID_LED_DEF1_DEF2 <<  4) | \
 866                               (ID_LED_DEF1_DEF2))
 867 #define ID_LED_DEF1_DEF2     0x1
 868 #define ID_LED_DEF1_ON2      0x2
 869 #define ID_LED_DEF1_OFF2     0x3
 870 #define ID_LED_ON1_DEF2      0x4
 871 #define ID_LED_ON1_ON2       0x5
 872 #define ID_LED_ON1_OFF2      0x6
 873 #define ID_LED_OFF1_DEF2     0x7
 874 #define ID_LED_OFF1_ON2      0x8
 875 #define ID_LED_OFF1_OFF2     0x9
 876
 877 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
 878 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 879 #define IGP_LED3_MODE           0x07000000
 880
 881 /* PCI/PCI-X/PCI-EX Config space */
 882 #define PCIE_DEVICE_CONTROL2         0x28
 883 #define PCIE_DEVICE_CONTROL2_16ms    0x0005
 884
 885 #define PHY_REVISION_MASK      0xFFFFFFF0
 886 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 887 #define MAX_PHY_MULTI_PAGE_REG 0xF
 888
 889 /* Bit definitions for valid PHY IDs. */
 890 /* I = Integrated
 891  * E = External
 892  */
 893 #define M88E1111_I_PHY_ID    0x01410CC0
 894 #define M88E1112_E_PHY_ID    0x01410C90
 895 #define I347AT4_E_PHY_ID     0x01410DC0
 896 #define IGP03E1000_E_PHY_ID  0x02A80390
 897 #define I82580_I_PHY_ID      0x015403A0
 898 #define I350_I_PHY_ID        0x015403B0
 899 #define M88_VENDOR           0x0141
 900 #define I210_I_PHY_ID        0x01410C00
 901 #define M88E1543_E_PHY_ID    0x01410EA0
 902 #define M88E1512_E_PHY_ID    0x01410DD0
 903 #define BCM54616_E_PHY_ID    0x03625D10
 904
 905 /* M88E1000 Specific Registers */
 906 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 907 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 908 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 909
 910 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
 911 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
 912
 913 /* M88E1000 PHY Specific Control Register */
 914 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 915 /* 1=CLK125 low, 0=CLK125 toggling */
 916 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 917                                                /* Manual MDI configuration */
 918 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 919 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 920 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 921 /* Auto crossover enabled all speeds */
 922 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
 923 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
 924  * 0=Normal 10BASE-T Rx Threshold
 925  */
 926 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
 927 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
 928
 929 /* M88E1000 PHY Specific Status Register */
 930 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 931 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
 932 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 933 /* 0 = <50M
 934  * 1 = 50-80M
 935  * 2 = 80-110M
 936  * 3 = 110-140M
 937  * 4 = >140M
 938  */
 939 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
 940 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 941 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 942
 943 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 944
 945 /* M88E1000 Extended PHY Specific Control Register */
 946 /* 1 = Lost lock detect enabled.
 947  * Will assert lost lock and bring
 948  * link down if idle not seen
 949  * within 1ms in 1000BASE-T
 950  */
 951 /* Number of times we will attempt to autonegotiate before downshifting if we
 952  * are the master
 953  */
 954 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 955 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
 956 /* Number of times we will attempt to autonegotiate before downshifting if we
 957  * are the slave
 958  */
 959 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 960 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 961 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 962
 963 /* Intel i347-AT4 Registers */
 964
 965 #define I347AT4_PCDL0                  0x10 /* Pair 0 PHY Cable Diagnostics Length */
 966 #define I347AT4_PCDL1                  0x11 /* Pair 1 PHY Cable Diagnostics Length */
 967 #define I347AT4_PCDL2                  0x12 /* Pair 2 PHY Cable Diagnostics Length */
 968 #define I347AT4_PCDL3                  0x13 /* Pair 3 PHY Cable Diagnostics Length */
 969 #define I347AT4_PCDC                   0x15 /* PHY Cable Diagnostics Control */
 970 #define I347AT4_PAGE_SELECT            0x16
 971
 972 /* i347-AT4 Extended PHY Specific Control Register */
 973
 974 /*  Number of times we will attempt to autonegotiate before downshifting if we
 975  *  are the master
 976  */
 977 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
 978 #define I347AT4_PSCR_DOWNSHIFT_MASK   0x7000
 979 #define I347AT4_PSCR_DOWNSHIFT_1X     0x0000
 980 #define I347AT4_PSCR_DOWNSHIFT_2X     0x1000
 981 #define I347AT4_PSCR_DOWNSHIFT_3X     0x2000
 982 #define I347AT4_PSCR_DOWNSHIFT_4X     0x3000
 983 #define I347AT4_PSCR_DOWNSHIFT_5X     0x4000
 984 #define I347AT4_PSCR_DOWNSHIFT_6X     0x5000
 985 #define I347AT4_PSCR_DOWNSHIFT_7X     0x6000
 986 #define I347AT4_PSCR_DOWNSHIFT_8X     0x7000
 987
 988 /* i347-AT4 PHY Cable Diagnostics Control */
 989 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
 990
 991 /* Marvell 1112 only registers */
 992 #define M88E1112_VCT_DSP_DISTANCE       0x001A
 993
 994 /* M88EC018 Rev 2 specific DownShift settings */
 995 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 996 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
 997
 998 /* MDI Control */
 999 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1000 #define E1000_MDIC_REG_MASK  0x001F0000
1001 #define E1000_MDIC_REG_SHIFT 16
1002 #define E1000_MDIC_PHY_MASK  0x03E00000
1003 #define E1000_MDIC_PHY_SHIFT 21
1004 #define E1000_MDIC_OP_WRITE  0x04000000
1005 #define E1000_MDIC_OP_READ   0x08000000
1006 #define E1000_MDIC_READY     0x10000000
1007 #define E1000_MDIC_INT_EN    0x20000000
1008 #define E1000_MDIC_ERROR     0x40000000
1009 #define E1000_MDIC_DEST      0x80000000
1010
1011 /* Thermal Sensor */
1012 #define E1000_THSTAT_PWR_DOWN       0x00000001 /* Power Down Event */
1013 #define E1000_THSTAT_LINK_THROTTLE  0x00000002 /* Link Speed Throttle Event */
1014
1015 /* Energy Efficient Ethernet */
1016 #define E1000_IPCNFG_EEE_1G_AN       0x00000008  /* EEE Enable 1G AN */
1017 #define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
1018 #define E1000_EEER_TX_LPI_EN         0x00010000  /* EEE Tx LPI Enable */
1019 #define E1000_EEER_RX_LPI_EN         0x00020000  /* EEE Rx LPI Enable */
1020 #define E1000_EEER_FRC_AN            0x10000000  /* Enable EEE in loopback */
1021 #define E1000_EEER_LPI_FC            0x00040000  /* EEE Enable on FC */
1022 #define E1000_EEE_SU_LPI_CLK_STP     0X00800000  /* EEE LPI Clock Stop */
1023 #define E1000_EEER_EEE_NEG           0x20000000  /* EEE capability nego */
1024 #define E1000_EEE_LP_ADV_ADDR_I350   0x040F      /* EEE LP Advertisement */
1025 #define E1000_EEE_LP_ADV_DEV_I210    7           /* EEE LP Adv Device */
1026 #define E1000_EEE_LP_ADV_ADDR_I210   61          /* EEE LP Adv Register */
1027 #define E1000_MMDAC_FUNC_DATA        0x4000      /* Data, no post increment */
1028 #define E1000_M88E1543_PAGE_ADDR        0x16       /* Page Offset Register */
1029 #define E1000_M88E1543_EEE_CTRL_1       0x0
1030 #define E1000_M88E1543_EEE_CTRL_1_MS    0x0001     /* EEE Master/Slave */
1031 #define E1000_M88E1543_FIBER_CTRL       0x0
1032 #define E1000_EEE_ADV_DEV_I354          7
1033 #define E1000_EEE_ADV_ADDR_I354         60
1034 #define E1000_EEE_ADV_100_SUPPORTED     BIT(1)   /* 100BaseTx EEE Supported */
1035 #define E1000_EEE_ADV_1000_SUPPORTED    BIT(2)   /* 1000BaseT EEE Supported */
1036 #define E1000_PCS_STATUS_DEV_I354       3
1037 #define E1000_PCS_STATUS_ADDR_I354      1
1038 #define E1000_PCS_STATUS_TX_LPI_IND     0x0200     /* Tx in LPI state */
1039 #define E1000_PCS_STATUS_RX_LPI_RCVD    0x0400
1040 #define E1000_PCS_STATUS_TX_LPI_RCVD    0x0800
1041
1042 /* SerDes Control */
1043 #define E1000_GEN_CTL_READY             0x80000000
1044 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
1045 #define E1000_GEN_POLL_TIMEOUT          640
1046
1047 #define E1000_VFTA_ENTRY_SHIFT               5
1048 #define E1000_VFTA_ENTRY_MASK                0x7F
1049 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
1050
1051 /* DMA Coalescing register fields */
1052 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power on DMA coal */
1053
1054 /* Tx Rate-Scheduler Config fields */
1055 #define E1000_RTTBCNRC_RS_ENA           0x80000000
1056 #define E1000_RTTBCNRC_RF_DEC_MASK      0x00003FFF
1057 #define E1000_RTTBCNRC_RF_INT_SHIFT     14
1058 #define E1000_RTTBCNRC_RF_INT_MASK      \
1059         (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1060
1061 #define E1000_VLAPQF_QUEUE_SEL(_n, q_idx) (q_idx << ((_n) * 4))
1062 #define E1000_VLAPQF_P_VALID(_n)        (0x1 << (3 + (_n) * 4))
1063 #define E1000_VLAPQF_QUEUE_MASK 0x03
1064
1065 /* TX Qav Control fields */
1066 #define E1000_TQAVCTRL_XMIT_MODE        BIT(0)
1067 #define E1000_TQAVCTRL_DATAFETCHARB     BIT(4)
1068 #define E1000_TQAVCTRL_DATATRANARB      BIT(8)
1069
1070 /* TX Qav Credit Control fields */
1071 #define E1000_TQAVCC_IDLESLOPE_MASK     0xFFFF
1072 #define E1000_TQAVCC_QUEUEMODE          BIT(31)
1073
1074 /* Transmit Descriptor Control fields */
1075 #define E1000_TXDCTL_PRIORITY           BIT(27)
1076
1077 #endif