drivers/net/ethernet/intel/igb/igb.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* Linux PRO/1000 Ethernet Driver main header file */
  25
  26 #ifndef _IGB_H_
  27 #define _IGB_H_
  28
  29 #include "e1000_mac.h"
  30 #include "e1000_82575.h"
  31
  32 #include <linux/timecounter.h>
  33 #include <linux/net_tstamp.h>
  34 #include <linux/ptp_clock_kernel.h>
  35 #include <linux/bitops.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/pci.h>
  40 #include <linux/mdio.h>
  41
  42 struct igb_adapter;
  43
  44 #define E1000_PCS_CFG_IGN_SD    1
  45
  46 /* Interrupt defines */
  47 #define IGB_START_ITR           648 /* ~6000 ints/sec */
  48 #define IGB_4K_ITR              980
  49 #define IGB_20K_ITR             196
  50 #define IGB_70K_ITR             56
  51
  52 /* TX/RX descriptor defines */
  53 #define IGB_DEFAULT_TXD         256
  54 #define IGB_DEFAULT_TX_WORK     128
  55 #define IGB_MIN_TXD             80
  56 #define IGB_MAX_TXD             4096
  57
  58 #define IGB_DEFAULT_RXD         256
  59 #define IGB_MIN_RXD             80
  60 #define IGB_MAX_RXD             4096
  61
  62 #define IGB_DEFAULT_ITR         3 /* dynamic */
  63 #define IGB_MAX_ITR_USECS       10000
  64 #define IGB_MIN_ITR_USECS       10
  65 #define NON_Q_VECTORS           1
  66 #define MAX_Q_VECTORS           8
  67 #define MAX_MSIX_ENTRIES        10
  68
  69 /* Transmit and receive queues */
  70 #define IGB_MAX_RX_QUEUES       8
  71 #define IGB_MAX_RX_QUEUES_82575 4
  72 #define IGB_MAX_RX_QUEUES_I211  2
  73 #define IGB_MAX_TX_QUEUES       8
  74 #define IGB_MAX_VF_MC_ENTRIES   30
  75 #define IGB_MAX_VF_FUNCTIONS    8
  76 #define IGB_MAX_VFTA_ENTRIES    128
  77 #define IGB_82576_VF_DEV_ID     0x10CA
  78 #define IGB_I350_VF_DEV_ID      0x1520
  79
  80 /* NVM version defines */
  81 #define IGB_MAJOR_MASK          0xF000
  82 #define IGB_MINOR_MASK          0x0FF0
  83 #define IGB_BUILD_MASK          0x000F
  84 #define IGB_COMB_VER_MASK       0x00FF
  85 #define IGB_MAJOR_SHIFT         12
  86 #define IGB_MINOR_SHIFT         4
  87 #define IGB_COMB_VER_SHFT       8
  88 #define IGB_NVM_VER_INVALID     0xFFFF
  89 #define IGB_ETRACK_SHIFT        16
  90 #define NVM_ETRACK_WORD         0x0042
  91 #define NVM_COMB_VER_OFF        0x0083
  92 #define NVM_COMB_VER_PTR        0x003d
  93
  94 /* Transmit and receive latency (for PTP timestamps) */
  95 #define IGB_I210_TX_LATENCY_10          9542
  96 #define IGB_I210_TX_LATENCY_100         1024
  97 #define IGB_I210_TX_LATENCY_1000        178
  98 #define IGB_I210_RX_LATENCY_10          20662
  99 #define IGB_I210_RX_LATENCY_100         2213
 100 #define IGB_I210_RX_LATENCY_1000        448
 101
 102 struct vf_data_storage {
 103         unsigned char vf_mac_addresses[ETH_ALEN];
 104         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
 105         u16 num_vf_mc_hashes;
 106         u32 flags;
 107         unsigned long last_nack;
 108         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 109         u16 pf_qos;
 110         u16 tx_rate;
 111         bool spoofchk_enabled;
 112 };
 113
 114 /* Number of unicast MAC filters reserved for the PF in the RAR registers */
 115 #define IGB_PF_MAC_FILTERS_RESERVED     3
 116
 117 struct vf_mac_filter {
 118         struct list_head l;
 119         int vf;
 120         bool free;
 121         u8 vf_mac[ETH_ALEN];
 122 };
 123
 124 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
 125 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
 126 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
 127 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
 128
 129 /* RX descriptor control thresholds.
 130  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 131  *           descriptors available in its onboard memory.
 132  *           Setting this to 0 disables RX descriptor prefetch.
 133  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 134  *           available in host memory.
 135  *           If PTHRESH is 0, this should also be 0.
 136  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 137  *           descriptors until either it has this many to write back, or the
 138  *           ITR timer expires.
 139  */
 140 #define IGB_RX_PTHRESH  ((hw->mac.type == e1000_i354) ? 12 : 8)
 141 #define IGB_RX_HTHRESH  8
 142 #define IGB_TX_PTHRESH  ((hw->mac.type == e1000_i354) ? 20 : 8)
 143 #define IGB_TX_HTHRESH  1
 144 #define IGB_RX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 145                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
 146 #define IGB_TX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 147                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
 148
 149 /* this is the size past which hardware will drop packets when setting LPE=0 */
 150 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 151
 152 /* Supported Rx Buffer Sizes */
 153 #define IGB_RXBUFFER_256        256
 154 #define IGB_RXBUFFER_2048       2048
 155 #define IGB_RXBUFFER_3072       3072
 156 #define IGB_RX_HDR_LEN          IGB_RXBUFFER_256
 157 #define IGB_TS_HDR_LEN          16
 158
 159 #define IGB_SKB_PAD             (NET_SKB_PAD + NET_IP_ALIGN)
 160 #if (PAGE_SIZE < 8192)
 161 #define IGB_MAX_FRAME_BUILD_SKB \
 162         (SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN)
 163 #else
 164 #define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN)
 165 #endif
 166
 167 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 168 #define IGB_RX_BUFFER_WRITE     16 /* Must be power of 2 */
 169
 170 #define IGB_RX_DMA_ATTR \
 171         (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
 172
 173 #define AUTO_ALL_MODES          0
 174 #define IGB_EEPROM_APME         0x0400
 175
 176 #ifndef IGB_MASTER_SLAVE
 177 /* Switch to override PHY master/slave setting */
 178 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 179 #endif
 180
 181 #define IGB_MNG_VLAN_NONE       -1
 182
 183 enum igb_tx_flags {
 184         /* cmd_type flags */
 185         IGB_TX_FLAGS_VLAN       = 0x01,
 186         IGB_TX_FLAGS_TSO        = 0x02,
 187         IGB_TX_FLAGS_TSTAMP     = 0x04,
 188
 189         /* olinfo flags */
 190         IGB_TX_FLAGS_IPV4       = 0x10,
 191         IGB_TX_FLAGS_CSUM       = 0x20,
 192 };
 193
 194 /* VLAN info */
 195 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
 196 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 197
 198 /* The largest size we can write to the descriptor is 65535.  In order to
 199  * maintain a power of two alignment we have to limit ourselves to 32K.
 200  */
 201 #define IGB_MAX_TXD_PWR 15
 202 #define IGB_MAX_DATA_PER_TXD    (1u << IGB_MAX_TXD_PWR)
 203
 204 /* Tx Descriptors needed, worst case */
 205 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
 206 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 207
 208 /* EEPROM byte offsets */
 209 #define IGB_SFF_8472_SWAP               0x5C
 210 #define IGB_SFF_8472_COMP               0x5E
 211
 212 /* Bitmasks */
 213 #define IGB_SFF_ADDRESSING_MODE         0x4
 214 #define IGB_SFF_8472_UNSUP              0x00
 215
 216 /* wrapper around a pointer to a socket buffer,
 217  * so a DMA handle can be stored along with the buffer
 218  */
 219 struct igb_tx_buffer {
 220         union e1000_adv_tx_desc *next_to_watch;
 221         unsigned long time_stamp;
 222         struct sk_buff *skb;
 223         unsigned int bytecount;
 224         u16 gso_segs;
 225         __be16 protocol;
 226
 227         DEFINE_DMA_UNMAP_ADDR(dma);
 228         DEFINE_DMA_UNMAP_LEN(len);
 229         u32 tx_flags;
 230 };
 231
 232 struct igb_rx_buffer {
 233         dma_addr_t dma;
 234         struct page *page;
 235 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
 236         __u32 page_offset;
 237 #else
 238         __u16 page_offset;
 239 #endif
 240         __u16 pagecnt_bias;
 241 };
 242
 243 struct igb_tx_queue_stats {
 244         u64 packets;
 245         u64 bytes;
 246         u64 restart_queue;
 247         u64 restart_queue2;
 248 };
 249
 250 struct igb_rx_queue_stats {
 251         u64 packets;
 252         u64 bytes;
 253         u64 drops;
 254         u64 csum_err;
 255         u64 alloc_failed;
 256 };
 257
 258 struct igb_ring_container {
 259         struct igb_ring *ring;          /* pointer to linked list of rings */
 260         unsigned int total_bytes;       /* total bytes processed this int */
 261         unsigned int total_packets;     /* total packets processed this int */
 262         u16 work_limit;                 /* total work allowed per interrupt */
 263         u8 count;                       /* total number of rings in vector */
 264         u8 itr;                         /* current ITR setting for ring */
 265 };
 266
 267 struct igb_ring {
 268         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 269         struct net_device *netdev;      /* back pointer to net_device */
 270         struct device *dev;             /* device pointer for dma mapping */
 271         union {                         /* array of buffer info structs */
 272                 struct igb_tx_buffer *tx_buffer_info;
 273                 struct igb_rx_buffer *rx_buffer_info;
 274         };
 275         void *desc;                     /* descriptor ring memory */
 276         unsigned long flags;            /* ring specific flags */
 277         void __iomem *tail;             /* pointer to ring tail register */
 278         dma_addr_t dma;                 /* phys address of the ring */
 279         unsigned int  size;             /* length of desc. ring in bytes */
 280
 281         u16 count;                      /* number of desc. in the ring */
 282         u8 queue_index;                 /* logical index of the ring*/
 283         u8 reg_idx;                     /* physical index of the ring */
 284         bool cbs_enable;                /* indicates if CBS is enabled */
 285         s32 idleslope;                  /* idleSlope in kbps */
 286         s32 sendslope;                  /* sendSlope in kbps */
 287         s32 hicredit;                   /* hiCredit in bytes */
 288         s32 locredit;                   /* loCredit in bytes */
 289
 290         /* everything past this point are written often */
 291         u16 next_to_clean;
 292         u16 next_to_use;
 293         u16 next_to_alloc;
 294
 295         union {
 296                 /* TX */
 297                 struct {
 298                         struct igb_tx_queue_stats tx_stats;
 299                         struct u64_stats_sync tx_syncp;
 300                         struct u64_stats_sync tx_syncp2;
 301                 };
 302                 /* RX */
 303                 struct {
 304                         struct sk_buff *skb;
 305                         struct igb_rx_queue_stats rx_stats;
 306                         struct u64_stats_sync rx_syncp;
 307                 };
 308         };
 309 } ____cacheline_internodealigned_in_smp;
 310
 311 struct igb_q_vector {
 312         struct igb_adapter *adapter;    /* backlink */
 313         int cpu;                        /* CPU for DCA */
 314         u32 eims_value;                 /* EIMS mask value */
 315
 316         u16 itr_val;
 317         u8 set_itr;
 318         void __iomem *itr_register;
 319
 320         struct igb_ring_container rx, tx;
 321
 322         struct napi_struct napi;
 323         struct rcu_head rcu;    /* to avoid race with update stats on free */
 324         char name[IFNAMSIZ + 9];
 325
 326         /* for dynamic allocation of rings associated with this q_vector */
 327         struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
 328 };
 329
 330 enum e1000_ring_flags_t {
 331         IGB_RING_FLAG_RX_3K_BUFFER,
 332         IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
 333         IGB_RING_FLAG_RX_SCTP_CSUM,
 334         IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 335         IGB_RING_FLAG_TX_CTX_IDX,
 336         IGB_RING_FLAG_TX_DETECT_HANG
 337 };
 338
 339 #define ring_uses_large_buffer(ring) \
 340         test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
 341 #define set_ring_uses_large_buffer(ring) \
 342         set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
 343 #define clear_ring_uses_large_buffer(ring) \
 344         clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
 345
 346 #define ring_uses_build_skb(ring) \
 347         test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
 348 #define set_ring_build_skb_enabled(ring) \
 349         set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
 350 #define clear_ring_build_skb_enabled(ring) \
 351         clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
 352
 353 static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
 354 {
 355 #if (PAGE_SIZE < 8192)
 356         if (ring_uses_large_buffer(ring))
 357                 return IGB_RXBUFFER_3072;
 358
 359         if (ring_uses_build_skb(ring))
 360                 return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN;
 361 #endif
 362         return IGB_RXBUFFER_2048;
 363 }
 364
 365 static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
 366 {
 367 #if (PAGE_SIZE < 8192)
 368         if (ring_uses_large_buffer(ring))
 369                 return 1;
 370 #endif
 371         return 0;
 372 }
 373
 374 #define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
 375
 376 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 377
 378 #define IGB_RX_DESC(R, i)       \
 379         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 380 #define IGB_TX_DESC(R, i)       \
 381         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 382 #define IGB_TX_CTXTDESC(R, i)   \
 383         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 384
 385 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 386 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 387                                       const u32 stat_err_bits)
 388 {
 389         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 390 }
 391
 392 /* igb_desc_unused - calculate if we have unused descriptors */
 393 static inline int igb_desc_unused(struct igb_ring *ring)
 394 {
 395         if (ring->next_to_clean > ring->next_to_use)
 396                 return ring->next_to_clean - ring->next_to_use - 1;
 397
 398         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 399 }
 400
 401 #ifdef CONFIG_IGB_HWMON
 402
 403 #define IGB_HWMON_TYPE_LOC      0
 404 #define IGB_HWMON_TYPE_TEMP     1
 405 #define IGB_HWMON_TYPE_CAUTION  2
 406 #define IGB_HWMON_TYPE_MAX      3
 407
 408 struct hwmon_attr {
 409         struct device_attribute dev_attr;
 410         struct e1000_hw *hw;
 411         struct e1000_thermal_diode_data *sensor;
 412         char name[12];
 413         };
 414
 415 struct hwmon_buff {
 416         struct attribute_group group;
 417         const struct attribute_group *groups[2];
 418         struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
 419         struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
 420         unsigned int n_hwmon;
 421         };
 422 #endif
 423
 424 /* The number of L2 ether-type filter registers, Index 3 is reserved
 425  * for PTP 1588 timestamp
 426  */
 427 #define MAX_ETYPE_FILTER        (4 - 1)
 428 /* ETQF filter list: one static filter per filter consumer. This is
 429  * to avoid filter collisions later. Add new filters here!!
 430  *
 431  * Current filters:             Filter 3
 432  */
 433 #define IGB_ETQF_FILTER_1588    3
 434
 435 #define IGB_N_EXTTS     2
 436 #define IGB_N_PEROUT    2
 437 #define IGB_N_SDP       4
 438 #define IGB_RETA_SIZE   128
 439
 440 enum igb_filter_match_flags {
 441         IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
 442         IGB_FILTER_FLAG_VLAN_TCI   = 0x2,
 443 };
 444
 445 #define IGB_MAX_RXNFC_FILTERS 16
 446
 447 /* RX network flow classification data structure */
 448 struct igb_nfc_input {
 449         /* Byte layout in order, all values with MSB first:
 450          * match_flags - 1 byte
 451          * etype - 2 bytes
 452          * vlan_tci - 2 bytes
 453          */
 454         u8 match_flags;
 455         __be16 etype;
 456         __be16 vlan_tci;
 457 };
 458
 459 struct igb_nfc_filter {
 460         struct hlist_node nfc_node;
 461         struct igb_nfc_input filter;
 462         u16 etype_reg_index;
 463         u16 sw_idx;
 464         u16 action;
 465 };
 466
 467 struct igb_mac_addr {
 468         u8 addr[ETH_ALEN];
 469         u8 queue;
 470         u8 state; /* bitmask */
 471 };
 472
 473 #define IGB_MAC_STATE_DEFAULT   0x1
 474 #define IGB_MAC_STATE_IN_USE    0x2
 475
 476 /* board specific private data structure */
 477 struct igb_adapter {
 478         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 479
 480         struct net_device *netdev;
 481
 482         unsigned long state;
 483         unsigned int flags;
 484
 485         unsigned int num_q_vectors;
 486         struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
 487
 488         /* Interrupt Throttle Rate */
 489         u32 rx_itr_setting;
 490         u32 tx_itr_setting;
 491         u16 tx_itr;
 492         u16 rx_itr;
 493
 494         /* TX */
 495         u16 tx_work_limit;
 496         u32 tx_timeout_count;
 497         int num_tx_queues;
 498         struct igb_ring *tx_ring[16];
 499
 500         /* RX */
 501         int num_rx_queues;
 502         struct igb_ring *rx_ring[16];
 503
 504         u32 max_frame_size;
 505         u32 min_frame_size;
 506
 507         struct timer_list watchdog_timer;
 508         struct timer_list phy_info_timer;
 509
 510         u16 mng_vlan_id;
 511         u32 bd_number;
 512         u32 wol;
 513         u32 en_mng_pt;
 514         u16 link_speed;
 515         u16 link_duplex;
 516
 517         u8 __iomem *io_addr; /* Mainly for iounmap use */
 518
 519         struct work_struct reset_task;
 520         struct work_struct watchdog_task;
 521         bool fc_autoneg;
 522         u8  tx_timeout_factor;
 523         struct timer_list blink_timer;
 524         unsigned long led_status;
 525
 526         /* OS defined structs */
 527         struct pci_dev *pdev;
 528
 529         spinlock_t stats64_lock;
 530         struct rtnl_link_stats64 stats64;
 531
 532         /* structs defined in e1000_hw.h */
 533         struct e1000_hw hw;
 534         struct e1000_hw_stats stats;
 535         struct e1000_phy_info phy_info;
 536
 537         u32 test_icr;
 538         struct igb_ring test_tx_ring;
 539         struct igb_ring test_rx_ring;
 540
 541         int msg_enable;
 542
 543         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 544         u32 eims_enable_mask;
 545         u32 eims_other;
 546
 547         /* to not mess up cache alignment, always add to the bottom */
 548         u16 tx_ring_count;
 549         u16 rx_ring_count;
 550         unsigned int vfs_allocated_count;
 551         struct vf_data_storage *vf_data;
 552         int vf_rate_link_speed;
 553         u32 rss_queues;
 554         u32 wvbr;
 555         u32 *shadow_vfta;
 556
 557         struct ptp_clock *ptp_clock;
 558         struct ptp_clock_info ptp_caps;
 559         struct delayed_work ptp_overflow_work;
 560         struct work_struct ptp_tx_work;
 561         struct sk_buff *ptp_tx_skb;
 562         struct hwtstamp_config tstamp_config;
 563         unsigned long ptp_tx_start;
 564         unsigned long last_rx_ptp_check;
 565         unsigned long last_rx_timestamp;
 566         unsigned int ptp_flags;
 567         spinlock_t tmreg_lock;
 568         struct cyclecounter cc;
 569         struct timecounter tc;
 570         u32 tx_hwtstamp_timeouts;
 571         u32 tx_hwtstamp_skipped;
 572         u32 rx_hwtstamp_cleared;
 573         bool pps_sys_wrap_on;
 574
 575         struct ptp_pin_desc sdp_config[IGB_N_SDP];
 576         struct {
 577                 struct timespec64 start;
 578                 struct timespec64 period;
 579         } perout[IGB_N_PEROUT];
 580
 581         char fw_version[32];
 582 #ifdef CONFIG_IGB_HWMON
 583         struct hwmon_buff *igb_hwmon_buff;
 584         bool ets;
 585 #endif
 586         struct i2c_algo_bit_data i2c_algo;
 587         struct i2c_adapter i2c_adap;
 588         struct i2c_client *i2c_client;
 589         u32 rss_indir_tbl_init;
 590         u8 rss_indir_tbl[IGB_RETA_SIZE];
 591
 592         unsigned long link_check_timeout;
 593         int copper_tries;
 594         struct e1000_info ei;
 595         u16 eee_advert;
 596
 597         /* RX network flow classification support */
 598         struct hlist_head nfc_filter_list;
 599         unsigned int nfc_filter_count;
 600         /* lock for RX network flow classification filter */
 601         spinlock_t nfc_lock;
 602         bool etype_bitmap[MAX_ETYPE_FILTER];
 603
 604         struct igb_mac_addr *mac_table;
 605         struct vf_mac_filter vf_macs;
 606         struct vf_mac_filter *vf_mac_list;
 607 };
 608
 609 /* flags controlling PTP/1588 function */
 610 #define IGB_PTP_ENABLED         BIT(0)
 611 #define IGB_PTP_OVERFLOW_CHECK  BIT(1)
 612
 613 #define IGB_FLAG_HAS_MSI                BIT(0)
 614 #define IGB_FLAG_DCA_ENABLED            BIT(1)
 615 #define IGB_FLAG_QUAD_PORT_A            BIT(2)
 616 #define IGB_FLAG_QUEUE_PAIRS            BIT(3)
 617 #define IGB_FLAG_DMAC                   BIT(4)
 618 #define IGB_FLAG_RSS_FIELD_IPV4_UDP     BIT(6)
 619 #define IGB_FLAG_RSS_FIELD_IPV6_UDP     BIT(7)
 620 #define IGB_FLAG_WOL_SUPPORTED          BIT(8)
 621 #define IGB_FLAG_NEED_LINK_UPDATE       BIT(9)
 622 #define IGB_FLAG_MEDIA_RESET            BIT(10)
 623 #define IGB_FLAG_MAS_CAPABLE            BIT(11)
 624 #define IGB_FLAG_MAS_ENABLE             BIT(12)
 625 #define IGB_FLAG_HAS_MSIX               BIT(13)
 626 #define IGB_FLAG_EEE                    BIT(14)
 627 #define IGB_FLAG_VLAN_PROMISC           BIT(15)
 628 #define IGB_FLAG_RX_LEGACY              BIT(16)
 629 #define IGB_FLAG_FQTSS                  BIT(17)
 630
 631 /* Media Auto Sense */
 632 #define IGB_MAS_ENABLE_0                0X0001
 633 #define IGB_MAS_ENABLE_1                0X0002
 634 #define IGB_MAS_ENABLE_2                0X0004
 635 #define IGB_MAS_ENABLE_3                0X0008
 636
 637 /* DMA Coalescing defines */
 638 #define IGB_MIN_TXPBSIZE        20408
 639 #define IGB_TX_BUF_4096         4096
 640 #define IGB_DMCTLX_DCFLUSH_DIS  0x80000000  /* Disable DMA Coal Flush */
 641
 642 #define IGB_82576_TSYNC_SHIFT   19
 643 enum e1000_state_t {
 644         __IGB_TESTING,
 645         __IGB_RESETTING,
 646         __IGB_DOWN,
 647         __IGB_PTP_TX_IN_PROGRESS,
 648 };
 649
 650 enum igb_boards {
 651         board_82575,
 652 };
 653
 654 extern char igb_driver_name[];
 655 extern char igb_driver_version[];
 656
 657 int igb_open(struct net_device *netdev);
 658 int igb_close(struct net_device *netdev);
 659 int igb_up(struct igb_adapter *);
 660 void igb_down(struct igb_adapter *);
 661 void igb_reinit_locked(struct igb_adapter *);
 662 void igb_reset(struct igb_adapter *);
 663 int igb_reinit_queues(struct igb_adapter *);
 664 void igb_write_rss_indir_tbl(struct igb_adapter *);
 665 int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 666 int igb_setup_tx_resources(struct igb_ring *);
 667 int igb_setup_rx_resources(struct igb_ring *);
 668 void igb_free_tx_resources(struct igb_ring *);
 669 void igb_free_rx_resources(struct igb_ring *);
 670 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 671 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 672 void igb_setup_tctl(struct igb_adapter *);
 673 void igb_setup_rctl(struct igb_adapter *);
 674 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 675 void igb_alloc_rx_buffers(struct igb_ring *, u16);
 676 void igb_update_stats(struct igb_adapter *);
 677 bool igb_has_link(struct igb_adapter *adapter);
 678 void igb_set_ethtool_ops(struct net_device *);
 679 void igb_power_up_link(struct igb_adapter *);
 680 void igb_set_fw_version(struct igb_adapter *);
 681 void igb_ptp_init(struct igb_adapter *adapter);
 682 void igb_ptp_stop(struct igb_adapter *adapter);
 683 void igb_ptp_reset(struct igb_adapter *adapter);
 684 void igb_ptp_suspend(struct igb_adapter *adapter);
 685 void igb_ptp_rx_hang(struct igb_adapter *adapter);
 686 void igb_ptp_tx_hang(struct igb_adapter *adapter);
 687 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
 688 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
 689                          struct sk_buff *skb);
 690 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
 691 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
 692 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
 693 unsigned int igb_get_max_rss_queues(struct igb_adapter *);
 694 #ifdef CONFIG_IGB_HWMON
 695 void igb_sysfs_exit(struct igb_adapter *adapter);
 696 int igb_sysfs_init(struct igb_adapter *adapter);
 697 #endif
 698 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 699 {
 700         if (hw->phy.ops.reset)
 701                 return hw->phy.ops.reset(hw);
 702
 703         return 0;
 704 }
 705
 706 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 707 {
 708         if (hw->phy.ops.read_reg)
 709                 return hw->phy.ops.read_reg(hw, offset, data);
 710
 711         return 0;
 712 }
 713
 714 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 715 {
 716         if (hw->phy.ops.write_reg)
 717                 return hw->phy.ops.write_reg(hw, offset, data);
 718
 719         return 0;
 720 }
 721
 722 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 723 {
 724         if (hw->phy.ops.get_phy_info)
 725                 return hw->phy.ops.get_phy_info(hw);
 726
 727         return 0;
 728 }
 729
 730 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 731 {
 732         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 733 }
 734
 735 int igb_add_filter(struct igb_adapter *adapter,
 736                    struct igb_nfc_filter *input);
 737 int igb_erase_filter(struct igb_adapter *adapter,
 738                      struct igb_nfc_filter *input);
 739
 740 #endif /* _IGB_H_ */