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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
blob606e6761758f7b2bde7fdae1e7c54ae713d007fa
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 /* ethtool support for igb */
25
26 #include <linux/vmalloc.h>
27 #include <linux/netdevice.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/if_ether.h>
32 #include <linux/ethtool.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/highmem.h>
37 #include <linux/mdio.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45 };
46
47 #define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51 }
52 static const struct igb_stats igb_gstrings_stats[] = {
53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
93 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
94 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
95 };
96
97 #define IGB_NETDEV_STAT(_net_stat) { \
98 .stat_string = __stringify(_net_stat), \
99 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
100 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
101 }
102 static const struct igb_stats igb_gstrings_net_stats[] = {
103 IGB_NETDEV_STAT(rx_errors),
104 IGB_NETDEV_STAT(tx_errors),
105 IGB_NETDEV_STAT(tx_dropped),
106 IGB_NETDEV_STAT(rx_length_errors),
107 IGB_NETDEV_STAT(rx_over_errors),
108 IGB_NETDEV_STAT(rx_frame_errors),
109 IGB_NETDEV_STAT(rx_fifo_errors),
110 IGB_NETDEV_STAT(tx_fifo_errors),
111 IGB_NETDEV_STAT(tx_heartbeat_errors)
112 };
113
114 #define IGB_GLOBAL_STATS_LEN \
115 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
116 #define IGB_NETDEV_STATS_LEN \
117 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
118 #define IGB_RX_QUEUE_STATS_LEN \
119 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
120
121 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
122
123 #define IGB_QUEUE_STATS_LEN \
124 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
125 IGB_RX_QUEUE_STATS_LEN) + \
126 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
127 IGB_TX_QUEUE_STATS_LEN))
128 #define IGB_STATS_LEN \
129 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
130
131 enum igb_diagnostics_results {
132 TEST_REG = 0,
133 TEST_EEP,
134 TEST_IRQ,
135 TEST_LOOP,
136 TEST_LINK
137 };
138
139 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
140 [TEST_REG] = "Register test (offline)",
141 [TEST_EEP] = "Eeprom test (offline)",
142 [TEST_IRQ] = "Interrupt test (offline)",
143 [TEST_LOOP] = "Loopback test (offline)",
144 [TEST_LINK] = "Link test (on/offline)"
145 };
146 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
147
148 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {
149 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
150 "legacy-rx",
151 };
152
153 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)
154
155 static int igb_get_link_ksettings(struct net_device *netdev,
156 struct ethtool_link_ksettings *cmd)
157 {
158 struct igb_adapter *adapter = netdev_priv(netdev);
159 struct e1000_hw *hw = &adapter->hw;
160 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
161 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
162 u32 status;
163 u32 speed;
164 u32 supported, advertising;
165
166 status = rd32(E1000_STATUS);
167 if (hw->phy.media_type == e1000_media_type_copper) {
168
169 supported = (SUPPORTED_10baseT_Half |
170 SUPPORTED_10baseT_Full |
171 SUPPORTED_100baseT_Half |
172 SUPPORTED_100baseT_Full |
173 SUPPORTED_1000baseT_Full|
174 SUPPORTED_Autoneg |
175 SUPPORTED_TP |
176 SUPPORTED_Pause);
177 advertising = ADVERTISED_TP;
178
179 if (hw->mac.autoneg == 1) {
180 advertising |= ADVERTISED_Autoneg;
181 /* the e1000 autoneg seems to match ethtool nicely */
182 advertising |= hw->phy.autoneg_advertised;
183 }
184
185 cmd->base.port = PORT_TP;
186 cmd->base.phy_address = hw->phy.addr;
187 } else {
188 supported = (SUPPORTED_FIBRE |
189 SUPPORTED_1000baseKX_Full |
190 SUPPORTED_Autoneg |
191 SUPPORTED_Pause);
192 advertising = (ADVERTISED_FIBRE |
193 ADVERTISED_1000baseKX_Full);
194 if (hw->mac.type == e1000_i354) {
195 if ((hw->device_id ==
196 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
197 !(status & E1000_STATUS_2P5_SKU_OVER)) {
198 supported |= SUPPORTED_2500baseX_Full;
199 supported &= ~SUPPORTED_1000baseKX_Full;
200 advertising |= ADVERTISED_2500baseX_Full;
201 advertising &= ~ADVERTISED_1000baseKX_Full;
202 }
203 }
204 if (eth_flags->e100_base_fx) {
205 supported |= SUPPORTED_100baseT_Full;
206 advertising |= ADVERTISED_100baseT_Full;
207 }
208 if (hw->mac.autoneg == 1)
209 advertising |= ADVERTISED_Autoneg;
210
211 cmd->base.port = PORT_FIBRE;
212 }
213 if (hw->mac.autoneg != 1)
214 advertising &= ~(ADVERTISED_Pause |
215 ADVERTISED_Asym_Pause);
216
217 switch (hw->fc.requested_mode) {
218 case e1000_fc_full:
219 advertising |= ADVERTISED_Pause;
220 break;
221 case e1000_fc_rx_pause:
222 advertising |= (ADVERTISED_Pause |
223 ADVERTISED_Asym_Pause);
224 break;
225 case e1000_fc_tx_pause:
226 advertising |= ADVERTISED_Asym_Pause;
227 break;
228 default:
229 advertising &= ~(ADVERTISED_Pause |
230 ADVERTISED_Asym_Pause);
231 }
232 if (status & E1000_STATUS_LU) {
233 if ((status & E1000_STATUS_2P5_SKU) &&
234 !(status & E1000_STATUS_2P5_SKU_OVER)) {
235 speed = SPEED_2500;
236 } else if (status & E1000_STATUS_SPEED_1000) {
237 speed = SPEED_1000;
238 } else if (status & E1000_STATUS_SPEED_100) {
239 speed = SPEED_100;
240 } else {
241 speed = SPEED_10;
242 }
243 if ((status & E1000_STATUS_FD) ||
244 hw->phy.media_type != e1000_media_type_copper)
245 cmd->base.duplex = DUPLEX_FULL;
246 else
247 cmd->base.duplex = DUPLEX_HALF;
248 } else {
249 speed = SPEED_UNKNOWN;
250 cmd->base.duplex = DUPLEX_UNKNOWN;
251 }
252 cmd->base.speed = speed;
253 if ((hw->phy.media_type == e1000_media_type_fiber) ||
254 hw->mac.autoneg)
255 cmd->base.autoneg = AUTONEG_ENABLE;
256 else
257 cmd->base.autoneg = AUTONEG_DISABLE;
258
259 /* MDI-X => 2; MDI =>1; Invalid =>0 */
260 if (hw->phy.media_type == e1000_media_type_copper)
261 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
262 ETH_TP_MDI;
263 else
264 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
265
266 if (hw->phy.mdix == AUTO_ALL_MODES)
267 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
268 else
269 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;
270
271 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
272 supported);
273 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
274 advertising);
275
276 return 0;
277 }
278
279 static int igb_set_link_ksettings(struct net_device *netdev,
280 const struct ethtool_link_ksettings *cmd)
281 {
282 struct igb_adapter *adapter = netdev_priv(netdev);
283 struct e1000_hw *hw = &adapter->hw;
284 u32 advertising;
285
286 /* When SoL/IDER sessions are active, autoneg/speed/duplex
287 * cannot be changed
288 */
289 if (igb_check_reset_block(hw)) {
290 dev_err(&adapter->pdev->dev,
291 "Cannot change link characteristics when SoL/IDER is active.\n");
292 return -EINVAL;
293 }
294
295 /* MDI setting is only allowed when autoneg enabled because
296 * some hardware doesn't allow MDI setting when speed or
297 * duplex is forced.
298 */
299 if (cmd->base.eth_tp_mdix_ctrl) {
300 if (hw->phy.media_type != e1000_media_type_copper)
301 return -EOPNOTSUPP;
302
303 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
304 (cmd->base.autoneg != AUTONEG_ENABLE)) {
305 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
306 return -EINVAL;
307 }
308 }
309
310 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
311 usleep_range(1000, 2000);
312
313 ethtool_convert_link_mode_to_legacy_u32(&advertising,
314 cmd->link_modes.advertising);
315
316 if (cmd->base.autoneg == AUTONEG_ENABLE) {
317 hw->mac.autoneg = 1;
318 if (hw->phy.media_type == e1000_media_type_fiber) {
319 hw->phy.autoneg_advertised = advertising |
320 ADVERTISED_FIBRE |
321 ADVERTISED_Autoneg;
322 switch (adapter->link_speed) {
323 case SPEED_2500:
324 hw->phy.autoneg_advertised =
325 ADVERTISED_2500baseX_Full;
326 break;
327 case SPEED_1000:
328 hw->phy.autoneg_advertised =
329 ADVERTISED_1000baseT_Full;
330 break;
331 case SPEED_100:
332 hw->phy.autoneg_advertised =
333 ADVERTISED_100baseT_Full;
334 break;
335 default:
336 break;
337 }
338 } else {
339 hw->phy.autoneg_advertised = advertising |
340 ADVERTISED_TP |
341 ADVERTISED_Autoneg;
342 }
343 advertising = hw->phy.autoneg_advertised;
344 if (adapter->fc_autoneg)
345 hw->fc.requested_mode = e1000_fc_default;
346 } else {
347 u32 speed = cmd->base.speed;
348 /* calling this overrides forced MDI setting */
349 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {
350 clear_bit(__IGB_RESETTING, &adapter->state);
351 return -EINVAL;
352 }
353 }
354
355 /* MDI-X => 2; MDI => 1; Auto => 3 */
356 if (cmd->base.eth_tp_mdix_ctrl) {
357 /* fix up the value for auto (3 => 0) as zero is mapped
358 * internally to auto
359 */
360 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
361 hw->phy.mdix = AUTO_ALL_MODES;
362 else
363 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;
364 }
365
366 /* reset the link */
367 if (netif_running(adapter->netdev)) {
368 igb_down(adapter);
369 igb_up(adapter);
370 } else
371 igb_reset(adapter);
372
373 clear_bit(__IGB_RESETTING, &adapter->state);
374 return 0;
375 }
376
377 static u32 igb_get_link(struct net_device *netdev)
378 {
379 struct igb_adapter *adapter = netdev_priv(netdev);
380 struct e1000_mac_info *mac = &adapter->hw.mac;
381
382 /* If the link is not reported up to netdev, interrupts are disabled,
383 * and so the physical link state may have changed since we last
384 * looked. Set get_link_status to make sure that the true link
385 * state is interrogated, rather than pulling a cached and possibly
386 * stale link state from the driver.
387 */
388 if (!netif_carrier_ok(netdev))
389 mac->get_link_status = 1;
390
391 return igb_has_link(adapter);
392 }
393
394 static void igb_get_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *pause)
396 {
397 struct igb_adapter *adapter = netdev_priv(netdev);
398 struct e1000_hw *hw = &adapter->hw;
399
400 pause->autoneg =
401 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
402
403 if (hw->fc.current_mode == e1000_fc_rx_pause)
404 pause->rx_pause = 1;
405 else if (hw->fc.current_mode == e1000_fc_tx_pause)
406 pause->tx_pause = 1;
407 else if (hw->fc.current_mode == e1000_fc_full) {
408 pause->rx_pause = 1;
409 pause->tx_pause = 1;
410 }
411 }
412
413 static int igb_set_pauseparam(struct net_device *netdev,
414 struct ethtool_pauseparam *pause)
415 {
416 struct igb_adapter *adapter = netdev_priv(netdev);
417 struct e1000_hw *hw = &adapter->hw;
418 int retval = 0;
419
420 /* 100basefx does not support setting link flow control */
421 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
422 return -EINVAL;
423
424 adapter->fc_autoneg = pause->autoneg;
425
426 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
427 usleep_range(1000, 2000);
428
429 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
430 hw->fc.requested_mode = e1000_fc_default;
431 if (netif_running(adapter->netdev)) {
432 igb_down(adapter);
433 igb_up(adapter);
434 } else {
435 igb_reset(adapter);
436 }
437 } else {
438 if (pause->rx_pause && pause->tx_pause)
439 hw->fc.requested_mode = e1000_fc_full;
440 else if (pause->rx_pause && !pause->tx_pause)
441 hw->fc.requested_mode = e1000_fc_rx_pause;
442 else if (!pause->rx_pause && pause->tx_pause)
443 hw->fc.requested_mode = e1000_fc_tx_pause;
444 else if (!pause->rx_pause && !pause->tx_pause)
445 hw->fc.requested_mode = e1000_fc_none;
446
447 hw->fc.current_mode = hw->fc.requested_mode;
448
449 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
450 igb_force_mac_fc(hw) : igb_setup_link(hw));
451 }
452
453 clear_bit(__IGB_RESETTING, &adapter->state);
454 return retval;
455 }
456
457 static u32 igb_get_msglevel(struct net_device *netdev)
458 {
459 struct igb_adapter *adapter = netdev_priv(netdev);
460 return adapter->msg_enable;
461 }
462
463 static void igb_set_msglevel(struct net_device *netdev, u32 data)
464 {
465 struct igb_adapter *adapter = netdev_priv(netdev);
466 adapter->msg_enable = data;
467 }
468
469 static int igb_get_regs_len(struct net_device *netdev)
470 {
471 #define IGB_REGS_LEN 739
472 return IGB_REGS_LEN * sizeof(u32);
473 }
474
475 static void igb_get_regs(struct net_device *netdev,
476 struct ethtool_regs *regs, void *p)
477 {
478 struct igb_adapter *adapter = netdev_priv(netdev);
479 struct e1000_hw *hw = &adapter->hw;
480 u32 *regs_buff = p;
481 u8 i;
482
483 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
484
485 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
486
487 /* General Registers */
488 regs_buff[0] = rd32(E1000_CTRL);
489 regs_buff[1] = rd32(E1000_STATUS);
490 regs_buff[2] = rd32(E1000_CTRL_EXT);
491 regs_buff[3] = rd32(E1000_MDIC);
492 regs_buff[4] = rd32(E1000_SCTL);
493 regs_buff[5] = rd32(E1000_CONNSW);
494 regs_buff[6] = rd32(E1000_VET);
495 regs_buff[7] = rd32(E1000_LEDCTL);
496 regs_buff[8] = rd32(E1000_PBA);
497 regs_buff[9] = rd32(E1000_PBS);
498 regs_buff[10] = rd32(E1000_FRTIMER);
499 regs_buff[11] = rd32(E1000_TCPTIMER);
500
501 /* NVM Register */
502 regs_buff[12] = rd32(E1000_EECD);
503
504 /* Interrupt */
505 /* Reading EICS for EICR because they read the
506 * same but EICS does not clear on read
507 */
508 regs_buff[13] = rd32(E1000_EICS);
509 regs_buff[14] = rd32(E1000_EICS);
510 regs_buff[15] = rd32(E1000_EIMS);
511 regs_buff[16] = rd32(E1000_EIMC);
512 regs_buff[17] = rd32(E1000_EIAC);
513 regs_buff[18] = rd32(E1000_EIAM);
514 /* Reading ICS for ICR because they read the
515 * same but ICS does not clear on read
516 */
517 regs_buff[19] = rd32(E1000_ICS);
518 regs_buff[20] = rd32(E1000_ICS);
519 regs_buff[21] = rd32(E1000_IMS);
520 regs_buff[22] = rd32(E1000_IMC);
521 regs_buff[23] = rd32(E1000_IAC);
522 regs_buff[24] = rd32(E1000_IAM);
523 regs_buff[25] = rd32(E1000_IMIRVP);
524
525 /* Flow Control */
526 regs_buff[26] = rd32(E1000_FCAL);
527 regs_buff[27] = rd32(E1000_FCAH);
528 regs_buff[28] = rd32(E1000_FCTTV);
529 regs_buff[29] = rd32(E1000_FCRTL);
530 regs_buff[30] = rd32(E1000_FCRTH);
531 regs_buff[31] = rd32(E1000_FCRTV);
532
533 /* Receive */
534 regs_buff[32] = rd32(E1000_RCTL);
535 regs_buff[33] = rd32(E1000_RXCSUM);
536 regs_buff[34] = rd32(E1000_RLPML);
537 regs_buff[35] = rd32(E1000_RFCTL);
538 regs_buff[36] = rd32(E1000_MRQC);
539 regs_buff[37] = rd32(E1000_VT_CTL);
540
541 /* Transmit */
542 regs_buff[38] = rd32(E1000_TCTL);
543 regs_buff[39] = rd32(E1000_TCTL_EXT);
544 regs_buff[40] = rd32(E1000_TIPG);
545 regs_buff[41] = rd32(E1000_DTXCTL);
546
547 /* Wake Up */
548 regs_buff[42] = rd32(E1000_WUC);
549 regs_buff[43] = rd32(E1000_WUFC);
550 regs_buff[44] = rd32(E1000_WUS);
551 regs_buff[45] = rd32(E1000_IPAV);
552 regs_buff[46] = rd32(E1000_WUPL);
553
554 /* MAC */
555 regs_buff[47] = rd32(E1000_PCS_CFG0);
556 regs_buff[48] = rd32(E1000_PCS_LCTL);
557 regs_buff[49] = rd32(E1000_PCS_LSTAT);
558 regs_buff[50] = rd32(E1000_PCS_ANADV);
559 regs_buff[51] = rd32(E1000_PCS_LPAB);
560 regs_buff[52] = rd32(E1000_PCS_NPTX);
561 regs_buff[53] = rd32(E1000_PCS_LPABNP);
562
563 /* Statistics */
564 regs_buff[54] = adapter->stats.crcerrs;
565 regs_buff[55] = adapter->stats.algnerrc;
566 regs_buff[56] = adapter->stats.symerrs;
567 regs_buff[57] = adapter->stats.rxerrc;
568 regs_buff[58] = adapter->stats.mpc;
569 regs_buff[59] = adapter->stats.scc;
570 regs_buff[60] = adapter->stats.ecol;
571 regs_buff[61] = adapter->stats.mcc;
572 regs_buff[62] = adapter->stats.latecol;
573 regs_buff[63] = adapter->stats.colc;
574 regs_buff[64] = adapter->stats.dc;
575 regs_buff[65] = adapter->stats.tncrs;
576 regs_buff[66] = adapter->stats.sec;
577 regs_buff[67] = adapter->stats.htdpmc;
578 regs_buff[68] = adapter->stats.rlec;
579 regs_buff[69] = adapter->stats.xonrxc;
580 regs_buff[70] = adapter->stats.xontxc;
581 regs_buff[71] = adapter->stats.xoffrxc;
582 regs_buff[72] = adapter->stats.xofftxc;
583 regs_buff[73] = adapter->stats.fcruc;
584 regs_buff[74] = adapter->stats.prc64;
585 regs_buff[75] = adapter->stats.prc127;
586 regs_buff[76] = adapter->stats.prc255;
587 regs_buff[77] = adapter->stats.prc511;
588 regs_buff[78] = adapter->stats.prc1023;
589 regs_buff[79] = adapter->stats.prc1522;
590 regs_buff[80] = adapter->stats.gprc;
591 regs_buff[81] = adapter->stats.bprc;
592 regs_buff[82] = adapter->stats.mprc;
593 regs_buff[83] = adapter->stats.gptc;
594 regs_buff[84] = adapter->stats.gorc;
595 regs_buff[86] = adapter->stats.gotc;
596 regs_buff[88] = adapter->stats.rnbc;
597 regs_buff[89] = adapter->stats.ruc;
598 regs_buff[90] = adapter->stats.rfc;
599 regs_buff[91] = adapter->stats.roc;
600 regs_buff[92] = adapter->stats.rjc;
601 regs_buff[93] = adapter->stats.mgprc;
602 regs_buff[94] = adapter->stats.mgpdc;
603 regs_buff[95] = adapter->stats.mgptc;
604 regs_buff[96] = adapter->stats.tor;
605 regs_buff[98] = adapter->stats.tot;
606 regs_buff[100] = adapter->stats.tpr;
607 regs_buff[101] = adapter->stats.tpt;
608 regs_buff[102] = adapter->stats.ptc64;
609 regs_buff[103] = adapter->stats.ptc127;
610 regs_buff[104] = adapter->stats.ptc255;
611 regs_buff[105] = adapter->stats.ptc511;
612 regs_buff[106] = adapter->stats.ptc1023;
613 regs_buff[107] = adapter->stats.ptc1522;
614 regs_buff[108] = adapter->stats.mptc;
615 regs_buff[109] = adapter->stats.bptc;
616 regs_buff[110] = adapter->stats.tsctc;
617 regs_buff[111] = adapter->stats.iac;
618 regs_buff[112] = adapter->stats.rpthc;
619 regs_buff[113] = adapter->stats.hgptc;
620 regs_buff[114] = adapter->stats.hgorc;
621 regs_buff[116] = adapter->stats.hgotc;
622 regs_buff[118] = adapter->stats.lenerrs;
623 regs_buff[119] = adapter->stats.scvpc;
624 regs_buff[120] = adapter->stats.hrmpc;
625
626 for (i = 0; i < 4; i++)
627 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
628 for (i = 0; i < 4; i++)
629 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
630 for (i = 0; i < 4; i++)
631 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
632 for (i = 0; i < 4; i++)
633 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
634 for (i = 0; i < 4; i++)
635 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
636 for (i = 0; i < 4; i++)
637 regs_buff[141 + i] = rd32(E1000_RDH(i));
638 for (i = 0; i < 4; i++)
639 regs_buff[145 + i] = rd32(E1000_RDT(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
642
643 for (i = 0; i < 10; i++)
644 regs_buff[153 + i] = rd32(E1000_EITR(i));
645 for (i = 0; i < 8; i++)
646 regs_buff[163 + i] = rd32(E1000_IMIR(i));
647 for (i = 0; i < 8; i++)
648 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
649 for (i = 0; i < 16; i++)
650 regs_buff[179 + i] = rd32(E1000_RAL(i));
651 for (i = 0; i < 16; i++)
652 regs_buff[195 + i] = rd32(E1000_RAH(i));
653
654 for (i = 0; i < 4; i++)
655 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
656 for (i = 0; i < 4; i++)
657 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
658 for (i = 0; i < 4; i++)
659 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
660 for (i = 0; i < 4; i++)
661 regs_buff[223 + i] = rd32(E1000_TDH(i));
662 for (i = 0; i < 4; i++)
663 regs_buff[227 + i] = rd32(E1000_TDT(i));
664 for (i = 0; i < 4; i++)
665 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
666 for (i = 0; i < 4; i++)
667 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
668 for (i = 0; i < 4; i++)
669 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
670 for (i = 0; i < 4; i++)
671 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
672
673 for (i = 0; i < 4; i++)
674 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
675 for (i = 0; i < 4; i++)
676 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
677 for (i = 0; i < 32; i++)
678 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
679 for (i = 0; i < 128; i++)
680 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
681 for (i = 0; i < 128; i++)
682 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
683 for (i = 0; i < 4; i++)
684 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
685
686 regs_buff[547] = rd32(E1000_TDFH);
687 regs_buff[548] = rd32(E1000_TDFT);
688 regs_buff[549] = rd32(E1000_TDFHS);
689 regs_buff[550] = rd32(E1000_TDFPC);
690
691 if (hw->mac.type > e1000_82580) {
692 regs_buff[551] = adapter->stats.o2bgptc;
693 regs_buff[552] = adapter->stats.b2ospc;
694 regs_buff[553] = adapter->stats.o2bspc;
695 regs_buff[554] = adapter->stats.b2ogprc;
696 }
697
698 if (hw->mac.type != e1000_82576)
699 return;
700 for (i = 0; i < 12; i++)
701 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
702 for (i = 0; i < 4; i++)
703 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
704 for (i = 0; i < 12; i++)
705 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
706 for (i = 0; i < 12; i++)
707 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
708 for (i = 0; i < 12; i++)
709 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
710 for (i = 0; i < 12; i++)
711 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
712 for (i = 0; i < 12; i++)
713 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
714 for (i = 0; i < 12; i++)
715 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
716
717 for (i = 0; i < 12; i++)
718 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
719 for (i = 0; i < 12; i++)
720 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
721 for (i = 0; i < 12; i++)
722 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
723 for (i = 0; i < 12; i++)
724 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
725 for (i = 0; i < 12; i++)
726 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
727 for (i = 0; i < 12; i++)
728 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
729 for (i = 0; i < 12; i++)
730 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
731 for (i = 0; i < 12; i++)
732 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
733 }
734
735 static int igb_get_eeprom_len(struct net_device *netdev)
736 {
737 struct igb_adapter *adapter = netdev_priv(netdev);
738 return adapter->hw.nvm.word_size * 2;
739 }
740
741 static int igb_get_eeprom(struct net_device *netdev,
742 struct ethtool_eeprom *eeprom, u8 *bytes)
743 {
744 struct igb_adapter *adapter = netdev_priv(netdev);
745 struct e1000_hw *hw = &adapter->hw;
746 u16 *eeprom_buff;
747 int first_word, last_word;
748 int ret_val = 0;
749 u16 i;
750
751 if (eeprom->len == 0)
752 return -EINVAL;
753
754 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
755
756 first_word = eeprom->offset >> 1;
757 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
758
759 eeprom_buff = kmalloc(sizeof(u16) *
760 (last_word - first_word + 1), GFP_KERNEL);
761 if (!eeprom_buff)
762 return -ENOMEM;
763
764 if (hw->nvm.type == e1000_nvm_eeprom_spi)
765 ret_val = hw->nvm.ops.read(hw, first_word,
766 last_word - first_word + 1,
767 eeprom_buff);
768 else {
769 for (i = 0; i < last_word - first_word + 1; i++) {
770 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
771 &eeprom_buff[i]);
772 if (ret_val)
773 break;
774 }
775 }
776
777 /* Device's eeprom is always little-endian, word addressable */
778 for (i = 0; i < last_word - first_word + 1; i++)
779 le16_to_cpus(&eeprom_buff[i]);
780
781 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
782 eeprom->len);
783 kfree(eeprom_buff);
784
785 return ret_val;
786 }
787
788 static int igb_set_eeprom(struct net_device *netdev,
789 struct ethtool_eeprom *eeprom, u8 *bytes)
790 {
791 struct igb_adapter *adapter = netdev_priv(netdev);
792 struct e1000_hw *hw = &adapter->hw;
793 u16 *eeprom_buff;
794 void *ptr;
795 int max_len, first_word, last_word, ret_val = 0;
796 u16 i;
797
798 if (eeprom->len == 0)
799 return -EOPNOTSUPP;
800
801 if ((hw->mac.type >= e1000_i210) &&
802 !igb_get_flash_presence_i210(hw)) {
803 return -EOPNOTSUPP;
804 }
805
806 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
807 return -EFAULT;
808
809 max_len = hw->nvm.word_size * 2;
810
811 first_word = eeprom->offset >> 1;
812 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
813 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
814 if (!eeprom_buff)
815 return -ENOMEM;
816
817 ptr = (void *)eeprom_buff;
818
819 if (eeprom->offset & 1) {
820 /* need read/modify/write of first changed EEPROM word
821 * only the second byte of the word is being modified
822 */
823 ret_val = hw->nvm.ops.read(hw, first_word, 1,
824 &eeprom_buff[0]);
825 ptr++;
826 }
827 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
828 /* need read/modify/write of last changed EEPROM word
829 * only the first byte of the word is being modified
830 */
831 ret_val = hw->nvm.ops.read(hw, last_word, 1,
832 &eeprom_buff[last_word - first_word]);
833 }
834
835 /* Device's eeprom is always little-endian, word addressable */
836 for (i = 0; i < last_word - first_word + 1; i++)
837 le16_to_cpus(&eeprom_buff[i]);
838
839 memcpy(ptr, bytes, eeprom->len);
840
841 for (i = 0; i < last_word - first_word + 1; i++)
842 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
843
844 ret_val = hw->nvm.ops.write(hw, first_word,
845 last_word - first_word + 1, eeprom_buff);
846
847 /* Update the checksum if nvm write succeeded */
848 if (ret_val == 0)
849 hw->nvm.ops.update(hw);
850
851 igb_set_fw_version(adapter);
852 kfree(eeprom_buff);
853 return ret_val;
854 }
855
856 static void igb_get_drvinfo(struct net_device *netdev,
857 struct ethtool_drvinfo *drvinfo)
858 {
859 struct igb_adapter *adapter = netdev_priv(netdev);
860
861 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
862 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
863
864 /* EEPROM image version # is reported as firmware version # for
865 * 82575 controllers
866 */
867 strlcpy(drvinfo->fw_version, adapter->fw_version,
868 sizeof(drvinfo->fw_version));
869 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
870 sizeof(drvinfo->bus_info));
871
872 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;
873 }
874
875 static void igb_get_ringparam(struct net_device *netdev,
876 struct ethtool_ringparam *ring)
877 {
878 struct igb_adapter *adapter = netdev_priv(netdev);
879
880 ring->rx_max_pending = IGB_MAX_RXD;
881 ring->tx_max_pending = IGB_MAX_TXD;
882 ring->rx_pending = adapter->rx_ring_count;
883 ring->tx_pending = adapter->tx_ring_count;
884 }
885
886 static int igb_set_ringparam(struct net_device *netdev,
887 struct ethtool_ringparam *ring)
888 {
889 struct igb_adapter *adapter = netdev_priv(netdev);
890 struct igb_ring *temp_ring;
891 int i, err = 0;
892 u16 new_rx_count, new_tx_count;
893
894 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
895 return -EINVAL;
896
897 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
898 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
899 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
900
901 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
902 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
903 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
904
905 if ((new_tx_count == adapter->tx_ring_count) &&
906 (new_rx_count == adapter->rx_ring_count)) {
907 /* nothing to do */
908 return 0;
909 }
910
911 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
912 usleep_range(1000, 2000);
913
914 if (!netif_running(adapter->netdev)) {
915 for (i = 0; i < adapter->num_tx_queues; i++)
916 adapter->tx_ring[i]->count = new_tx_count;
917 for (i = 0; i < adapter->num_rx_queues; i++)
918 adapter->rx_ring[i]->count = new_rx_count;
919 adapter->tx_ring_count = new_tx_count;
920 adapter->rx_ring_count = new_rx_count;
921 goto clear_reset;
922 }
923
924 if (adapter->num_tx_queues > adapter->num_rx_queues)
925 temp_ring = vmalloc(adapter->num_tx_queues *
926 sizeof(struct igb_ring));
927 else
928 temp_ring = vmalloc(adapter->num_rx_queues *
929 sizeof(struct igb_ring));
930
931 if (!temp_ring) {
932 err = -ENOMEM;
933 goto clear_reset;
934 }
935
936 igb_down(adapter);
937
938 /* We can't just free everything and then setup again,
939 * because the ISRs in MSI-X mode get passed pointers
940 * to the Tx and Rx ring structs.
941 */
942 if (new_tx_count != adapter->tx_ring_count) {
943 for (i = 0; i < adapter->num_tx_queues; i++) {
944 memcpy(&temp_ring[i], adapter->tx_ring[i],
945 sizeof(struct igb_ring));
946
947 temp_ring[i].count = new_tx_count;
948 err = igb_setup_tx_resources(&temp_ring[i]);
949 if (err) {
950 while (i) {
951 i--;
952 igb_free_tx_resources(&temp_ring[i]);
953 }
954 goto err_setup;
955 }
956 }
957
958 for (i = 0; i < adapter->num_tx_queues; i++) {
959 igb_free_tx_resources(adapter->tx_ring[i]);
960
961 memcpy(adapter->tx_ring[i], &temp_ring[i],
962 sizeof(struct igb_ring));
963 }
964
965 adapter->tx_ring_count = new_tx_count;
966 }
967
968 if (new_rx_count != adapter->rx_ring_count) {
969 for (i = 0; i < adapter->num_rx_queues; i++) {
970 memcpy(&temp_ring[i], adapter->rx_ring[i],
971 sizeof(struct igb_ring));
972
973 temp_ring[i].count = new_rx_count;
974 err = igb_setup_rx_resources(&temp_ring[i]);
975 if (err) {
976 while (i) {
977 i--;
978 igb_free_rx_resources(&temp_ring[i]);
979 }
980 goto err_setup;
981 }
982
983 }
984
985 for (i = 0; i < adapter->num_rx_queues; i++) {
986 igb_free_rx_resources(adapter->rx_ring[i]);
987
988 memcpy(adapter->rx_ring[i], &temp_ring[i],
989 sizeof(struct igb_ring));
990 }
991
992 adapter->rx_ring_count = new_rx_count;
993 }
994 err_setup:
995 igb_up(adapter);
996 vfree(temp_ring);
997 clear_reset:
998 clear_bit(__IGB_RESETTING, &adapter->state);
999 return err;
1000 }
1001
1002 /* ethtool register test data */
1003 struct igb_reg_test {
1004 u16 reg;
1005 u16 reg_offset;
1006 u16 array_len;
1007 u16 test_type;
1008 u32 mask;
1009 u32 write;
1010 };
1011
1012 /* In the hardware, registers are laid out either singly, in arrays
1013 * spaced 0x100 bytes apart, or in contiguous tables. We assume
1014 * most tests take place on arrays or single registers (handled
1015 * as a single-element array) and special-case the tables.
1016 * Table tests are always pattern tests.
1017 *
1018 * We also make provision for some required setup steps by specifying
1019 * registers to be written without any read-back testing.
1020 */
1021
1022 #define PATTERN_TEST 1
1023 #define SET_READ_TEST 2
1024 #define WRITE_NO_TEST 3
1025 #define TABLE32_TEST 4
1026 #define TABLE64_TEST_LO 5
1027 #define TABLE64_TEST_HI 6
1028
1029 /* i210 reg test */
1030 static struct igb_reg_test reg_test_i210[] = {
1031 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1032 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1033 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1034 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1035 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1036 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1037 /* RDH is read-only for i210, only test RDT. */
1038 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1039 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1040 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1041 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1042 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1043 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1044 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1045 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1046 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1047 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1048 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1049 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1050 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1051 0xFFFFFFFF, 0xFFFFFFFF },
1052 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1053 0x900FFFFF, 0xFFFFFFFF },
1054 { E1000_MTA, 0, 128, TABLE32_TEST,
1055 0xFFFFFFFF, 0xFFFFFFFF },
1056 { 0, 0, 0, 0, 0 }
1057 };
1058
1059 /* i350 reg test */
1060 static struct igb_reg_test reg_test_i350[] = {
1061 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1063 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1064 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1065 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1066 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1067 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1068 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1069 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1070 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1071 /* RDH is read-only for i350, only test RDT. */
1072 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1073 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1074 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1075 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1076 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1077 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1078 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1079 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1080 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1081 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1083 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1084 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1085 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1086 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1087 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1088 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1089 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1090 0xFFFFFFFF, 0xFFFFFFFF },
1091 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1092 0xC3FFFFFF, 0xFFFFFFFF },
1093 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1094 0xFFFFFFFF, 0xFFFFFFFF },
1095 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1096 0xC3FFFFFF, 0xFFFFFFFF },
1097 { E1000_MTA, 0, 128, TABLE32_TEST,
1098 0xFFFFFFFF, 0xFFFFFFFF },
1099 { 0, 0, 0, 0 }
1100 };
1101
1102 /* 82580 reg test */
1103 static struct igb_reg_test reg_test_82580[] = {
1104 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1106 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1107 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1108 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1109 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1110 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1111 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1112 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1113 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1114 /* RDH is read-only for 82580, only test RDT. */
1115 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1116 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1117 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1118 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1119 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1120 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1121 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1122 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1123 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1124 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1125 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1126 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1127 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1128 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1129 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1130 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1131 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1132 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1133 0xFFFFFFFF, 0xFFFFFFFF },
1134 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1135 0x83FFFFFF, 0xFFFFFFFF },
1136 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1137 0xFFFFFFFF, 0xFFFFFFFF },
1138 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1139 0x83FFFFFF, 0xFFFFFFFF },
1140 { E1000_MTA, 0, 128, TABLE32_TEST,
1141 0xFFFFFFFF, 0xFFFFFFFF },
1142 { 0, 0, 0, 0 }
1143 };
1144
1145 /* 82576 reg test */
1146 static struct igb_reg_test reg_test_82576[] = {
1147 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1149 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1150 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1152 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1153 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1154 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1155 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1156 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1157 /* Enable all RX queues before testing. */
1158 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1159 E1000_RXDCTL_QUEUE_ENABLE },
1160 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1161 E1000_RXDCTL_QUEUE_ENABLE },
1162 /* RDH is read-only for 82576, only test RDT. */
1163 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1164 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1165 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1166 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1167 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1168 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1169 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1170 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1171 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1173 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1174 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1175 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1176 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1177 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1178 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1179 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1180 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1182 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1183 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1184 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1185 { 0, 0, 0, 0 }
1186 };
1187
1188 /* 82575 register test */
1189 static struct igb_reg_test reg_test_82575[] = {
1190 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1192 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1193 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1194 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1195 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1196 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1197 /* Enable all four RX queues before testing. */
1198 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1199 E1000_RXDCTL_QUEUE_ENABLE },
1200 /* RDH is read-only for 82575, only test RDT. */
1201 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1202 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1203 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1204 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1205 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1206 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1207 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1208 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1209 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1210 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1211 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1212 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1213 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1214 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1215 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1216 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1217 { 0, 0, 0, 0 }
1218 };
1219
1220 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1221 int reg, u32 mask, u32 write)
1222 {
1223 struct e1000_hw *hw = &adapter->hw;
1224 u32 pat, val;
1225 static const u32 _test[] = {
1226 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1227 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1228 wr32(reg, (_test[pat] & write));
1229 val = rd32(reg) & mask;
1230 if (val != (_test[pat] & write & mask)) {
1231 dev_err(&adapter->pdev->dev,
1232 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1233 reg, val, (_test[pat] & write & mask));
1234 *data = reg;
1235 return true;
1236 }
1237 }
1238
1239 return false;
1240 }
1241
1242 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1243 int reg, u32 mask, u32 write)
1244 {
1245 struct e1000_hw *hw = &adapter->hw;
1246 u32 val;
1247
1248 wr32(reg, write & mask);
1249 val = rd32(reg);
1250 if ((write & mask) != (val & mask)) {
1251 dev_err(&adapter->pdev->dev,
1252 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1253 reg, (val & mask), (write & mask));
1254 *data = reg;
1255 return true;
1256 }
1257
1258 return false;
1259 }
1260
1261 #define REG_PATTERN_TEST(reg, mask, write) \
1262 do { \
1263 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1264 return 1; \
1265 } while (0)
1266
1267 #define REG_SET_AND_CHECK(reg, mask, write) \
1268 do { \
1269 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1270 return 1; \
1271 } while (0)
1272
1273 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1274 {
1275 struct e1000_hw *hw = &adapter->hw;
1276 struct igb_reg_test *test;
1277 u32 value, before, after;
1278 u32 i, toggle;
1279
1280 switch (adapter->hw.mac.type) {
1281 case e1000_i350:
1282 case e1000_i354:
1283 test = reg_test_i350;
1284 toggle = 0x7FEFF3FF;
1285 break;
1286 case e1000_i210:
1287 case e1000_i211:
1288 test = reg_test_i210;
1289 toggle = 0x7FEFF3FF;
1290 break;
1291 case e1000_82580:
1292 test = reg_test_82580;
1293 toggle = 0x7FEFF3FF;
1294 break;
1295 case e1000_82576:
1296 test = reg_test_82576;
1297 toggle = 0x7FFFF3FF;
1298 break;
1299 default:
1300 test = reg_test_82575;
1301 toggle = 0x7FFFF3FF;
1302 break;
1303 }
1304
1305 /* Because the status register is such a special case,
1306 * we handle it separately from the rest of the register
1307 * tests. Some bits are read-only, some toggle, and some
1308 * are writable on newer MACs.
1309 */
1310 before = rd32(E1000_STATUS);
1311 value = (rd32(E1000_STATUS) & toggle);
1312 wr32(E1000_STATUS, toggle);
1313 after = rd32(E1000_STATUS) & toggle;
1314 if (value != after) {
1315 dev_err(&adapter->pdev->dev,
1316 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1317 after, value);
1318 *data = 1;
1319 return 1;
1320 }
1321 /* restore previous status */
1322 wr32(E1000_STATUS, before);
1323
1324 /* Perform the remainder of the register test, looping through
1325 * the test table until we either fail or reach the null entry.
1326 */
1327 while (test->reg) {
1328 for (i = 0; i < test->array_len; i++) {
1329 switch (test->test_type) {
1330 case PATTERN_TEST:
1331 REG_PATTERN_TEST(test->reg +
1332 (i * test->reg_offset),
1333 test->mask,
1334 test->write);
1335 break;
1336 case SET_READ_TEST:
1337 REG_SET_AND_CHECK(test->reg +
1338 (i * test->reg_offset),
1339 test->mask,
1340 test->write);
1341 break;
1342 case WRITE_NO_TEST:
1343 writel(test->write,
1344 (adapter->hw.hw_addr + test->reg)
1345 + (i * test->reg_offset));
1346 break;
1347 case TABLE32_TEST:
1348 REG_PATTERN_TEST(test->reg + (i * 4),
1349 test->mask,
1350 test->write);
1351 break;
1352 case TABLE64_TEST_LO:
1353 REG_PATTERN_TEST(test->reg + (i * 8),
1354 test->mask,
1355 test->write);
1356 break;
1357 case TABLE64_TEST_HI:
1358 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1359 test->mask,
1360 test->write);
1361 break;
1362 }
1363 }
1364 test++;
1365 }
1366
1367 *data = 0;
1368 return 0;
1369 }
1370
1371 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1372 {
1373 struct e1000_hw *hw = &adapter->hw;
1374
1375 *data = 0;
1376
1377 /* Validate eeprom on all parts but flashless */
1378 switch (hw->mac.type) {
1379 case e1000_i210:
1380 case e1000_i211:
1381 if (igb_get_flash_presence_i210(hw)) {
1382 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1383 *data = 2;
1384 }
1385 break;
1386 default:
1387 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1388 *data = 2;
1389 break;
1390 }
1391
1392 return *data;
1393 }
1394
1395 static irqreturn_t igb_test_intr(int irq, void *data)
1396 {
1397 struct igb_adapter *adapter = (struct igb_adapter *) data;
1398 struct e1000_hw *hw = &adapter->hw;
1399
1400 adapter->test_icr |= rd32(E1000_ICR);
1401
1402 return IRQ_HANDLED;
1403 }
1404
1405 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1406 {
1407 struct e1000_hw *hw = &adapter->hw;
1408 struct net_device *netdev = adapter->netdev;
1409 u32 mask, ics_mask, i = 0, shared_int = true;
1410 u32 irq = adapter->pdev->irq;
1411
1412 *data = 0;
1413
1414 /* Hook up test interrupt handler just for this test */
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 if (request_irq(adapter->msix_entries[0].vector,
1417 igb_test_intr, 0, netdev->name, adapter)) {
1418 *data = 1;
1419 return -1;
1420 }
1421 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1422 shared_int = false;
1423 if (request_irq(irq,
1424 igb_test_intr, 0, netdev->name, adapter)) {
1425 *data = 1;
1426 return -1;
1427 }
1428 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1429 netdev->name, adapter)) {
1430 shared_int = false;
1431 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1432 netdev->name, adapter)) {
1433 *data = 1;
1434 return -1;
1435 }
1436 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1437 (shared_int ? "shared" : "unshared"));
1438
1439 /* Disable all the interrupts */
1440 wr32(E1000_IMC, ~0);
1441 wrfl();
1442 usleep_range(10000, 11000);
1443
1444 /* Define all writable bits for ICS */
1445 switch (hw->mac.type) {
1446 case e1000_82575:
1447 ics_mask = 0x37F47EDD;
1448 break;
1449 case e1000_82576:
1450 ics_mask = 0x77D4FBFD;
1451 break;
1452 case e1000_82580:
1453 ics_mask = 0x77DCFED5;
1454 break;
1455 case e1000_i350:
1456 case e1000_i354:
1457 case e1000_i210:
1458 case e1000_i211:
1459 ics_mask = 0x77DCFED5;
1460 break;
1461 default:
1462 ics_mask = 0x7FFFFFFF;
1463 break;
1464 }
1465
1466 /* Test each interrupt */
1467 for (; i < 31; i++) {
1468 /* Interrupt to test */
1469 mask = BIT(i);
1470
1471 if (!(mask & ics_mask))
1472 continue;
1473
1474 if (!shared_int) {
1475 /* Disable the interrupt to be reported in
1476 * the cause register and then force the same
1477 * interrupt and see if one gets posted. If
1478 * an interrupt was posted to the bus, the
1479 * test failed.
1480 */
1481 adapter->test_icr = 0;
1482
1483 /* Flush any pending interrupts */
1484 wr32(E1000_ICR, ~0);
1485
1486 wr32(E1000_IMC, mask);
1487 wr32(E1000_ICS, mask);
1488 wrfl();
1489 usleep_range(10000, 11000);
1490
1491 if (adapter->test_icr & mask) {
1492 *data = 3;
1493 break;
1494 }
1495 }
1496
1497 /* Enable the interrupt to be reported in
1498 * the cause register and then force the same
1499 * interrupt and see if one gets posted. If
1500 * an interrupt was not posted to the bus, the
1501 * test failed.
1502 */
1503 adapter->test_icr = 0;
1504
1505 /* Flush any pending interrupts */
1506 wr32(E1000_ICR, ~0);
1507
1508 wr32(E1000_IMS, mask);
1509 wr32(E1000_ICS, mask);
1510 wrfl();
1511 usleep_range(10000, 11000);
1512
1513 if (!(adapter->test_icr & mask)) {
1514 *data = 4;
1515 break;
1516 }
1517
1518 if (!shared_int) {
1519 /* Disable the other interrupts to be reported in
1520 * the cause register and then force the other
1521 * interrupts and see if any get posted. If
1522 * an interrupt was posted to the bus, the
1523 * test failed.
1524 */
1525 adapter->test_icr = 0;
1526
1527 /* Flush any pending interrupts */
1528 wr32(E1000_ICR, ~0);
1529
1530 wr32(E1000_IMC, ~mask);
1531 wr32(E1000_ICS, ~mask);
1532 wrfl();
1533 usleep_range(10000, 11000);
1534
1535 if (adapter->test_icr & mask) {
1536 *data = 5;
1537 break;
1538 }
1539 }
1540 }
1541
1542 /* Disable all the interrupts */
1543 wr32(E1000_IMC, ~0);
1544 wrfl();
1545 usleep_range(10000, 11000);
1546
1547 /* Unhook test interrupt handler */
1548 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1549 free_irq(adapter->msix_entries[0].vector, adapter);
1550 else
1551 free_irq(irq, adapter);
1552
1553 return *data;
1554 }
1555
1556 static void igb_free_desc_rings(struct igb_adapter *adapter)
1557 {
1558 igb_free_tx_resources(&adapter->test_tx_ring);
1559 igb_free_rx_resources(&adapter->test_rx_ring);
1560 }
1561
1562 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1563 {
1564 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1565 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1566 struct e1000_hw *hw = &adapter->hw;
1567 int ret_val;
1568
1569 /* Setup Tx descriptor ring and Tx buffers */
1570 tx_ring->count = IGB_DEFAULT_TXD;
1571 tx_ring->dev = &adapter->pdev->dev;
1572 tx_ring->netdev = adapter->netdev;
1573 tx_ring->reg_idx = adapter->vfs_allocated_count;
1574
1575 if (igb_setup_tx_resources(tx_ring)) {
1576 ret_val = 1;
1577 goto err_nomem;
1578 }
1579
1580 igb_setup_tctl(adapter);
1581 igb_configure_tx_ring(adapter, tx_ring);
1582
1583 /* Setup Rx descriptor ring and Rx buffers */
1584 rx_ring->count = IGB_DEFAULT_RXD;
1585 rx_ring->dev = &adapter->pdev->dev;
1586 rx_ring->netdev = adapter->netdev;
1587 rx_ring->reg_idx = adapter->vfs_allocated_count;
1588
1589 if (igb_setup_rx_resources(rx_ring)) {
1590 ret_val = 3;
1591 goto err_nomem;
1592 }
1593
1594 /* set the default queue to queue 0 of PF */
1595 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1596
1597 /* enable receive ring */
1598 igb_setup_rctl(adapter);
1599 igb_configure_rx_ring(adapter, rx_ring);
1600
1601 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1602
1603 return 0;
1604
1605 err_nomem:
1606 igb_free_desc_rings(adapter);
1607 return ret_val;
1608 }
1609
1610 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1611 {
1612 struct e1000_hw *hw = &adapter->hw;
1613
1614 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1615 igb_write_phy_reg(hw, 29, 0x001F);
1616 igb_write_phy_reg(hw, 30, 0x8FFC);
1617 igb_write_phy_reg(hw, 29, 0x001A);
1618 igb_write_phy_reg(hw, 30, 0x8FF0);
1619 }
1620
1621 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1622 {
1623 struct e1000_hw *hw = &adapter->hw;
1624 u32 ctrl_reg = 0;
1625
1626 hw->mac.autoneg = false;
1627
1628 if (hw->phy.type == e1000_phy_m88) {
1629 if (hw->phy.id != I210_I_PHY_ID) {
1630 /* Auto-MDI/MDIX Off */
1631 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1632 /* reset to update Auto-MDI/MDIX */
1633 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1634 /* autoneg off */
1635 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1636 } else {
1637 /* force 1000, set loopback */
1638 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1639 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1640 }
1641 } else if (hw->phy.type == e1000_phy_82580) {
1642 /* enable MII loopback */
1643 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1644 }
1645
1646 /* add small delay to avoid loopback test failure */
1647 msleep(50);
1648
1649 /* force 1000, set loopback */
1650 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1651
1652 /* Now set up the MAC to the same speed/duplex as the PHY. */
1653 ctrl_reg = rd32(E1000_CTRL);
1654 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1655 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1656 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1657 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1658 E1000_CTRL_FD | /* Force Duplex to FULL */
1659 E1000_CTRL_SLU); /* Set link up enable bit */
1660
1661 if (hw->phy.type == e1000_phy_m88)
1662 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1663
1664 wr32(E1000_CTRL, ctrl_reg);
1665
1666 /* Disable the receiver on the PHY so when a cable is plugged in, the
1667 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1668 */
1669 if (hw->phy.type == e1000_phy_m88)
1670 igb_phy_disable_receiver(adapter);
1671
1672 mdelay(500);
1673 return 0;
1674 }
1675
1676 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1677 {
1678 return igb_integrated_phy_loopback(adapter);
1679 }
1680
1681 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1682 {
1683 struct e1000_hw *hw = &adapter->hw;
1684 u32 reg;
1685
1686 reg = rd32(E1000_CTRL_EXT);
1687
1688 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1689 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1690 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1691 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1693 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1694 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1695 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1696 /* Enable DH89xxCC MPHY for near end loopback */
1697 reg = rd32(E1000_MPHY_ADDR_CTL);
1698 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1699 E1000_MPHY_PCS_CLK_REG_OFFSET;
1700 wr32(E1000_MPHY_ADDR_CTL, reg);
1701
1702 reg = rd32(E1000_MPHY_DATA);
1703 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1704 wr32(E1000_MPHY_DATA, reg);
1705 }
1706
1707 reg = rd32(E1000_RCTL);
1708 reg |= E1000_RCTL_LBM_TCVR;
1709 wr32(E1000_RCTL, reg);
1710
1711 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1712
1713 reg = rd32(E1000_CTRL);
1714 reg &= ~(E1000_CTRL_RFCE |
1715 E1000_CTRL_TFCE |
1716 E1000_CTRL_LRST);
1717 reg |= E1000_CTRL_SLU |
1718 E1000_CTRL_FD;
1719 wr32(E1000_CTRL, reg);
1720
1721 /* Unset switch control to serdes energy detect */
1722 reg = rd32(E1000_CONNSW);
1723 reg &= ~E1000_CONNSW_ENRGSRC;
1724 wr32(E1000_CONNSW, reg);
1725
1726 /* Unset sigdetect for SERDES loopback on
1727 * 82580 and newer devices.
1728 */
1729 if (hw->mac.type >= e1000_82580) {
1730 reg = rd32(E1000_PCS_CFG0);
1731 reg |= E1000_PCS_CFG_IGN_SD;
1732 wr32(E1000_PCS_CFG0, reg);
1733 }
1734
1735 /* Set PCS register for forced speed */
1736 reg = rd32(E1000_PCS_LCTL);
1737 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1738 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1739 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1740 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1741 E1000_PCS_LCTL_FSD | /* Force Speed */
1742 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1743 wr32(E1000_PCS_LCTL, reg);
1744
1745 return 0;
1746 }
1747
1748 return igb_set_phy_loopback(adapter);
1749 }
1750
1751 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1752 {
1753 struct e1000_hw *hw = &adapter->hw;
1754 u32 rctl;
1755 u16 phy_reg;
1756
1757 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1758 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1759 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1760 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1761 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1762 u32 reg;
1763
1764 /* Disable near end loopback on DH89xxCC */
1765 reg = rd32(E1000_MPHY_ADDR_CTL);
1766 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1767 E1000_MPHY_PCS_CLK_REG_OFFSET;
1768 wr32(E1000_MPHY_ADDR_CTL, reg);
1769
1770 reg = rd32(E1000_MPHY_DATA);
1771 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1772 wr32(E1000_MPHY_DATA, reg);
1773 }
1774
1775 rctl = rd32(E1000_RCTL);
1776 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1777 wr32(E1000_RCTL, rctl);
1778
1779 hw->mac.autoneg = true;
1780 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1781 if (phy_reg & MII_CR_LOOPBACK) {
1782 phy_reg &= ~MII_CR_LOOPBACK;
1783 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1784 igb_phy_sw_reset(hw);
1785 }
1786 }
1787
1788 static void igb_create_lbtest_frame(struct sk_buff *skb,
1789 unsigned int frame_size)
1790 {
1791 memset(skb->data, 0xFF, frame_size);
1792 frame_size /= 2;
1793 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1794 memset(&skb->data[frame_size + 10], 0xBE, 1);
1795 memset(&skb->data[frame_size + 12], 0xAF, 1);
1796 }
1797
1798 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1799 unsigned int frame_size)
1800 {
1801 unsigned char *data;
1802 bool match = true;
1803
1804 frame_size >>= 1;
1805
1806 data = kmap(rx_buffer->page);
1807
1808 if (data[3] != 0xFF ||
1809 data[frame_size + 10] != 0xBE ||
1810 data[frame_size + 12] != 0xAF)
1811 match = false;
1812
1813 kunmap(rx_buffer->page);
1814
1815 return match;
1816 }
1817
1818 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1819 struct igb_ring *tx_ring,
1820 unsigned int size)
1821 {
1822 union e1000_adv_rx_desc *rx_desc;
1823 struct igb_rx_buffer *rx_buffer_info;
1824 struct igb_tx_buffer *tx_buffer_info;
1825 u16 rx_ntc, tx_ntc, count = 0;
1826
1827 /* initialize next to clean and descriptor values */
1828 rx_ntc = rx_ring->next_to_clean;
1829 tx_ntc = tx_ring->next_to_clean;
1830 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1831
1832 while (rx_desc->wb.upper.length) {
1833 /* check Rx buffer */
1834 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1835
1836 /* sync Rx buffer for CPU read */
1837 dma_sync_single_for_cpu(rx_ring->dev,
1838 rx_buffer_info->dma,
1839 size,
1840 DMA_FROM_DEVICE);
1841
1842 /* verify contents of skb */
1843 if (igb_check_lbtest_frame(rx_buffer_info, size))
1844 count++;
1845
1846 /* sync Rx buffer for device write */
1847 dma_sync_single_for_device(rx_ring->dev,
1848 rx_buffer_info->dma,
1849 size,
1850 DMA_FROM_DEVICE);
1851
1852 /* unmap buffer on Tx side */
1853 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1854
1855 /* Free all the Tx ring sk_buffs */
1856 dev_kfree_skb_any(tx_buffer_info->skb);
1857
1858 /* unmap skb header data */
1859 dma_unmap_single(tx_ring->dev,
1860 dma_unmap_addr(tx_buffer_info, dma),
1861 dma_unmap_len(tx_buffer_info, len),
1862 DMA_TO_DEVICE);
1863 dma_unmap_len_set(tx_buffer_info, len, 0);
1864
1865 /* increment Rx/Tx next to clean counters */
1866 rx_ntc++;
1867 if (rx_ntc == rx_ring->count)
1868 rx_ntc = 0;
1869 tx_ntc++;
1870 if (tx_ntc == tx_ring->count)
1871 tx_ntc = 0;
1872
1873 /* fetch next descriptor */
1874 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1875 }
1876
1877 netdev_tx_reset_queue(txring_txq(tx_ring));
1878
1879 /* re-map buffers to ring, store next to clean values */
1880 igb_alloc_rx_buffers(rx_ring, count);
1881 rx_ring->next_to_clean = rx_ntc;
1882 tx_ring->next_to_clean = tx_ntc;
1883
1884 return count;
1885 }
1886
1887 static int igb_run_loopback_test(struct igb_adapter *adapter)
1888 {
1889 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1890 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1891 u16 i, j, lc, good_cnt;
1892 int ret_val = 0;
1893 unsigned int size = IGB_RX_HDR_LEN;
1894 netdev_tx_t tx_ret_val;
1895 struct sk_buff *skb;
1896
1897 /* allocate test skb */
1898 skb = alloc_skb(size, GFP_KERNEL);
1899 if (!skb)
1900 return 11;
1901
1902 /* place data into test skb */
1903 igb_create_lbtest_frame(skb, size);
1904 skb_put(skb, size);
1905
1906 /* Calculate the loop count based on the largest descriptor ring
1907 * The idea is to wrap the largest ring a number of times using 64
1908 * send/receive pairs during each loop
1909 */
1910
1911 if (rx_ring->count <= tx_ring->count)
1912 lc = ((tx_ring->count / 64) * 2) + 1;
1913 else
1914 lc = ((rx_ring->count / 64) * 2) + 1;
1915
1916 for (j = 0; j <= lc; j++) { /* loop count loop */
1917 /* reset count of good packets */
1918 good_cnt = 0;
1919
1920 /* place 64 packets on the transmit queue*/
1921 for (i = 0; i < 64; i++) {
1922 skb_get(skb);
1923 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1924 if (tx_ret_val == NETDEV_TX_OK)
1925 good_cnt++;
1926 }
1927
1928 if (good_cnt != 64) {
1929 ret_val = 12;
1930 break;
1931 }
1932
1933 /* allow 200 milliseconds for packets to go from Tx to Rx */
1934 msleep(200);
1935
1936 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1937 if (good_cnt != 64) {
1938 ret_val = 13;
1939 break;
1940 }
1941 } /* end loop count loop */
1942
1943 /* free the original skb */
1944 kfree_skb(skb);
1945
1946 return ret_val;
1947 }
1948
1949 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1950 {
1951 /* PHY loopback cannot be performed if SoL/IDER
1952 * sessions are active
1953 */
1954 if (igb_check_reset_block(&adapter->hw)) {
1955 dev_err(&adapter->pdev->dev,
1956 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1957 *data = 0;
1958 goto out;
1959 }
1960
1961 if (adapter->hw.mac.type == e1000_i354) {
1962 dev_info(&adapter->pdev->dev,
1963 "Loopback test not supported on i354.\n");
1964 *data = 0;
1965 goto out;
1966 }
1967 *data = igb_setup_desc_rings(adapter);
1968 if (*data)
1969 goto out;
1970 *data = igb_setup_loopback_test(adapter);
1971 if (*data)
1972 goto err_loopback;
1973 *data = igb_run_loopback_test(adapter);
1974 igb_loopback_cleanup(adapter);
1975
1976 err_loopback:
1977 igb_free_desc_rings(adapter);
1978 out:
1979 return *data;
1980 }
1981
1982 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1983 {
1984 struct e1000_hw *hw = &adapter->hw;
1985 *data = 0;
1986 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1987 int i = 0;
1988
1989 hw->mac.serdes_has_link = false;
1990
1991 /* On some blade server designs, link establishment
1992 * could take as long as 2-3 minutes
1993 */
1994 do {
1995 hw->mac.ops.check_for_link(&adapter->hw);
1996 if (hw->mac.serdes_has_link)
1997 return *data;
1998 msleep(20);
1999 } while (i++ < 3750);
2000
2001 *data = 1;
2002 } else {
2003 hw->mac.ops.check_for_link(&adapter->hw);
2004 if (hw->mac.autoneg)
2005 msleep(5000);
2006
2007 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
2008 *data = 1;
2009 }
2010 return *data;
2011 }
2012
2013 static void igb_diag_test(struct net_device *netdev,
2014 struct ethtool_test *eth_test, u64 *data)
2015 {
2016 struct igb_adapter *adapter = netdev_priv(netdev);
2017 u16 autoneg_advertised;
2018 u8 forced_speed_duplex, autoneg;
2019 bool if_running = netif_running(netdev);
2020
2021 set_bit(__IGB_TESTING, &adapter->state);
2022
2023 /* can't do offline tests on media switching devices */
2024 if (adapter->hw.dev_spec._82575.mas_capable)
2025 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
2026 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2027 /* Offline tests */
2028
2029 /* save speed, duplex, autoneg settings */
2030 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2031 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2032 autoneg = adapter->hw.mac.autoneg;
2033
2034 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2035
2036 /* power up link for link test */
2037 igb_power_up_link(adapter);
2038
2039 /* Link test performed before hardware reset so autoneg doesn't
2040 * interfere with test result
2041 */
2042 if (igb_link_test(adapter, &data[TEST_LINK]))
2043 eth_test->flags |= ETH_TEST_FL_FAILED;
2044
2045 if (if_running)
2046 /* indicate we're in test mode */
2047 igb_close(netdev);
2048 else
2049 igb_reset(adapter);
2050
2051 if (igb_reg_test(adapter, &data[TEST_REG]))
2052 eth_test->flags |= ETH_TEST_FL_FAILED;
2053
2054 igb_reset(adapter);
2055 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
2056 eth_test->flags |= ETH_TEST_FL_FAILED;
2057
2058 igb_reset(adapter);
2059 if (igb_intr_test(adapter, &data[TEST_IRQ]))
2060 eth_test->flags |= ETH_TEST_FL_FAILED;
2061
2062 igb_reset(adapter);
2063 /* power up link for loopback test */
2064 igb_power_up_link(adapter);
2065 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
2066 eth_test->flags |= ETH_TEST_FL_FAILED;
2067
2068 /* restore speed, duplex, autoneg settings */
2069 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2070 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2071 adapter->hw.mac.autoneg = autoneg;
2072
2073 /* force this routine to wait until autoneg complete/timeout */
2074 adapter->hw.phy.autoneg_wait_to_complete = true;
2075 igb_reset(adapter);
2076 adapter->hw.phy.autoneg_wait_to_complete = false;
2077
2078 clear_bit(__IGB_TESTING, &adapter->state);
2079 if (if_running)
2080 igb_open(netdev);
2081 } else {
2082 dev_info(&adapter->pdev->dev, "online testing starting\n");
2083
2084 /* PHY is powered down when interface is down */
2085 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
2086 eth_test->flags |= ETH_TEST_FL_FAILED;
2087 else
2088 data[TEST_LINK] = 0;
2089
2090 /* Online tests aren't run; pass by default */
2091 data[TEST_REG] = 0;
2092 data[TEST_EEP] = 0;
2093 data[TEST_IRQ] = 0;
2094 data[TEST_LOOP] = 0;
2095
2096 clear_bit(__IGB_TESTING, &adapter->state);
2097 }
2098 msleep_interruptible(4 * 1000);
2099 }
2100
2101 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2102 {
2103 struct igb_adapter *adapter = netdev_priv(netdev);
2104
2105 wol->wolopts = 0;
2106
2107 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2108 return;
2109
2110 wol->supported = WAKE_UCAST | WAKE_MCAST |
2111 WAKE_BCAST | WAKE_MAGIC |
2112 WAKE_PHY;
2113
2114 /* apply any specific unsupported masks here */
2115 switch (adapter->hw.device_id) {
2116 default:
2117 break;
2118 }
2119
2120 if (adapter->wol & E1000_WUFC_EX)
2121 wol->wolopts |= WAKE_UCAST;
2122 if (adapter->wol & E1000_WUFC_MC)
2123 wol->wolopts |= WAKE_MCAST;
2124 if (adapter->wol & E1000_WUFC_BC)
2125 wol->wolopts |= WAKE_BCAST;
2126 if (adapter->wol & E1000_WUFC_MAG)
2127 wol->wolopts |= WAKE_MAGIC;
2128 if (adapter->wol & E1000_WUFC_LNKC)
2129 wol->wolopts |= WAKE_PHY;
2130 }
2131
2132 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2133 {
2134 struct igb_adapter *adapter = netdev_priv(netdev);
2135
2136 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2137 return -EOPNOTSUPP;
2138
2139 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2140 return wol->wolopts ? -EOPNOTSUPP : 0;
2141
2142 /* these settings will always override what we currently have */
2143 adapter->wol = 0;
2144
2145 if (wol->wolopts & WAKE_UCAST)
2146 adapter->wol |= E1000_WUFC_EX;
2147 if (wol->wolopts & WAKE_MCAST)
2148 adapter->wol |= E1000_WUFC_MC;
2149 if (wol->wolopts & WAKE_BCAST)
2150 adapter->wol |= E1000_WUFC_BC;
2151 if (wol->wolopts & WAKE_MAGIC)
2152 adapter->wol |= E1000_WUFC_MAG;
2153 if (wol->wolopts & WAKE_PHY)
2154 adapter->wol |= E1000_WUFC_LNKC;
2155 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2156
2157 return 0;
2158 }
2159
2160 /* bit defines for adapter->led_status */
2161 #define IGB_LED_ON 0
2162
2163 static int igb_set_phys_id(struct net_device *netdev,
2164 enum ethtool_phys_id_state state)
2165 {
2166 struct igb_adapter *adapter = netdev_priv(netdev);
2167 struct e1000_hw *hw = &adapter->hw;
2168
2169 switch (state) {
2170 case ETHTOOL_ID_ACTIVE:
2171 igb_blink_led(hw);
2172 return 2;
2173 case ETHTOOL_ID_ON:
2174 igb_blink_led(hw);
2175 break;
2176 case ETHTOOL_ID_OFF:
2177 igb_led_off(hw);
2178 break;
2179 case ETHTOOL_ID_INACTIVE:
2180 igb_led_off(hw);
2181 clear_bit(IGB_LED_ON, &adapter->led_status);
2182 igb_cleanup_led(hw);
2183 break;
2184 }
2185
2186 return 0;
2187 }
2188
2189 static int igb_set_coalesce(struct net_device *netdev,
2190 struct ethtool_coalesce *ec)
2191 {
2192 struct igb_adapter *adapter = netdev_priv(netdev);
2193 int i;
2194
2195 if (ec->rx_max_coalesced_frames ||
2196 ec->rx_coalesce_usecs_irq ||
2197 ec->rx_max_coalesced_frames_irq ||
2198 ec->tx_max_coalesced_frames ||
2199 ec->tx_coalesce_usecs_irq ||
2200 ec->stats_block_coalesce_usecs ||
2201 ec->use_adaptive_rx_coalesce ||
2202 ec->use_adaptive_tx_coalesce ||
2203 ec->pkt_rate_low ||
2204 ec->rx_coalesce_usecs_low ||
2205 ec->rx_max_coalesced_frames_low ||
2206 ec->tx_coalesce_usecs_low ||
2207 ec->tx_max_coalesced_frames_low ||
2208 ec->pkt_rate_high ||
2209 ec->rx_coalesce_usecs_high ||
2210 ec->rx_max_coalesced_frames_high ||
2211 ec->tx_coalesce_usecs_high ||
2212 ec->tx_max_coalesced_frames_high ||
2213 ec->rate_sample_interval)
2214 return -ENOTSUPP;
2215
2216 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2217 ((ec->rx_coalesce_usecs > 3) &&
2218 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2219 (ec->rx_coalesce_usecs == 2))
2220 return -EINVAL;
2221
2222 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2223 ((ec->tx_coalesce_usecs > 3) &&
2224 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2225 (ec->tx_coalesce_usecs == 2))
2226 return -EINVAL;
2227
2228 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2229 return -EINVAL;
2230
2231 /* If ITR is disabled, disable DMAC */
2232 if (ec->rx_coalesce_usecs == 0) {
2233 if (adapter->flags & IGB_FLAG_DMAC)
2234 adapter->flags &= ~IGB_FLAG_DMAC;
2235 }
2236
2237 /* convert to rate of irq's per second */
2238 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2239 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2240 else
2241 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2242
2243 /* convert to rate of irq's per second */
2244 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2245 adapter->tx_itr_setting = adapter->rx_itr_setting;
2246 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2247 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2248 else
2249 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2250
2251 for (i = 0; i < adapter->num_q_vectors; i++) {
2252 struct igb_q_vector *q_vector = adapter->q_vector[i];
2253 q_vector->tx.work_limit = adapter->tx_work_limit;
2254 if (q_vector->rx.ring)
2255 q_vector->itr_val = adapter->rx_itr_setting;
2256 else
2257 q_vector->itr_val = adapter->tx_itr_setting;
2258 if (q_vector->itr_val && q_vector->itr_val <= 3)
2259 q_vector->itr_val = IGB_START_ITR;
2260 q_vector->set_itr = 1;
2261 }
2262
2263 return 0;
2264 }
2265
2266 static int igb_get_coalesce(struct net_device *netdev,
2267 struct ethtool_coalesce *ec)
2268 {
2269 struct igb_adapter *adapter = netdev_priv(netdev);
2270
2271 if (adapter->rx_itr_setting <= 3)
2272 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2273 else
2274 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2275
2276 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2277 if (adapter->tx_itr_setting <= 3)
2278 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2279 else
2280 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2281 }
2282
2283 return 0;
2284 }
2285
2286 static int igb_nway_reset(struct net_device *netdev)
2287 {
2288 struct igb_adapter *adapter = netdev_priv(netdev);
2289 if (netif_running(netdev))
2290 igb_reinit_locked(adapter);
2291 return 0;
2292 }
2293
2294 static int igb_get_sset_count(struct net_device *netdev, int sset)
2295 {
2296 switch (sset) {
2297 case ETH_SS_STATS:
2298 return IGB_STATS_LEN;
2299 case ETH_SS_TEST:
2300 return IGB_TEST_LEN;
2301 case ETH_SS_PRIV_FLAGS:
2302 return IGB_PRIV_FLAGS_STR_LEN;
2303 default:
2304 return -ENOTSUPP;
2305 }
2306 }
2307
2308 static void igb_get_ethtool_stats(struct net_device *netdev,
2309 struct ethtool_stats *stats, u64 *data)
2310 {
2311 struct igb_adapter *adapter = netdev_priv(netdev);
2312 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2313 unsigned int start;
2314 struct igb_ring *ring;
2315 int i, j;
2316 char *p;
2317
2318 spin_lock(&adapter->stats64_lock);
2319 igb_update_stats(adapter);
2320
2321 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2322 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2323 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2324 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2325 }
2326 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2327 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2328 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2329 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2330 }
2331 for (j = 0; j < adapter->num_tx_queues; j++) {
2332 u64 restart2;
2333
2334 ring = adapter->tx_ring[j];
2335 do {
2336 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2337 data[i] = ring->tx_stats.packets;
2338 data[i+1] = ring->tx_stats.bytes;
2339 data[i+2] = ring->tx_stats.restart_queue;
2340 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2341 do {
2342 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2343 restart2 = ring->tx_stats.restart_queue2;
2344 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2345 data[i+2] += restart2;
2346
2347 i += IGB_TX_QUEUE_STATS_LEN;
2348 }
2349 for (j = 0; j < adapter->num_rx_queues; j++) {
2350 ring = adapter->rx_ring[j];
2351 do {
2352 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2353 data[i] = ring->rx_stats.packets;
2354 data[i+1] = ring->rx_stats.bytes;
2355 data[i+2] = ring->rx_stats.drops;
2356 data[i+3] = ring->rx_stats.csum_err;
2357 data[i+4] = ring->rx_stats.alloc_failed;
2358 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2359 i += IGB_RX_QUEUE_STATS_LEN;
2360 }
2361 spin_unlock(&adapter->stats64_lock);
2362 }
2363
2364 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2365 {
2366 struct igb_adapter *adapter = netdev_priv(netdev);
2367 u8 *p = data;
2368 int i;
2369
2370 switch (stringset) {
2371 case ETH_SS_TEST:
2372 memcpy(data, *igb_gstrings_test,
2373 IGB_TEST_LEN*ETH_GSTRING_LEN);
2374 break;
2375 case ETH_SS_STATS:
2376 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2377 memcpy(p, igb_gstrings_stats[i].stat_string,
2378 ETH_GSTRING_LEN);
2379 p += ETH_GSTRING_LEN;
2380 }
2381 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2382 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2383 ETH_GSTRING_LEN);
2384 p += ETH_GSTRING_LEN;
2385 }
2386 for (i = 0; i < adapter->num_tx_queues; i++) {
2387 sprintf(p, "tx_queue_%u_packets", i);
2388 p += ETH_GSTRING_LEN;
2389 sprintf(p, "tx_queue_%u_bytes", i);
2390 p += ETH_GSTRING_LEN;
2391 sprintf(p, "tx_queue_%u_restart", i);
2392 p += ETH_GSTRING_LEN;
2393 }
2394 for (i = 0; i < adapter->num_rx_queues; i++) {
2395 sprintf(p, "rx_queue_%u_packets", i);
2396 p += ETH_GSTRING_LEN;
2397 sprintf(p, "rx_queue_%u_bytes", i);
2398 p += ETH_GSTRING_LEN;
2399 sprintf(p, "rx_queue_%u_drops", i);
2400 p += ETH_GSTRING_LEN;
2401 sprintf(p, "rx_queue_%u_csum_err", i);
2402 p += ETH_GSTRING_LEN;
2403 sprintf(p, "rx_queue_%u_alloc_failed", i);
2404 p += ETH_GSTRING_LEN;
2405 }
2406 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2407 break;
2408 case ETH_SS_PRIV_FLAGS:
2409 memcpy(data, igb_priv_flags_strings,
2410 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
2411 break;
2412 }
2413 }
2414
2415 static int igb_get_ts_info(struct net_device *dev,
2416 struct ethtool_ts_info *info)
2417 {
2418 struct igb_adapter *adapter = netdev_priv(dev);
2419
2420 if (adapter->ptp_clock)
2421 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2422 else
2423 info->phc_index = -1;
2424
2425 switch (adapter->hw.mac.type) {
2426 case e1000_82575:
2427 info->so_timestamping =
2428 SOF_TIMESTAMPING_TX_SOFTWARE |
2429 SOF_TIMESTAMPING_RX_SOFTWARE |
2430 SOF_TIMESTAMPING_SOFTWARE;
2431 return 0;
2432 case e1000_82576:
2433 case e1000_82580:
2434 case e1000_i350:
2435 case e1000_i354:
2436 case e1000_i210:
2437 case e1000_i211:
2438 info->so_timestamping =
2439 SOF_TIMESTAMPING_TX_SOFTWARE |
2440 SOF_TIMESTAMPING_RX_SOFTWARE |
2441 SOF_TIMESTAMPING_SOFTWARE |
2442 SOF_TIMESTAMPING_TX_HARDWARE |
2443 SOF_TIMESTAMPING_RX_HARDWARE |
2444 SOF_TIMESTAMPING_RAW_HARDWARE;
2445
2446 info->tx_types =
2447 BIT(HWTSTAMP_TX_OFF) |
2448 BIT(HWTSTAMP_TX_ON);
2449
2450 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2451
2452 /* 82576 does not support timestamping all packets. */
2453 if (adapter->hw.mac.type >= e1000_82580)
2454 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2455 else
2456 info->rx_filters |=
2457 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2458 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2459 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2460
2461 return 0;
2462 default:
2463 return -EOPNOTSUPP;
2464 }
2465 }
2466
2467 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2468 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2469 struct ethtool_rxnfc *cmd)
2470 {
2471 struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2472 struct igb_nfc_filter *rule = NULL;
2473
2474 /* report total rule count */
2475 cmd->data = IGB_MAX_RXNFC_FILTERS;
2476
2477 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2478 if (fsp->location <= rule->sw_idx)
2479 break;
2480 }
2481
2482 if (!rule || fsp->location != rule->sw_idx)
2483 return -EINVAL;
2484
2485 if (rule->filter.match_flags) {
2486 fsp->flow_type = ETHER_FLOW;
2487 fsp->ring_cookie = rule->action;
2488 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2489 fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2490 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2491 }
2492 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2493 fsp->flow_type |= FLOW_EXT;
2494 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2495 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2496 }
2497 return 0;
2498 }
2499 return -EINVAL;
2500 }
2501
2502 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2503 struct ethtool_rxnfc *cmd,
2504 u32 *rule_locs)
2505 {
2506 struct igb_nfc_filter *rule;
2507 int cnt = 0;
2508
2509 /* report total rule count */
2510 cmd->data = IGB_MAX_RXNFC_FILTERS;
2511
2512 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2513 if (cnt == cmd->rule_cnt)
2514 return -EMSGSIZE;
2515 rule_locs[cnt] = rule->sw_idx;
2516 cnt++;
2517 }
2518
2519 cmd->rule_cnt = cnt;
2520
2521 return 0;
2522 }
2523
2524 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2525 struct ethtool_rxnfc *cmd)
2526 {
2527 cmd->data = 0;
2528
2529 /* Report default options for RSS on igb */
2530 switch (cmd->flow_type) {
2531 case TCP_V4_FLOW:
2532 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2533 /* Fall through */
2534 case UDP_V4_FLOW:
2535 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2536 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2537 /* Fall through */
2538 case SCTP_V4_FLOW:
2539 case AH_ESP_V4_FLOW:
2540 case AH_V4_FLOW:
2541 case ESP_V4_FLOW:
2542 case IPV4_FLOW:
2543 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2544 break;
2545 case TCP_V6_FLOW:
2546 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2547 /* Fall through */
2548 case UDP_V6_FLOW:
2549 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2550 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2551 /* Fall through */
2552 case SCTP_V6_FLOW:
2553 case AH_ESP_V6_FLOW:
2554 case AH_V6_FLOW:
2555 case ESP_V6_FLOW:
2556 case IPV6_FLOW:
2557 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2558 break;
2559 default:
2560 return -EINVAL;
2561 }
2562
2563 return 0;
2564 }
2565
2566 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2567 u32 *rule_locs)
2568 {
2569 struct igb_adapter *adapter = netdev_priv(dev);
2570 int ret = -EOPNOTSUPP;
2571
2572 switch (cmd->cmd) {
2573 case ETHTOOL_GRXRINGS:
2574 cmd->data = adapter->num_rx_queues;
2575 ret = 0;
2576 break;
2577 case ETHTOOL_GRXCLSRLCNT:
2578 cmd->rule_cnt = adapter->nfc_filter_count;
2579 ret = 0;
2580 break;
2581 case ETHTOOL_GRXCLSRULE:
2582 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2583 break;
2584 case ETHTOOL_GRXCLSRLALL:
2585 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2586 break;
2587 case ETHTOOL_GRXFH:
2588 ret = igb_get_rss_hash_opts(adapter, cmd);
2589 break;
2590 default:
2591 break;
2592 }
2593
2594 return ret;
2595 }
2596
2597 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2598 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2599 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2600 struct ethtool_rxnfc *nfc)
2601 {
2602 u32 flags = adapter->flags;
2603
2604 /* RSS does not support anything other than hashing
2605 * to queues on src and dst IPs and ports
2606 */
2607 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2608 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2609 return -EINVAL;
2610
2611 switch (nfc->flow_type) {
2612 case TCP_V4_FLOW:
2613 case TCP_V6_FLOW:
2614 if (!(nfc->data & RXH_IP_SRC) ||
2615 !(nfc->data & RXH_IP_DST) ||
2616 !(nfc->data & RXH_L4_B_0_1) ||
2617 !(nfc->data & RXH_L4_B_2_3))
2618 return -EINVAL;
2619 break;
2620 case UDP_V4_FLOW:
2621 if (!(nfc->data & RXH_IP_SRC) ||
2622 !(nfc->data & RXH_IP_DST))
2623 return -EINVAL;
2624 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2625 case 0:
2626 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2627 break;
2628 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2629 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2630 break;
2631 default:
2632 return -EINVAL;
2633 }
2634 break;
2635 case UDP_V6_FLOW:
2636 if (!(nfc->data & RXH_IP_SRC) ||
2637 !(nfc->data & RXH_IP_DST))
2638 return -EINVAL;
2639 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2640 case 0:
2641 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2642 break;
2643 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2644 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649 break;
2650 case AH_ESP_V4_FLOW:
2651 case AH_V4_FLOW:
2652 case ESP_V4_FLOW:
2653 case SCTP_V4_FLOW:
2654 case AH_ESP_V6_FLOW:
2655 case AH_V6_FLOW:
2656 case ESP_V6_FLOW:
2657 case SCTP_V6_FLOW:
2658 if (!(nfc->data & RXH_IP_SRC) ||
2659 !(nfc->data & RXH_IP_DST) ||
2660 (nfc->data & RXH_L4_B_0_1) ||
2661 (nfc->data & RXH_L4_B_2_3))
2662 return -EINVAL;
2663 break;
2664 default:
2665 return -EINVAL;
2666 }
2667
2668 /* if we changed something we need to update flags */
2669 if (flags != adapter->flags) {
2670 struct e1000_hw *hw = &adapter->hw;
2671 u32 mrqc = rd32(E1000_MRQC);
2672
2673 if ((flags & UDP_RSS_FLAGS) &&
2674 !(adapter->flags & UDP_RSS_FLAGS))
2675 dev_err(&adapter->pdev->dev,
2676 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2677
2678 adapter->flags = flags;
2679
2680 /* Perform hash on these packet types */
2681 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2682 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2683 E1000_MRQC_RSS_FIELD_IPV6 |
2684 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2685
2686 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2687 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2688
2689 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2690 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2691
2692 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2693 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2694
2695 wr32(E1000_MRQC, mrqc);
2696 }
2697
2698 return 0;
2699 }
2700
2701 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2702 struct igb_nfc_filter *input)
2703 {
2704 struct e1000_hw *hw = &adapter->hw;
2705 u8 i;
2706 u32 etqf;
2707 u16 etype;
2708
2709 /* find an empty etype filter register */
2710 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2711 if (!adapter->etype_bitmap[i])
2712 break;
2713 }
2714 if (i == MAX_ETYPE_FILTER) {
2715 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2716 return -EINVAL;
2717 }
2718
2719 adapter->etype_bitmap[i] = true;
2720
2721 etqf = rd32(E1000_ETQF(i));
2722 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2723
2724 etqf |= E1000_ETQF_FILTER_ENABLE;
2725 etqf &= ~E1000_ETQF_ETYPE_MASK;
2726 etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2727
2728 etqf &= ~E1000_ETQF_QUEUE_MASK;
2729 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2730 & E1000_ETQF_QUEUE_MASK);
2731 etqf |= E1000_ETQF_QUEUE_ENABLE;
2732
2733 wr32(E1000_ETQF(i), etqf);
2734
2735 input->etype_reg_index = i;
2736
2737 return 0;
2738 }
2739
2740 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2741 struct igb_nfc_filter *input)
2742 {
2743 struct e1000_hw *hw = &adapter->hw;
2744 u8 vlan_priority;
2745 u16 queue_index;
2746 u32 vlapqf;
2747
2748 vlapqf = rd32(E1000_VLAPQF);
2749 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2750 >> VLAN_PRIO_SHIFT;
2751 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2752
2753 /* check whether this vlan prio is already set */
2754 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2755 (queue_index != input->action)) {
2756 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2757 return -EEXIST;
2758 }
2759
2760 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2761 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2762
2763 wr32(E1000_VLAPQF, vlapqf);
2764
2765 return 0;
2766 }
2767
2768 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2769 {
2770 int err = -EINVAL;
2771
2772 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2773 err = igb_rxnfc_write_etype_filter(adapter, input);
2774 if (err)
2775 return err;
2776 }
2777
2778 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2779 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
2780
2781 return err;
2782 }
2783
2784 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2785 u16 reg_index)
2786 {
2787 struct e1000_hw *hw = &adapter->hw;
2788 u32 etqf = rd32(E1000_ETQF(reg_index));
2789
2790 etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2791 etqf &= ~E1000_ETQF_QUEUE_MASK;
2792 etqf &= ~E1000_ETQF_FILTER_ENABLE;
2793
2794 wr32(E1000_ETQF(reg_index), etqf);
2795
2796 adapter->etype_bitmap[reg_index] = false;
2797 }
2798
2799 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2800 u16 vlan_tci)
2801 {
2802 struct e1000_hw *hw = &adapter->hw;
2803 u8 vlan_priority;
2804 u32 vlapqf;
2805
2806 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2807
2808 vlapqf = rd32(E1000_VLAPQF);
2809 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2810 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2811 E1000_VLAPQF_QUEUE_MASK);
2812
2813 wr32(E1000_VLAPQF, vlapqf);
2814 }
2815
2816 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2817 {
2818 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2819 igb_clear_etype_filter_regs(adapter,
2820 input->etype_reg_index);
2821
2822 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2823 igb_clear_vlan_prio_filter(adapter,
2824 ntohs(input->filter.vlan_tci));
2825
2826 return 0;
2827 }
2828
2829 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2830 struct igb_nfc_filter *input,
2831 u16 sw_idx)
2832 {
2833 struct igb_nfc_filter *rule, *parent;
2834 int err = -EINVAL;
2835
2836 parent = NULL;
2837 rule = NULL;
2838
2839 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2840 /* hash found, or no matching entry */
2841 if (rule->sw_idx >= sw_idx)
2842 break;
2843 parent = rule;
2844 }
2845
2846 /* if there is an old rule occupying our place remove it */
2847 if (rule && (rule->sw_idx == sw_idx)) {
2848 if (!input)
2849 err = igb_erase_filter(adapter, rule);
2850
2851 hlist_del(&rule->nfc_node);
2852 kfree(rule);
2853 adapter->nfc_filter_count--;
2854 }
2855
2856 /* If no input this was a delete, err should be 0 if a rule was
2857 * successfully found and removed from the list else -EINVAL
2858 */
2859 if (!input)
2860 return err;
2861
2862 /* initialize node */
2863 INIT_HLIST_NODE(&input->nfc_node);
2864
2865 /* add filter to the list */
2866 if (parent)
2867 hlist_add_behind(&parent->nfc_node, &input->nfc_node);
2868 else
2869 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2870
2871 /* update counts */
2872 adapter->nfc_filter_count++;
2873
2874 return 0;
2875 }
2876
2877 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2878 struct ethtool_rxnfc *cmd)
2879 {
2880 struct net_device *netdev = adapter->netdev;
2881 struct ethtool_rx_flow_spec *fsp =
2882 (struct ethtool_rx_flow_spec *)&cmd->fs;
2883 struct igb_nfc_filter *input, *rule;
2884 int err = 0;
2885
2886 if (!(netdev->hw_features & NETIF_F_NTUPLE))
2887 return -EOPNOTSUPP;
2888
2889 /* Don't allow programming if the action is a queue greater than
2890 * the number of online Rx queues.
2891 */
2892 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2893 (fsp->ring_cookie >= adapter->num_rx_queues)) {
2894 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2895 return -EINVAL;
2896 }
2897
2898 /* Don't allow indexes to exist outside of available space */
2899 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2900 dev_err(&adapter->pdev->dev, "Location out of range\n");
2901 return -EINVAL;
2902 }
2903
2904 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2905 return -EINVAL;
2906
2907 if (fsp->m_u.ether_spec.h_proto != ETHER_TYPE_FULL_MASK &&
2908 fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK))
2909 return -EINVAL;
2910
2911 input = kzalloc(sizeof(*input), GFP_KERNEL);
2912 if (!input)
2913 return -ENOMEM;
2914
2915 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2916 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2917 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2918 }
2919
2920 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2921 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2922 err = -EINVAL;
2923 goto err_out;
2924 }
2925 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2926 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2927 }
2928
2929 input->action = fsp->ring_cookie;
2930 input->sw_idx = fsp->location;
2931
2932 spin_lock(&adapter->nfc_lock);
2933
2934 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2935 if (!memcmp(&input->filter, &rule->filter,
2936 sizeof(input->filter))) {
2937 err = -EEXIST;
2938 dev_err(&adapter->pdev->dev,
2939 "ethtool: this filter is already set\n");
2940 goto err_out_w_lock;
2941 }
2942 }
2943
2944 err = igb_add_filter(adapter, input);
2945 if (err)
2946 goto err_out_w_lock;
2947
2948 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2949
2950 spin_unlock(&adapter->nfc_lock);
2951 return 0;
2952
2953 err_out_w_lock:
2954 spin_unlock(&adapter->nfc_lock);
2955 err_out:
2956 kfree(input);
2957 return err;
2958 }
2959
2960 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
2961 struct ethtool_rxnfc *cmd)
2962 {
2963 struct ethtool_rx_flow_spec *fsp =
2964 (struct ethtool_rx_flow_spec *)&cmd->fs;
2965 int err;
2966
2967 spin_lock(&adapter->nfc_lock);
2968 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
2969 spin_unlock(&adapter->nfc_lock);
2970
2971 return err;
2972 }
2973
2974 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2975 {
2976 struct igb_adapter *adapter = netdev_priv(dev);
2977 int ret = -EOPNOTSUPP;
2978
2979 switch (cmd->cmd) {
2980 case ETHTOOL_SRXFH:
2981 ret = igb_set_rss_hash_opt(adapter, cmd);
2982 break;
2983 case ETHTOOL_SRXCLSRLINS:
2984 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
2985 break;
2986 case ETHTOOL_SRXCLSRLDEL:
2987 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
2988 default:
2989 break;
2990 }
2991
2992 return ret;
2993 }
2994
2995 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2996 {
2997 struct igb_adapter *adapter = netdev_priv(netdev);
2998 struct e1000_hw *hw = &adapter->hw;
2999 u32 ret_val;
3000 u16 phy_data;
3001
3002 if ((hw->mac.type < e1000_i350) ||
3003 (hw->phy.media_type != e1000_media_type_copper))
3004 return -EOPNOTSUPP;
3005
3006 edata->supported = (SUPPORTED_1000baseT_Full |
3007 SUPPORTED_100baseT_Full);
3008 if (!hw->dev_spec._82575.eee_disable)
3009 edata->advertised =
3010 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
3011
3012 /* The IPCNFG and EEER registers are not supported on I354. */
3013 if (hw->mac.type == e1000_i354) {
3014 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
3015 } else {
3016 u32 eeer;
3017
3018 eeer = rd32(E1000_EEER);
3019
3020 /* EEE status on negotiated link */
3021 if (eeer & E1000_EEER_EEE_NEG)
3022 edata->eee_active = true;
3023
3024 if (eeer & E1000_EEER_TX_LPI_EN)
3025 edata->tx_lpi_enabled = true;
3026 }
3027
3028 /* EEE Link Partner Advertised */
3029 switch (hw->mac.type) {
3030 case e1000_i350:
3031 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
3032 &phy_data);
3033 if (ret_val)
3034 return -ENODATA;
3035
3036 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3037 break;
3038 case e1000_i354:
3039 case e1000_i210:
3040 case e1000_i211:
3041 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3042 E1000_EEE_LP_ADV_DEV_I210,
3043 &phy_data);
3044 if (ret_val)
3045 return -ENODATA;
3046
3047 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3048
3049 break;
3050 default:
3051 break;
3052 }
3053
3054 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3055
3056 if ((hw->mac.type == e1000_i354) &&
3057 (edata->eee_enabled))
3058 edata->tx_lpi_enabled = true;
3059
3060 /* Report correct negotiated EEE status for devices that
3061 * wrongly report EEE at half-duplex
3062 */
3063 if (adapter->link_duplex == HALF_DUPLEX) {
3064 edata->eee_enabled = false;
3065 edata->eee_active = false;
3066 edata->tx_lpi_enabled = false;
3067 edata->advertised &= ~edata->advertised;
3068 }
3069
3070 return 0;
3071 }
3072
3073 static int igb_set_eee(struct net_device *netdev,
3074 struct ethtool_eee *edata)
3075 {
3076 struct igb_adapter *adapter = netdev_priv(netdev);
3077 struct e1000_hw *hw = &adapter->hw;
3078 struct ethtool_eee eee_curr;
3079 bool adv1g_eee = true, adv100m_eee = true;
3080 s32 ret_val;
3081
3082 if ((hw->mac.type < e1000_i350) ||
3083 (hw->phy.media_type != e1000_media_type_copper))
3084 return -EOPNOTSUPP;
3085
3086 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3087
3088 ret_val = igb_get_eee(netdev, &eee_curr);
3089 if (ret_val)
3090 return ret_val;
3091
3092 if (eee_curr.eee_enabled) {
3093 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3094 dev_err(&adapter->pdev->dev,
3095 "Setting EEE tx-lpi is not supported\n");
3096 return -EINVAL;
3097 }
3098
3099 /* Tx LPI timer is not implemented currently */
3100 if (edata->tx_lpi_timer) {
3101 dev_err(&adapter->pdev->dev,
3102 "Setting EEE Tx LPI timer is not supported\n");
3103 return -EINVAL;
3104 }
3105
3106 if (!edata->advertised || (edata->advertised &
3107 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
3108 dev_err(&adapter->pdev->dev,
3109 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
3110 return -EINVAL;
3111 }
3112 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3113 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
3114
3115 } else if (!edata->eee_enabled) {
3116 dev_err(&adapter->pdev->dev,
3117 "Setting EEE options are not supported with EEE disabled\n");
3118 return -EINVAL;
3119 }
3120
3121 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
3122 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3123 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
3124 adapter->flags |= IGB_FLAG_EEE;
3125
3126 /* reset link */
3127 if (netif_running(netdev))
3128 igb_reinit_locked(adapter);
3129 else
3130 igb_reset(adapter);
3131 }
3132
3133 if (hw->mac.type == e1000_i354)
3134 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3135 else
3136 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3137
3138 if (ret_val) {
3139 dev_err(&adapter->pdev->dev,
3140 "Problem setting EEE advertisement options\n");
3141 return -EINVAL;
3142 }
3143
3144 return 0;
3145 }
3146
3147 static int igb_get_module_info(struct net_device *netdev,
3148 struct ethtool_modinfo *modinfo)
3149 {
3150 struct igb_adapter *adapter = netdev_priv(netdev);
3151 struct e1000_hw *hw = &adapter->hw;
3152 u32 status = 0;
3153 u16 sff8472_rev, addr_mode;
3154 bool page_swap = false;
3155
3156 if ((hw->phy.media_type == e1000_media_type_copper) ||
3157 (hw->phy.media_type == e1000_media_type_unknown))
3158 return -EOPNOTSUPP;
3159
3160 /* Check whether we support SFF-8472 or not */
3161 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
3162 if (status)
3163 return -EIO;
3164
3165 /* addressing mode is not supported */
3166 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
3167 if (status)
3168 return -EIO;
3169
3170 /* addressing mode is not supported */
3171 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3172 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3173 page_swap = true;
3174 }
3175
3176 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3177 /* We have an SFP, but it does not support SFF-8472 */
3178 modinfo->type = ETH_MODULE_SFF_8079;
3179 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3180 } else {
3181 /* We have an SFP which supports a revision of SFF-8472 */
3182 modinfo->type = ETH_MODULE_SFF_8472;
3183 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3184 }
3185
3186 return 0;
3187 }
3188
3189 static int igb_get_module_eeprom(struct net_device *netdev,
3190 struct ethtool_eeprom *ee, u8 *data)
3191 {
3192 struct igb_adapter *adapter = netdev_priv(netdev);
3193 struct e1000_hw *hw = &adapter->hw;
3194 u32 status = 0;
3195 u16 *dataword;
3196 u16 first_word, last_word;
3197 int i = 0;
3198
3199 if (ee->len == 0)
3200 return -EINVAL;
3201
3202 first_word = ee->offset >> 1;
3203 last_word = (ee->offset + ee->len - 1) >> 1;
3204
3205 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
3206 GFP_KERNEL);
3207 if (!dataword)
3208 return -ENOMEM;
3209
3210 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3211 for (i = 0; i < last_word - first_word + 1; i++) {
3212 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3213 &dataword[i]);
3214 if (status) {
3215 /* Error occurred while reading module */
3216 kfree(dataword);
3217 return -EIO;
3218 }
3219
3220 be16_to_cpus(&dataword[i]);
3221 }
3222
3223 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3224 kfree(dataword);
3225
3226 return 0;
3227 }
3228
3229 static int igb_ethtool_begin(struct net_device *netdev)
3230 {
3231 struct igb_adapter *adapter = netdev_priv(netdev);
3232 pm_runtime_get_sync(&adapter->pdev->dev);
3233 return 0;
3234 }
3235
3236 static void igb_ethtool_complete(struct net_device *netdev)
3237 {
3238 struct igb_adapter *adapter = netdev_priv(netdev);
3239 pm_runtime_put(&adapter->pdev->dev);
3240 }
3241
3242 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3243 {
3244 return IGB_RETA_SIZE;
3245 }
3246
3247 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3248 u8 *hfunc)
3249 {
3250 struct igb_adapter *adapter = netdev_priv(netdev);
3251 int i;
3252
3253 if (hfunc)
3254 *hfunc = ETH_RSS_HASH_TOP;
3255 if (!indir)
3256 return 0;
3257 for (i = 0; i < IGB_RETA_SIZE; i++)
3258 indir[i] = adapter->rss_indir_tbl[i];
3259
3260 return 0;
3261 }
3262
3263 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3264 {
3265 struct e1000_hw *hw = &adapter->hw;
3266 u32 reg = E1000_RETA(0);
3267 u32 shift = 0;
3268 int i = 0;
3269
3270 switch (hw->mac.type) {
3271 case e1000_82575:
3272 shift = 6;
3273 break;
3274 case e1000_82576:
3275 /* 82576 supports 2 RSS queues for SR-IOV */
3276 if (adapter->vfs_allocated_count)
3277 shift = 3;
3278 break;
3279 default:
3280 break;
3281 }
3282
3283 while (i < IGB_RETA_SIZE) {
3284 u32 val = 0;
3285 int j;
3286
3287 for (j = 3; j >= 0; j--) {
3288 val <<= 8;
3289 val |= adapter->rss_indir_tbl[i + j];
3290 }
3291
3292 wr32(reg, val << shift);
3293 reg += 4;
3294 i += 4;
3295 }
3296 }
3297
3298 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
3299 const u8 *key, const u8 hfunc)
3300 {
3301 struct igb_adapter *adapter = netdev_priv(netdev);
3302 struct e1000_hw *hw = &adapter->hw;
3303 int i;
3304 u32 num_queues;
3305
3306 /* We do not allow change in unsupported parameters */
3307 if (key ||
3308 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3309 return -EOPNOTSUPP;
3310 if (!indir)
3311 return 0;
3312
3313 num_queues = adapter->rss_queues;
3314
3315 switch (hw->mac.type) {
3316 case e1000_82576:
3317 /* 82576 supports 2 RSS queues for SR-IOV */
3318 if (adapter->vfs_allocated_count)
3319 num_queues = 2;
3320 break;
3321 default:
3322 break;
3323 }
3324
3325 /* Verify user input. */
3326 for (i = 0; i < IGB_RETA_SIZE; i++)
3327 if (indir[i] >= num_queues)
3328 return -EINVAL;
3329
3330
3331 for (i = 0; i < IGB_RETA_SIZE; i++)
3332 adapter->rss_indir_tbl[i] = indir[i];
3333
3334 igb_write_rss_indir_tbl(adapter);
3335
3336 return 0;
3337 }
3338
3339 static unsigned int igb_max_channels(struct igb_adapter *adapter)
3340 {
3341 return igb_get_max_rss_queues(adapter);
3342 }
3343
3344 static void igb_get_channels(struct net_device *netdev,
3345 struct ethtool_channels *ch)
3346 {
3347 struct igb_adapter *adapter = netdev_priv(netdev);
3348
3349 /* Report maximum channels */
3350 ch->max_combined = igb_max_channels(adapter);
3351
3352 /* Report info for other vector */
3353 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
3354 ch->max_other = NON_Q_VECTORS;
3355 ch->other_count = NON_Q_VECTORS;
3356 }
3357
3358 ch->combined_count = adapter->rss_queues;
3359 }
3360
3361 static int igb_set_channels(struct net_device *netdev,
3362 struct ethtool_channels *ch)
3363 {
3364 struct igb_adapter *adapter = netdev_priv(netdev);
3365 unsigned int count = ch->combined_count;
3366 unsigned int max_combined = 0;
3367
3368 /* Verify they are not requesting separate vectors */
3369 if (!count || ch->rx_count || ch->tx_count)
3370 return -EINVAL;
3371
3372 /* Verify other_count is valid and has not been changed */
3373 if (ch->other_count != NON_Q_VECTORS)
3374 return -EINVAL;
3375
3376 /* Verify the number of channels doesn't exceed hw limits */
3377 max_combined = igb_max_channels(adapter);
3378 if (count > max_combined)
3379 return -EINVAL;
3380
3381 if (count != adapter->rss_queues) {
3382 adapter->rss_queues = count;
3383 igb_set_flag_queue_pairs(adapter, max_combined);
3384
3385 /* Hardware has to reinitialize queues and interrupts to
3386 * match the new configuration.
3387 */
3388 return igb_reinit_queues(adapter);
3389 }
3390
3391 return 0;
3392 }
3393
3394 static u32 igb_get_priv_flags(struct net_device *netdev)
3395 {
3396 struct igb_adapter *adapter = netdev_priv(netdev);
3397 u32 priv_flags = 0;
3398
3399 if (adapter->flags & IGB_FLAG_RX_LEGACY)
3400 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;
3401
3402 return priv_flags;
3403 }
3404
3405 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3406 {
3407 struct igb_adapter *adapter = netdev_priv(netdev);
3408 unsigned int flags = adapter->flags;
3409
3410 flags &= ~IGB_FLAG_RX_LEGACY;
3411 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)
3412 flags |= IGB_FLAG_RX_LEGACY;
3413
3414 if (flags != adapter->flags) {
3415 adapter->flags = flags;
3416
3417 /* reset interface to repopulate queues */
3418 if (netif_running(netdev))
3419 igb_reinit_locked(adapter);
3420 }
3421
3422 return 0;
3423 }
3424
3425 static const struct ethtool_ops igb_ethtool_ops = {
3426 .get_drvinfo = igb_get_drvinfo,
3427 .get_regs_len = igb_get_regs_len,
3428 .get_regs = igb_get_regs,
3429 .get_wol = igb_get_wol,
3430 .set_wol = igb_set_wol,
3431 .get_msglevel = igb_get_msglevel,
3432 .set_msglevel = igb_set_msglevel,
3433 .nway_reset = igb_nway_reset,
3434 .get_link = igb_get_link,
3435 .get_eeprom_len = igb_get_eeprom_len,
3436 .get_eeprom = igb_get_eeprom,
3437 .set_eeprom = igb_set_eeprom,
3438 .get_ringparam = igb_get_ringparam,
3439 .set_ringparam = igb_set_ringparam,
3440 .get_pauseparam = igb_get_pauseparam,
3441 .set_pauseparam = igb_set_pauseparam,
3442 .self_test = igb_diag_test,
3443 .get_strings = igb_get_strings,
3444 .set_phys_id = igb_set_phys_id,
3445 .get_sset_count = igb_get_sset_count,
3446 .get_ethtool_stats = igb_get_ethtool_stats,
3447 .get_coalesce = igb_get_coalesce,
3448 .set_coalesce = igb_set_coalesce,
3449 .get_ts_info = igb_get_ts_info,
3450 .get_rxnfc = igb_get_rxnfc,
3451 .set_rxnfc = igb_set_rxnfc,
3452 .get_eee = igb_get_eee,
3453 .set_eee = igb_set_eee,
3454 .get_module_info = igb_get_module_info,
3455 .get_module_eeprom = igb_get_module_eeprom,
3456 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3457 .get_rxfh = igb_get_rxfh,
3458 .set_rxfh = igb_set_rxfh,
3459 .get_channels = igb_get_channels,
3460 .set_channels = igb_set_channels,
3461 .get_priv_flags = igb_get_priv_flags,
3462 .set_priv_flags = igb_set_priv_flags,
3463 .begin = igb_ethtool_begin,
3464 .complete = igb_ethtool_complete,
3465 .get_link_ksettings = igb_get_link_ksettings,
3466 .set_link_ksettings = igb_set_link_ksettings,
3467 };
3468
3469 void igb_set_ethtool_ops(struct net_device *netdev)
3470 {
3471 netdev->ethtool_ops = &igb_ethtool_ops;
3472 }
CRIS linux kernel tree