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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / net / ethernet / mellanox / mlx5 / core / eq.c
blob25106e996a968406cb1bfbc655868ccf622009d3
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
38 #include "fpga/core.h"
39 #include "eswitch.h"
40
41 enum {
42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
43 MLX5_EQE_OWNER_INIT_VAL = 0x1,
44 };
45
46 enum {
47 MLX5_EQ_STATE_ARMED = 0x9,
48 MLX5_EQ_STATE_FIRED = 0xa,
49 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
50 };
51
52 enum {
53 MLX5_NUM_SPARE_EQE = 0x80,
54 MLX5_NUM_ASYNC_EQE = 0x1000,
55 MLX5_NUM_CMD_EQE = 32,
56 MLX5_NUM_PF_DRAIN = 64,
57 };
58
59 enum {
60 MLX5_EQ_DOORBEL_OFFSET = 0x40,
61 };
62
63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
64 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
65 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
66 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
67 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
69 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
70 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
71 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
72 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
73 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
74 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
75
76 struct map_eq_in {
77 u64 mask;
78 u32 reserved;
79 u32 unmap_eqn;
80 };
81
82 struct cre_des_eq {
83 u8 reserved[15];
84 u8 eqn;
85 };
86
87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
88 {
89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
90 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
91
92 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
93 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
95 }
96
97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
98 {
99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
100 }
101
102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
103 {
104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
105
106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
107 }
108
109 static const char *eqe_type_str(u8 type)
110 {
111 switch (type) {
112 case MLX5_EVENT_TYPE_COMP:
113 return "MLX5_EVENT_TYPE_COMP";
114 case MLX5_EVENT_TYPE_PATH_MIG:
115 return "MLX5_EVENT_TYPE_PATH_MIG";
116 case MLX5_EVENT_TYPE_COMM_EST:
117 return "MLX5_EVENT_TYPE_COMM_EST";
118 case MLX5_EVENT_TYPE_SQ_DRAINED:
119 return "MLX5_EVENT_TYPE_SQ_DRAINED";
120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
124 case MLX5_EVENT_TYPE_CQ_ERROR:
125 return "MLX5_EVENT_TYPE_CQ_ERROR";
126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
136 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
138 case MLX5_EVENT_TYPE_PORT_CHANGE:
139 return "MLX5_EVENT_TYPE_PORT_CHANGE";
140 case MLX5_EVENT_TYPE_GPIO_EVENT:
141 return "MLX5_EVENT_TYPE_GPIO_EVENT";
142 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
144 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
148 case MLX5_EVENT_TYPE_STALL_EVENT:
149 return "MLX5_EVENT_TYPE_STALL_EVENT";
150 case MLX5_EVENT_TYPE_CMD:
151 return "MLX5_EVENT_TYPE_CMD";
152 case MLX5_EVENT_TYPE_PAGE_REQUEST:
153 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
154 case MLX5_EVENT_TYPE_PAGE_FAULT:
155 return "MLX5_EVENT_TYPE_PAGE_FAULT";
156 case MLX5_EVENT_TYPE_PPS_EVENT:
157 return "MLX5_EVENT_TYPE_PPS_EVENT";
158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
160 case MLX5_EVENT_TYPE_FPGA_ERROR:
161 return "MLX5_EVENT_TYPE_FPGA_ERROR";
162 case MLX5_EVENT_TYPE_GENERAL_EVENT:
163 return "MLX5_EVENT_TYPE_GENERAL_EVENT";
164 default:
165 return "Unrecognized event";
166 }
167 }
168
169 static enum mlx5_dev_event port_subtype_event(u8 subtype)
170 {
171 switch (subtype) {
172 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
173 return MLX5_DEV_EVENT_PORT_DOWN;
174 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
175 return MLX5_DEV_EVENT_PORT_UP;
176 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
177 return MLX5_DEV_EVENT_PORT_INITIALIZED;
178 case MLX5_PORT_CHANGE_SUBTYPE_LID:
179 return MLX5_DEV_EVENT_LID_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
181 return MLX5_DEV_EVENT_PKEY_CHANGE;
182 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
183 return MLX5_DEV_EVENT_GUID_CHANGE;
184 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
185 return MLX5_DEV_EVENT_CLIENT_REREG;
186 }
187 return -1;
188 }
189
190 static void eq_update_ci(struct mlx5_eq *eq, int arm)
191 {
192 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
193 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
194
195 __raw_writel((__force u32)cpu_to_be32(val), addr);
196 /* We still want ordering, just not swabbing, so add a barrier */
197 mb();
198 }
199
200 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
201 static void eqe_pf_action(struct work_struct *work)
202 {
203 struct mlx5_pagefault *pfault = container_of(work,
204 struct mlx5_pagefault,
205 work);
206 struct mlx5_eq *eq = pfault->eq;
207
208 mlx5_core_page_fault(eq->dev, pfault);
209 mempool_free(pfault, eq->pf_ctx.pool);
210 }
211
212 static void eq_pf_process(struct mlx5_eq *eq)
213 {
214 struct mlx5_core_dev *dev = eq->dev;
215 struct mlx5_eqe_page_fault *pf_eqe;
216 struct mlx5_pagefault *pfault;
217 struct mlx5_eqe *eqe;
218 int set_ci = 0;
219
220 while ((eqe = next_eqe_sw(eq))) {
221 pfault = mempool_alloc(eq->pf_ctx.pool, GFP_ATOMIC);
222 if (!pfault) {
223 schedule_work(&eq->pf_ctx.work);
224 break;
225 }
226
227 dma_rmb();
228 pf_eqe = &eqe->data.page_fault;
229 pfault->event_subtype = eqe->sub_type;
230 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
231
232 mlx5_core_dbg(dev,
233 "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
234 eqe->sub_type, pfault->bytes_committed);
235
236 switch (eqe->sub_type) {
237 case MLX5_PFAULT_SUBTYPE_RDMA:
238 /* RDMA based event */
239 pfault->type =
240 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
241 pfault->token =
242 be32_to_cpu(pf_eqe->rdma.pftype_token) &
243 MLX5_24BIT_MASK;
244 pfault->rdma.r_key =
245 be32_to_cpu(pf_eqe->rdma.r_key);
246 pfault->rdma.packet_size =
247 be16_to_cpu(pf_eqe->rdma.packet_length);
248 pfault->rdma.rdma_op_len =
249 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
250 pfault->rdma.rdma_va =
251 be64_to_cpu(pf_eqe->rdma.rdma_va);
252 mlx5_core_dbg(dev,
253 "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
254 pfault->type, pfault->token,
255 pfault->rdma.r_key);
256 mlx5_core_dbg(dev,
257 "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
258 pfault->rdma.rdma_op_len,
259 pfault->rdma.rdma_va);
260 break;
261
262 case MLX5_PFAULT_SUBTYPE_WQE:
263 /* WQE based event */
264 pfault->type =
265 be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24;
266 pfault->token =
267 be32_to_cpu(pf_eqe->wqe.token);
268 pfault->wqe.wq_num =
269 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
270 MLX5_24BIT_MASK;
271 pfault->wqe.wqe_index =
272 be16_to_cpu(pf_eqe->wqe.wqe_index);
273 pfault->wqe.packet_size =
274 be16_to_cpu(pf_eqe->wqe.packet_length);
275 mlx5_core_dbg(dev,
276 "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
277 pfault->type, pfault->token,
278 pfault->wqe.wq_num,
279 pfault->wqe.wqe_index);
280 break;
281
282 default:
283 mlx5_core_warn(dev,
284 "Unsupported page fault event sub-type: 0x%02hhx\n",
285 eqe->sub_type);
286 /* Unsupported page faults should still be
287 * resolved by the page fault handler
288 */
289 }
290
291 pfault->eq = eq;
292 INIT_WORK(&pfault->work, eqe_pf_action);
293 queue_work(eq->pf_ctx.wq, &pfault->work);
294
295 ++eq->cons_index;
296 ++set_ci;
297
298 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
299 eq_update_ci(eq, 0);
300 set_ci = 0;
301 }
302 }
303
304 eq_update_ci(eq, 1);
305 }
306
307 static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
308 {
309 struct mlx5_eq *eq = eq_ptr;
310 unsigned long flags;
311
312 if (spin_trylock_irqsave(&eq->pf_ctx.lock, flags)) {
313 eq_pf_process(eq);
314 spin_unlock_irqrestore(&eq->pf_ctx.lock, flags);
315 } else {
316 schedule_work(&eq->pf_ctx.work);
317 }
318
319 return IRQ_HANDLED;
320 }
321
322 /* mempool_refill() was proposed but unfortunately wasn't accepted
323 * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
324 * Chip workaround.
325 */
326 static void mempool_refill(mempool_t *pool)
327 {
328 while (pool->curr_nr < pool->min_nr)
329 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
330 }
331
332 static void eq_pf_action(struct work_struct *work)
333 {
334 struct mlx5_eq *eq = container_of(work, struct mlx5_eq, pf_ctx.work);
335
336 mempool_refill(eq->pf_ctx.pool);
337
338 spin_lock_irq(&eq->pf_ctx.lock);
339 eq_pf_process(eq);
340 spin_unlock_irq(&eq->pf_ctx.lock);
341 }
342
343 static int init_pf_ctx(struct mlx5_eq_pagefault *pf_ctx, const char *name)
344 {
345 spin_lock_init(&pf_ctx->lock);
346 INIT_WORK(&pf_ctx->work, eq_pf_action);
347
348 pf_ctx->wq = alloc_ordered_workqueue(name,
349 WQ_MEM_RECLAIM);
350 if (!pf_ctx->wq)
351 return -ENOMEM;
352
353 pf_ctx->pool = mempool_create_kmalloc_pool
354 (MLX5_NUM_PF_DRAIN, sizeof(struct mlx5_pagefault));
355 if (!pf_ctx->pool)
356 goto err_wq;
357
358 return 0;
359 err_wq:
360 destroy_workqueue(pf_ctx->wq);
361 return -ENOMEM;
362 }
363
364 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
365 u32 wq_num, u8 type, int error)
366 {
367 u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = {0};
368 u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {0};
369
370 MLX5_SET(page_fault_resume_in, in, opcode,
371 MLX5_CMD_OP_PAGE_FAULT_RESUME);
372 MLX5_SET(page_fault_resume_in, in, error, !!error);
373 MLX5_SET(page_fault_resume_in, in, page_fault_type, type);
374 MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
375 MLX5_SET(page_fault_resume_in, in, token, token);
376
377 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
378 }
379 EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
380 #endif
381
382 static void general_event_handler(struct mlx5_core_dev *dev,
383 struct mlx5_eqe *eqe)
384 {
385 switch (eqe->sub_type) {
386 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
387 if (dev->event)
388 dev->event(dev, MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 0);
389 break;
390 default:
391 mlx5_core_dbg(dev, "General event with unrecognized subtype: sub_type %d\n",
392 eqe->sub_type);
393 }
394 }
395
396 static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
397 {
398 struct mlx5_eq *eq = eq_ptr;
399 struct mlx5_core_dev *dev = eq->dev;
400 struct mlx5_eqe *eqe;
401 int set_ci = 0;
402 u32 cqn = -1;
403 u32 rsn;
404 u8 port;
405
406 while ((eqe = next_eqe_sw(eq))) {
407 /*
408 * Make sure we read EQ entry contents after we've
409 * checked the ownership bit.
410 */
411 dma_rmb();
412
413 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
414 eq->eqn, eqe_type_str(eqe->type));
415 switch (eqe->type) {
416 case MLX5_EVENT_TYPE_COMP:
417 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
418 mlx5_cq_completion(dev, cqn);
419 break;
420 case MLX5_EVENT_TYPE_DCT_DRAINED:
421 rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
422 rsn |= (MLX5_RES_DCT << MLX5_USER_INDEX_LEN);
423 mlx5_rsc_event(dev, rsn, eqe->type);
424 break;
425 case MLX5_EVENT_TYPE_PATH_MIG:
426 case MLX5_EVENT_TYPE_COMM_EST:
427 case MLX5_EVENT_TYPE_SQ_DRAINED:
428 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
429 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
430 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
431 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
432 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
433 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
434 rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
435 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
436 eqe_type_str(eqe->type), eqe->type, rsn);
437 mlx5_rsc_event(dev, rsn, eqe->type);
438 break;
439
440 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
441 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
442 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
443 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
444 eqe_type_str(eqe->type), eqe->type, rsn);
445 mlx5_srq_event(dev, rsn, eqe->type);
446 break;
447
448 case MLX5_EVENT_TYPE_CMD:
449 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
450 break;
451
452 case MLX5_EVENT_TYPE_PORT_CHANGE:
453 port = (eqe->data.port.port >> 4) & 0xf;
454 switch (eqe->sub_type) {
455 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
456 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
457 case MLX5_PORT_CHANGE_SUBTYPE_LID:
458 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
459 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
460 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
461 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
462 if (dev->event)
463 dev->event(dev, port_subtype_event(eqe->sub_type),
464 (unsigned long)port);
465 break;
466 default:
467 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
468 port, eqe->sub_type);
469 }
470 break;
471 case MLX5_EVENT_TYPE_CQ_ERROR:
472 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
473 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrome 0x%x\n",
474 cqn, eqe->data.cq_err.syndrome);
475 mlx5_cq_event(dev, cqn, eqe->type);
476 break;
477
478 case MLX5_EVENT_TYPE_PAGE_REQUEST:
479 {
480 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
481 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
482
483 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
484 func_id, npages);
485 mlx5_core_req_pages_handler(dev, func_id, npages);
486 }
487 break;
488
489 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
490 mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
491 break;
492
493 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
494 mlx5_port_module_event(dev, eqe);
495 break;
496
497 case MLX5_EVENT_TYPE_PPS_EVENT:
498 mlx5_pps_event(dev, eqe);
499 break;
500
501 case MLX5_EVENT_TYPE_FPGA_ERROR:
502 mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
503 break;
504
505 case MLX5_EVENT_TYPE_GENERAL_EVENT:
506 general_event_handler(dev, eqe);
507 break;
508 default:
509 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
510 eqe->type, eq->eqn);
511 break;
512 }
513
514 ++eq->cons_index;
515 ++set_ci;
516
517 /* The HCA will think the queue has overflowed if we
518 * don't tell it we've been processing events. We
519 * create our EQs with MLX5_NUM_SPARE_EQE extra
520 * entries, so we must update our consumer index at
521 * least that often.
522 */
523 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
524 eq_update_ci(eq, 0);
525 set_ci = 0;
526 }
527 }
528
529 eq_update_ci(eq, 1);
530
531 if (cqn != -1)
532 tasklet_schedule(&eq->tasklet_ctx.task);
533
534 return IRQ_HANDLED;
535 }
536
537 /* Some architectures don't latch interrupts when they are disabled, so using
538 * mlx5_eq_poll_irq_disabled could end up losing interrupts while trying to
539 * avoid losing them. It is not recommended to use it, unless this is the last
540 * resort.
541 */
542 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq *eq)
543 {
544 u32 count_eqe;
545
546 disable_irq(eq->irqn);
547 count_eqe = eq->cons_index;
548 mlx5_eq_int(eq->irqn, eq);
549 count_eqe = eq->cons_index - count_eqe;
550 enable_irq(eq->irqn);
551
552 return count_eqe;
553 }
554
555 static void init_eq_buf(struct mlx5_eq *eq)
556 {
557 struct mlx5_eqe *eqe;
558 int i;
559
560 for (i = 0; i < eq->nent; i++) {
561 eqe = get_eqe(eq, i);
562 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
563 }
564 }
565
566 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
567 int nent, u64 mask, const char *name,
568 enum mlx5_eq_type type)
569 {
570 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
571 struct mlx5_priv *priv = &dev->priv;
572 irq_handler_t handler;
573 __be64 *pas;
574 void *eqc;
575 int inlen;
576 u32 *in;
577 int err;
578
579 eq->type = type;
580 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
581 eq->cons_index = 0;
582 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
583 if (err)
584 return err;
585
586 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
587 if (type == MLX5_EQ_TYPE_PF)
588 handler = mlx5_eq_pf_int;
589 else
590 #endif
591 handler = mlx5_eq_int;
592
593 init_eq_buf(eq);
594
595 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
596 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
597
598 in = kvzalloc(inlen, GFP_KERNEL);
599 if (!in) {
600 err = -ENOMEM;
601 goto err_buf;
602 }
603
604 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
605 mlx5_fill_page_array(&eq->buf, pas);
606
607 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
608 MLX5_SET64(create_eq_in, in, event_bitmask, mask);
609
610 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
611 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
612 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
613 MLX5_SET(eqc, eqc, intr, vecidx);
614 MLX5_SET(eqc, eqc, log_page_size,
615 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
616
617 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
618 if (err)
619 goto err_in;
620
621 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
622 name, pci_name(dev->pdev));
623
624 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
625 eq->irqn = pci_irq_vector(dev->pdev, vecidx);
626 eq->dev = dev;
627 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
628 err = request_irq(eq->irqn, handler, 0,
629 priv->irq_info[vecidx].name, eq);
630 if (err)
631 goto err_eq;
632
633 err = mlx5_debug_eq_add(dev, eq);
634 if (err)
635 goto err_irq;
636
637 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
638 if (type == MLX5_EQ_TYPE_PF) {
639 err = init_pf_ctx(&eq->pf_ctx, name);
640 if (err)
641 goto err_irq;
642 } else
643 #endif
644 {
645 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
646 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
647 spin_lock_init(&eq->tasklet_ctx.lock);
648 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
649 (unsigned long)&eq->tasklet_ctx);
650 }
651
652 /* EQs are created in ARMED state
653 */
654 eq_update_ci(eq, 1);
655
656 kvfree(in);
657 return 0;
658
659 err_irq:
660 free_irq(eq->irqn, eq);
661
662 err_eq:
663 mlx5_cmd_destroy_eq(dev, eq->eqn);
664
665 err_in:
666 kvfree(in);
667
668 err_buf:
669 mlx5_buf_free(dev, &eq->buf);
670 return err;
671 }
672 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
673
674 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
675 {
676 int err;
677
678 mlx5_debug_eq_remove(dev, eq);
679 free_irq(eq->irqn, eq);
680 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
681 if (err)
682 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
683 eq->eqn);
684 synchronize_irq(eq->irqn);
685
686 if (eq->type == MLX5_EQ_TYPE_COMP) {
687 tasklet_disable(&eq->tasklet_ctx.task);
688 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
689 } else if (eq->type == MLX5_EQ_TYPE_PF) {
690 cancel_work_sync(&eq->pf_ctx.work);
691 destroy_workqueue(eq->pf_ctx.wq);
692 mempool_destroy(eq->pf_ctx.pool);
693 #endif
694 }
695 mlx5_buf_free(dev, &eq->buf);
696
697 return err;
698 }
699 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
700
701 int mlx5_eq_init(struct mlx5_core_dev *dev)
702 {
703 int err;
704
705 spin_lock_init(&dev->priv.eq_table.lock);
706
707 err = mlx5_eq_debugfs_init(dev);
708
709 return err;
710 }
711
712 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
713 {
714 mlx5_eq_debugfs_cleanup(dev);
715 }
716
717 int mlx5_start_eqs(struct mlx5_core_dev *dev)
718 {
719 struct mlx5_eq_table *table = &dev->priv.eq_table;
720 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
721 int err;
722
723 if (MLX5_VPORT_MANAGER(dev))
724 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
725
726 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
727 MLX5_CAP_GEN(dev, general_notification_event))
728 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
729
730 if (MLX5_CAP_GEN(dev, port_module_event))
731 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
732 else
733 mlx5_core_dbg(dev, "port_module_event is not set\n");
734
735 if (MLX5_PPS_CAP(dev))
736 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
737
738 if (MLX5_CAP_GEN(dev, fpga))
739 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
740 if (MLX5_CAP_GEN_MAX(dev, dct))
741 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
742
743
744 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
745 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
746 "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
747 if (err) {
748 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
749 return err;
750 }
751
752 mlx5_cmd_use_events(dev);
753
754 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
755 MLX5_NUM_ASYNC_EQE, async_event_mask,
756 "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
757 if (err) {
758 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
759 goto err1;
760 }
761
762 err = mlx5_create_map_eq(dev, &table->pages_eq,
763 MLX5_EQ_VEC_PAGES,
764 /* TODO: sriov max_vf + */ 1,
765 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
766 MLX5_EQ_TYPE_ASYNC);
767 if (err) {
768 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
769 goto err2;
770 }
771
772 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
773 if (MLX5_CAP_GEN(dev, pg)) {
774 err = mlx5_create_map_eq(dev, &table->pfault_eq,
775 MLX5_EQ_VEC_PFAULT,
776 MLX5_NUM_ASYNC_EQE,
777 1 << MLX5_EVENT_TYPE_PAGE_FAULT,
778 "mlx5_page_fault_eq",
779 MLX5_EQ_TYPE_PF);
780 if (err) {
781 mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
782 err);
783 goto err3;
784 }
785 }
786
787 return err;
788 err3:
789 mlx5_destroy_unmap_eq(dev, &table->pages_eq);
790 #else
791 return err;
792 #endif
793
794 err2:
795 mlx5_destroy_unmap_eq(dev, &table->async_eq);
796
797 err1:
798 mlx5_cmd_use_polling(dev);
799 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
800 return err;
801 }
802
803 void mlx5_stop_eqs(struct mlx5_core_dev *dev)
804 {
805 struct mlx5_eq_table *table = &dev->priv.eq_table;
806 int err;
807
808 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
809 if (MLX5_CAP_GEN(dev, pg)) {
810 err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq);
811 if (err)
812 mlx5_core_err(dev, "failed to destroy page fault eq, err(%d)\n",
813 err);
814 }
815 #endif
816
817 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
818 if (err)
819 mlx5_core_err(dev, "failed to destroy pages eq, err(%d)\n",
820 err);
821
822 err = mlx5_destroy_unmap_eq(dev, &table->async_eq);
823 if (err)
824 mlx5_core_err(dev, "failed to destroy async eq, err(%d)\n",
825 err);
826 mlx5_cmd_use_polling(dev);
827
828 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
829 if (err)
830 mlx5_core_err(dev, "failed to destroy command eq, err(%d)\n",
831 err);
832 }
833
834 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
835 u32 *out, int outlen)
836 {
837 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
838
839 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
840 MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
841 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
842 }
843 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
CRIS linux kernel tree