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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / net / ethernet / mellanox / mlxsw / pci.c
blob85faa87bf42d5a88a6b7ed173ee675e093e72436
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/pci.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/export.h>
38 #include <linux/err.h>
39 #include <linux/device.h>
40 #include <linux/pci.h>
41 #include <linux/interrupt.h>
42 #include <linux/wait.h>
43 #include <linux/types.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <linux/log2.h>
47 #include <linux/string.h>
48
49 #include "pci_hw.h"
50 #include "pci.h"
51 #include "core.h"
52 #include "cmd.h"
53 #include "port.h"
54 #include "resources.h"
55
56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
57
58 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
59 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
60 #define mlxsw_pci_read32(mlxsw_pci, reg) \
61 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
62
63 enum mlxsw_pci_queue_type {
64 MLXSW_PCI_QUEUE_TYPE_SDQ,
65 MLXSW_PCI_QUEUE_TYPE_RDQ,
66 MLXSW_PCI_QUEUE_TYPE_CQ,
67 MLXSW_PCI_QUEUE_TYPE_EQ,
68 };
69
70 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
71
72 static const u16 mlxsw_pci_doorbell_type_offset[] = {
73 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
74 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
75 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
76 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
77 };
78
79 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
80 0, /* unused */
81 0, /* unused */
82 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
83 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
84 };
85
86 struct mlxsw_pci_mem_item {
87 char *buf;
88 dma_addr_t mapaddr;
89 size_t size;
90 };
91
92 struct mlxsw_pci_queue_elem_info {
93 char *elem; /* pointer to actual dma mapped element mem chunk */
94 union {
95 struct {
96 struct sk_buff *skb;
97 } sdq;
98 struct {
99 struct sk_buff *skb;
100 } rdq;
101 } u;
102 };
103
104 struct mlxsw_pci_queue {
105 spinlock_t lock; /* for queue accesses */
106 struct mlxsw_pci_mem_item mem_item;
107 struct mlxsw_pci_queue_elem_info *elem_info;
108 u16 producer_counter;
109 u16 consumer_counter;
110 u16 count; /* number of elements in queue */
111 u8 num; /* queue number */
112 u8 elem_size; /* size of one element */
113 enum mlxsw_pci_queue_type type;
114 struct tasklet_struct tasklet; /* queue processing tasklet */
115 struct mlxsw_pci *pci;
116 union {
117 struct {
118 u32 comp_sdq_count;
119 u32 comp_rdq_count;
120 } cq;
121 struct {
122 u32 ev_cmd_count;
123 u32 ev_comp_count;
124 u32 ev_other_count;
125 } eq;
126 } u;
127 };
128
129 struct mlxsw_pci_queue_type_group {
130 struct mlxsw_pci_queue *q;
131 u8 count; /* number of queues in group */
132 };
133
134 struct mlxsw_pci {
135 struct pci_dev *pdev;
136 u8 __iomem *hw_addr;
137 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
138 u32 doorbell_offset;
139 struct mlxsw_core *core;
140 struct {
141 struct mlxsw_pci_mem_item *items;
142 unsigned int count;
143 } fw_area;
144 struct {
145 struct mlxsw_pci_mem_item out_mbox;
146 struct mlxsw_pci_mem_item in_mbox;
147 struct mutex lock; /* Lock access to command registers */
148 bool nopoll;
149 wait_queue_head_t wait;
150 bool wait_done;
151 struct {
152 u8 status;
153 u64 out_param;
154 } comp;
155 } cmd;
156 struct mlxsw_bus_info bus_info;
157 const struct pci_device_id *id;
158 };
159
160 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
161 {
162 tasklet_schedule(&q->tasklet);
163 }
164
165 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
166 size_t elem_size, int elem_index)
167 {
168 return q->mem_item.buf + (elem_size * elem_index);
169 }
170
171 static struct mlxsw_pci_queue_elem_info *
172 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
173 {
174 return &q->elem_info[elem_index];
175 }
176
177 static struct mlxsw_pci_queue_elem_info *
178 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
179 {
180 int index = q->producer_counter & (q->count - 1);
181
182 if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
183 return NULL;
184 return mlxsw_pci_queue_elem_info_get(q, index);
185 }
186
187 static struct mlxsw_pci_queue_elem_info *
188 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
189 {
190 int index = q->consumer_counter & (q->count - 1);
191
192 return mlxsw_pci_queue_elem_info_get(q, index);
193 }
194
195 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
196 {
197 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
198 }
199
200 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
201 {
202 return owner_bit != !!(q->consumer_counter & q->count);
203 }
204
205 static char *
206 mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
207 u32 (*get_elem_owner_func)(const char *))
208 {
209 struct mlxsw_pci_queue_elem_info *elem_info;
210 char *elem;
211 bool owner_bit;
212
213 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
214 elem = elem_info->elem;
215 owner_bit = get_elem_owner_func(elem);
216 if (mlxsw_pci_elem_hw_owned(q, owner_bit))
217 return NULL;
218 q->consumer_counter++;
219 rmb(); /* make sure we read owned bit before the rest of elem */
220 return elem;
221 }
222
223 static struct mlxsw_pci_queue_type_group *
224 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
225 enum mlxsw_pci_queue_type q_type)
226 {
227 return &mlxsw_pci->queues[q_type];
228 }
229
230 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
231 enum mlxsw_pci_queue_type q_type)
232 {
233 struct mlxsw_pci_queue_type_group *queue_group;
234
235 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
236 return queue_group->count;
237 }
238
239 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
240 {
241 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
242 }
243
244 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
245 {
246 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
247 }
248
249 static struct mlxsw_pci_queue *
250 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
251 enum mlxsw_pci_queue_type q_type, u8 q_num)
252 {
253 return &mlxsw_pci->queues[q_type].q[q_num];
254 }
255
256 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
257 u8 q_num)
258 {
259 return __mlxsw_pci_queue_get(mlxsw_pci,
260 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
261 }
262
263 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
264 u8 q_num)
265 {
266 return __mlxsw_pci_queue_get(mlxsw_pci,
267 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
268 }
269
270 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
271 u8 q_num)
272 {
273 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
274 }
275
276 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
277 u8 q_num)
278 {
279 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
280 }
281
282 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
283 struct mlxsw_pci_queue *q,
284 u16 val)
285 {
286 mlxsw_pci_write32(mlxsw_pci,
287 DOORBELL(mlxsw_pci->doorbell_offset,
288 mlxsw_pci_doorbell_type_offset[q->type],
289 q->num), val);
290 }
291
292 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
293 struct mlxsw_pci_queue *q,
294 u16 val)
295 {
296 mlxsw_pci_write32(mlxsw_pci,
297 DOORBELL(mlxsw_pci->doorbell_offset,
298 mlxsw_pci_doorbell_arm_type_offset[q->type],
299 q->num), val);
300 }
301
302 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
303 struct mlxsw_pci_queue *q)
304 {
305 wmb(); /* ensure all writes are done before we ring a bell */
306 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
307 }
308
309 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
310 struct mlxsw_pci_queue *q)
311 {
312 wmb(); /* ensure all writes are done before we ring a bell */
313 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
314 q->consumer_counter + q->count);
315 }
316
317 static void
318 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
319 struct mlxsw_pci_queue *q)
320 {
321 wmb(); /* ensure all writes are done before we ring a bell */
322 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
323 }
324
325 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
326 int page_index)
327 {
328 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
329 }
330
331 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
332 struct mlxsw_pci_queue *q)
333 {
334 int i;
335 int err;
336
337 q->producer_counter = 0;
338 q->consumer_counter = 0;
339
340 /* Set CQ of same number of this SDQ. */
341 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
342 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
343 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
344 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
345 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
346
347 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
348 }
349
350 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
351 if (err)
352 return err;
353 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
354 return 0;
355 }
356
357 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
358 struct mlxsw_pci_queue *q)
359 {
360 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
361 }
362
363 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
364 int index, char *frag_data, size_t frag_len,
365 int direction)
366 {
367 struct pci_dev *pdev = mlxsw_pci->pdev;
368 dma_addr_t mapaddr;
369
370 mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
371 if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
372 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
373 return -EIO;
374 }
375 mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
376 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
377 return 0;
378 }
379
380 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
381 int index, int direction)
382 {
383 struct pci_dev *pdev = mlxsw_pci->pdev;
384 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
385 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
386
387 if (!frag_len)
388 return;
389 pci_unmap_single(pdev, mapaddr, frag_len, direction);
390 }
391
392 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
393 struct mlxsw_pci_queue_elem_info *elem_info)
394 {
395 size_t buf_len = MLXSW_PORT_MAX_MTU;
396 char *wqe = elem_info->elem;
397 struct sk_buff *skb;
398 int err;
399
400 elem_info->u.rdq.skb = NULL;
401 skb = netdev_alloc_skb_ip_align(NULL, buf_len);
402 if (!skb)
403 return -ENOMEM;
404
405 /* Assume that wqe was previously zeroed. */
406
407 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
408 buf_len, DMA_FROM_DEVICE);
409 if (err)
410 goto err_frag_map;
411
412 elem_info->u.rdq.skb = skb;
413 return 0;
414
415 err_frag_map:
416 dev_kfree_skb_any(skb);
417 return err;
418 }
419
420 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
421 struct mlxsw_pci_queue_elem_info *elem_info)
422 {
423 struct sk_buff *skb;
424 char *wqe;
425
426 skb = elem_info->u.rdq.skb;
427 wqe = elem_info->elem;
428
429 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
430 dev_kfree_skb_any(skb);
431 }
432
433 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
434 struct mlxsw_pci_queue *q)
435 {
436 struct mlxsw_pci_queue_elem_info *elem_info;
437 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
438 int i;
439 int err;
440
441 q->producer_counter = 0;
442 q->consumer_counter = 0;
443
444 /* Set CQ of same number of this RDQ with base
445 * above SDQ count as the lower ones are assigned to SDQs.
446 */
447 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
448 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
449 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
450 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
451
452 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
453 }
454
455 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
456 if (err)
457 return err;
458
459 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
460
461 for (i = 0; i < q->count; i++) {
462 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
463 BUG_ON(!elem_info);
464 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
465 if (err)
466 goto rollback;
467 /* Everything is set up, ring doorbell to pass elem to HW */
468 q->producer_counter++;
469 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
470 }
471
472 return 0;
473
474 rollback:
475 for (i--; i >= 0; i--) {
476 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
477 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
478 }
479 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
480
481 return err;
482 }
483
484 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
485 struct mlxsw_pci_queue *q)
486 {
487 struct mlxsw_pci_queue_elem_info *elem_info;
488 int i;
489
490 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
491 for (i = 0; i < q->count; i++) {
492 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
493 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
494 }
495 }
496
497 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
498 struct mlxsw_pci_queue *q)
499 {
500 int i;
501 int err;
502
503 q->consumer_counter = 0;
504
505 for (i = 0; i < q->count; i++) {
506 char *elem = mlxsw_pci_queue_elem_get(q, i);
507
508 mlxsw_pci_cqe_owner_set(elem, 1);
509 }
510
511 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
512 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
513 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
514 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
515 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
516 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
517
518 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
519 }
520 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
521 if (err)
522 return err;
523 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
524 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
525 return 0;
526 }
527
528 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
529 struct mlxsw_pci_queue *q)
530 {
531 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
532 }
533
534 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
535 struct mlxsw_pci_queue *q,
536 u16 consumer_counter_limit,
537 char *cqe)
538 {
539 struct pci_dev *pdev = mlxsw_pci->pdev;
540 struct mlxsw_pci_queue_elem_info *elem_info;
541 char *wqe;
542 struct sk_buff *skb;
543 int i;
544
545 spin_lock(&q->lock);
546 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
547 skb = elem_info->u.sdq.skb;
548 wqe = elem_info->elem;
549 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
550 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
551 dev_kfree_skb_any(skb);
552 elem_info->u.sdq.skb = NULL;
553
554 if (q->consumer_counter++ != consumer_counter_limit)
555 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
556 spin_unlock(&q->lock);
557 }
558
559 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
560 struct mlxsw_pci_queue *q,
561 u16 consumer_counter_limit,
562 char *cqe)
563 {
564 struct pci_dev *pdev = mlxsw_pci->pdev;
565 struct mlxsw_pci_queue_elem_info *elem_info;
566 char *wqe;
567 struct sk_buff *skb;
568 struct mlxsw_rx_info rx_info;
569 u16 byte_count;
570 int err;
571
572 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
573 skb = elem_info->u.sdq.skb;
574 if (!skb)
575 return;
576 wqe = elem_info->elem;
577 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
578
579 if (q->consumer_counter++ != consumer_counter_limit)
580 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
581
582 if (mlxsw_pci_cqe_lag_get(cqe)) {
583 rx_info.is_lag = true;
584 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe);
585 rx_info.lag_port_index = mlxsw_pci_cqe_lag_port_index_get(cqe);
586 } else {
587 rx_info.is_lag = false;
588 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
589 }
590
591 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
592
593 byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
594 if (mlxsw_pci_cqe_crc_get(cqe))
595 byte_count -= ETH_FCS_LEN;
596 skb_put(skb, byte_count);
597 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
598
599 memset(wqe, 0, q->elem_size);
600 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
601 if (err)
602 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
603 /* Everything is set up, ring doorbell to pass elem to HW */
604 q->producer_counter++;
605 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
606 return;
607 }
608
609 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
610 {
611 return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
612 }
613
614 static void mlxsw_pci_cq_tasklet(unsigned long data)
615 {
616 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
617 struct mlxsw_pci *mlxsw_pci = q->pci;
618 char *cqe;
619 int items = 0;
620 int credits = q->count >> 1;
621
622 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
623 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
624 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
625 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
626
627 if (sendq) {
628 struct mlxsw_pci_queue *sdq;
629
630 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
631 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
632 wqe_counter, cqe);
633 q->u.cq.comp_sdq_count++;
634 } else {
635 struct mlxsw_pci_queue *rdq;
636
637 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
638 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
639 wqe_counter, cqe);
640 q->u.cq.comp_rdq_count++;
641 }
642 if (++items == credits)
643 break;
644 }
645 if (items) {
646 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
647 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
648 }
649 }
650
651 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
652 struct mlxsw_pci_queue *q)
653 {
654 int i;
655 int err;
656
657 q->consumer_counter = 0;
658
659 for (i = 0; i < q->count; i++) {
660 char *elem = mlxsw_pci_queue_elem_get(q, i);
661
662 mlxsw_pci_eqe_owner_set(elem, 1);
663 }
664
665 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
666 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
667 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
668 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
669 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
670
671 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
672 }
673 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
674 if (err)
675 return err;
676 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
677 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
678 return 0;
679 }
680
681 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
682 struct mlxsw_pci_queue *q)
683 {
684 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
685 }
686
687 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
688 {
689 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
690 mlxsw_pci->cmd.comp.out_param =
691 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
692 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
693 mlxsw_pci->cmd.wait_done = true;
694 wake_up(&mlxsw_pci->cmd.wait);
695 }
696
697 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
698 {
699 return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
700 }
701
702 static void mlxsw_pci_eq_tasklet(unsigned long data)
703 {
704 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
705 struct mlxsw_pci *mlxsw_pci = q->pci;
706 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
707 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
708 char *eqe;
709 u8 cqn;
710 bool cq_handle = false;
711 int items = 0;
712 int credits = q->count >> 1;
713
714 memset(&active_cqns, 0, sizeof(active_cqns));
715
716 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
717 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
718
719 switch (event_type) {
720 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
721 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
722 q->u.eq.ev_cmd_count++;
723 break;
724 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
725 cqn = mlxsw_pci_eqe_cqn_get(eqe);
726 set_bit(cqn, active_cqns);
727 cq_handle = true;
728 q->u.eq.ev_comp_count++;
729 break;
730 default:
731 q->u.eq.ev_other_count++;
732 }
733 if (++items == credits)
734 break;
735 }
736 if (items) {
737 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
738 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
739 }
740
741 if (!cq_handle)
742 return;
743 for_each_set_bit(cqn, active_cqns, cq_count) {
744 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
745 mlxsw_pci_queue_tasklet_schedule(q);
746 }
747 }
748
749 struct mlxsw_pci_queue_ops {
750 const char *name;
751 enum mlxsw_pci_queue_type type;
752 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
753 struct mlxsw_pci_queue *q);
754 void (*fini)(struct mlxsw_pci *mlxsw_pci,
755 struct mlxsw_pci_queue *q);
756 void (*tasklet)(unsigned long data);
757 u16 elem_count;
758 u8 elem_size;
759 };
760
761 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
762 .type = MLXSW_PCI_QUEUE_TYPE_SDQ,
763 .init = mlxsw_pci_sdq_init,
764 .fini = mlxsw_pci_sdq_fini,
765 .elem_count = MLXSW_PCI_WQE_COUNT,
766 .elem_size = MLXSW_PCI_WQE_SIZE,
767 };
768
769 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
770 .type = MLXSW_PCI_QUEUE_TYPE_RDQ,
771 .init = mlxsw_pci_rdq_init,
772 .fini = mlxsw_pci_rdq_fini,
773 .elem_count = MLXSW_PCI_WQE_COUNT,
774 .elem_size = MLXSW_PCI_WQE_SIZE
775 };
776
777 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
778 .type = MLXSW_PCI_QUEUE_TYPE_CQ,
779 .init = mlxsw_pci_cq_init,
780 .fini = mlxsw_pci_cq_fini,
781 .tasklet = mlxsw_pci_cq_tasklet,
782 .elem_count = MLXSW_PCI_CQE_COUNT,
783 .elem_size = MLXSW_PCI_CQE_SIZE
784 };
785
786 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
787 .type = MLXSW_PCI_QUEUE_TYPE_EQ,
788 .init = mlxsw_pci_eq_init,
789 .fini = mlxsw_pci_eq_fini,
790 .tasklet = mlxsw_pci_eq_tasklet,
791 .elem_count = MLXSW_PCI_EQE_COUNT,
792 .elem_size = MLXSW_PCI_EQE_SIZE
793 };
794
795 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
796 const struct mlxsw_pci_queue_ops *q_ops,
797 struct mlxsw_pci_queue *q, u8 q_num)
798 {
799 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
800 int i;
801 int err;
802
803 spin_lock_init(&q->lock);
804 q->num = q_num;
805 q->count = q_ops->elem_count;
806 q->elem_size = q_ops->elem_size;
807 q->type = q_ops->type;
808 q->pci = mlxsw_pci;
809
810 if (q_ops->tasklet)
811 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
812
813 mem_item->size = MLXSW_PCI_AQ_SIZE;
814 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
815 mem_item->size,
816 &mem_item->mapaddr);
817 if (!mem_item->buf)
818 return -ENOMEM;
819 memset(mem_item->buf, 0, mem_item->size);
820
821 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
822 if (!q->elem_info) {
823 err = -ENOMEM;
824 goto err_elem_info_alloc;
825 }
826
827 /* Initialize dma mapped elements info elem_info for
828 * future easy access.
829 */
830 for (i = 0; i < q->count; i++) {
831 struct mlxsw_pci_queue_elem_info *elem_info;
832
833 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
834 elem_info->elem =
835 __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
836 }
837
838 mlxsw_cmd_mbox_zero(mbox);
839 err = q_ops->init(mlxsw_pci, mbox, q);
840 if (err)
841 goto err_q_ops_init;
842 return 0;
843
844 err_q_ops_init:
845 kfree(q->elem_info);
846 err_elem_info_alloc:
847 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
848 mem_item->buf, mem_item->mapaddr);
849 return err;
850 }
851
852 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
853 const struct mlxsw_pci_queue_ops *q_ops,
854 struct mlxsw_pci_queue *q)
855 {
856 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
857
858 q_ops->fini(mlxsw_pci, q);
859 kfree(q->elem_info);
860 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
861 mem_item->buf, mem_item->mapaddr);
862 }
863
864 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
865 const struct mlxsw_pci_queue_ops *q_ops,
866 u8 num_qs)
867 {
868 struct mlxsw_pci_queue_type_group *queue_group;
869 int i;
870 int err;
871
872 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
873 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
874 if (!queue_group->q)
875 return -ENOMEM;
876
877 for (i = 0; i < num_qs; i++) {
878 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
879 &queue_group->q[i], i);
880 if (err)
881 goto err_queue_init;
882 }
883 queue_group->count = num_qs;
884
885 return 0;
886
887 err_queue_init:
888 for (i--; i >= 0; i--)
889 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
890 kfree(queue_group->q);
891 return err;
892 }
893
894 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
895 const struct mlxsw_pci_queue_ops *q_ops)
896 {
897 struct mlxsw_pci_queue_type_group *queue_group;
898 int i;
899
900 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
901 for (i = 0; i < queue_group->count; i++)
902 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
903 kfree(queue_group->q);
904 }
905
906 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
907 {
908 struct pci_dev *pdev = mlxsw_pci->pdev;
909 u8 num_sdqs;
910 u8 sdq_log2sz;
911 u8 num_rdqs;
912 u8 rdq_log2sz;
913 u8 num_cqs;
914 u8 cq_log2sz;
915 u8 num_eqs;
916 u8 eq_log2sz;
917 int err;
918
919 mlxsw_cmd_mbox_zero(mbox);
920 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
921 if (err)
922 return err;
923
924 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
925 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
926 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
927 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
928 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
929 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
930 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
931 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
932
933 if (num_sdqs + num_rdqs > num_cqs ||
934 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
935 dev_err(&pdev->dev, "Unsupported number of queues\n");
936 return -EINVAL;
937 }
938
939 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
940 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
941 (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
942 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
943 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
944 return -EINVAL;
945 }
946
947 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
948 num_eqs);
949 if (err) {
950 dev_err(&pdev->dev, "Failed to initialize event queues\n");
951 return err;
952 }
953
954 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
955 num_cqs);
956 if (err) {
957 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
958 goto err_cqs_init;
959 }
960
961 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
962 num_sdqs);
963 if (err) {
964 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
965 goto err_sdqs_init;
966 }
967
968 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
969 num_rdqs);
970 if (err) {
971 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
972 goto err_rdqs_init;
973 }
974
975 /* We have to poll in command interface until queues are initialized */
976 mlxsw_pci->cmd.nopoll = true;
977 return 0;
978
979 err_rdqs_init:
980 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
981 err_sdqs_init:
982 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
983 err_cqs_init:
984 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
985 return err;
986 }
987
988 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
989 {
990 mlxsw_pci->cmd.nopoll = false;
991 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
992 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
993 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
994 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
995 }
996
997 static void
998 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
999 char *mbox, int index,
1000 const struct mlxsw_swid_config *swid)
1001 {
1002 u8 mask = 0;
1003
1004 if (swid->used_type) {
1005 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1006 mbox, index, swid->type);
1007 mask |= 1;
1008 }
1009 if (swid->used_properties) {
1010 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1011 mbox, index, swid->properties);
1012 mask |= 2;
1013 }
1014 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1015 }
1016
1017 static int mlxsw_pci_resources_query(struct mlxsw_pci *mlxsw_pci, char *mbox,
1018 struct mlxsw_res *res,
1019 u8 query_enabled)
1020 {
1021 int index, i;
1022 u64 data;
1023 u16 id;
1024 int err;
1025
1026 /* Not all the versions support resources query */
1027 if (!query_enabled)
1028 return 0;
1029
1030 mlxsw_cmd_mbox_zero(mbox);
1031
1032 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES;
1033 index++) {
1034 err = mlxsw_cmd_query_resources(mlxsw_pci->core, mbox, index);
1035 if (err)
1036 return err;
1037
1038 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) {
1039 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i);
1040 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i);
1041
1042 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID)
1043 return 0;
1044
1045 mlxsw_res_parse(res, id, data);
1046 }
1047 }
1048
1049 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1050 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1051 */
1052 return -EIO;
1053 }
1054
1055 static int
1056 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1057 const struct mlxsw_config_profile *profile,
1058 struct mlxsw_res *res)
1059 {
1060 u64 single_size, double_size, linear_size;
1061 int err;
1062
1063 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1064 &single_size, &double_size,
1065 &linear_size);
1066 if (err)
1067 return err;
1068
1069 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1070 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1071 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1072
1073 return 0;
1074 }
1075
1076 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1077 const struct mlxsw_config_profile *profile,
1078 struct mlxsw_res *res)
1079 {
1080 int i;
1081 int err;
1082
1083 mlxsw_cmd_mbox_zero(mbox);
1084
1085 if (profile->used_max_vepa_channels) {
1086 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1087 mbox, 1);
1088 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1089 mbox, profile->max_vepa_channels);
1090 }
1091 if (profile->used_max_mid) {
1092 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1093 mbox, 1);
1094 mlxsw_cmd_mbox_config_profile_max_mid_set(
1095 mbox, profile->max_mid);
1096 }
1097 if (profile->used_max_pgt) {
1098 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1099 mbox, 1);
1100 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1101 mbox, profile->max_pgt);
1102 }
1103 if (profile->used_max_system_port) {
1104 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1105 mbox, 1);
1106 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1107 mbox, profile->max_system_port);
1108 }
1109 if (profile->used_max_vlan_groups) {
1110 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1111 mbox, 1);
1112 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1113 mbox, profile->max_vlan_groups);
1114 }
1115 if (profile->used_max_regions) {
1116 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1117 mbox, 1);
1118 mlxsw_cmd_mbox_config_profile_max_regions_set(
1119 mbox, profile->max_regions);
1120 }
1121 if (profile->used_flood_tables) {
1122 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1123 mbox, 1);
1124 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1125 mbox, profile->max_flood_tables);
1126 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1127 mbox, profile->max_vid_flood_tables);
1128 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1129 mbox, profile->max_fid_offset_flood_tables);
1130 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1131 mbox, profile->fid_offset_flood_table_size);
1132 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1133 mbox, profile->max_fid_flood_tables);
1134 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1135 mbox, profile->fid_flood_table_size);
1136 }
1137 if (profile->used_flood_mode) {
1138 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1139 mbox, 1);
1140 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1141 mbox, profile->flood_mode);
1142 }
1143 if (profile->used_max_ib_mc) {
1144 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1145 mbox, 1);
1146 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1147 mbox, profile->max_ib_mc);
1148 }
1149 if (profile->used_max_pkey) {
1150 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1151 mbox, 1);
1152 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1153 mbox, profile->max_pkey);
1154 }
1155 if (profile->used_ar_sec) {
1156 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1157 mbox, 1);
1158 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1159 mbox, profile->ar_sec);
1160 }
1161 if (profile->used_adaptive_routing_group_cap) {
1162 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1163 mbox, 1);
1164 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1165 mbox, profile->adaptive_routing_group_cap);
1166 }
1167 if (MLXSW_RES_VALID(res, KVD_SIZE)) {
1168 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1169 if (err)
1170 return err;
1171
1172 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1173 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1174 MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1175 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1176 1);
1177 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1178 MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1179 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1180 mbox, 1);
1181 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1182 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1183 }
1184
1185 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1186 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1187 &profile->swid_config[i]);
1188
1189 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1190 }
1191
1192 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1193 {
1194 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1195 int err;
1196
1197 mlxsw_cmd_mbox_zero(mbox);
1198 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1199 if (err)
1200 return err;
1201 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1202 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1203 return 0;
1204 }
1205
1206 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1207 u16 num_pages)
1208 {
1209 struct mlxsw_pci_mem_item *mem_item;
1210 int nent = 0;
1211 int i;
1212 int err;
1213
1214 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1215 GFP_KERNEL);
1216 if (!mlxsw_pci->fw_area.items)
1217 return -ENOMEM;
1218 mlxsw_pci->fw_area.count = num_pages;
1219
1220 mlxsw_cmd_mbox_zero(mbox);
1221 for (i = 0; i < num_pages; i++) {
1222 mem_item = &mlxsw_pci->fw_area.items[i];
1223
1224 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1225 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1226 mem_item->size,
1227 &mem_item->mapaddr);
1228 if (!mem_item->buf) {
1229 err = -ENOMEM;
1230 goto err_alloc;
1231 }
1232 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1233 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1234 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1235 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1236 if (err)
1237 goto err_cmd_map_fa;
1238 nent = 0;
1239 mlxsw_cmd_mbox_zero(mbox);
1240 }
1241 }
1242
1243 if (nent) {
1244 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1245 if (err)
1246 goto err_cmd_map_fa;
1247 }
1248
1249 return 0;
1250
1251 err_cmd_map_fa:
1252 err_alloc:
1253 for (i--; i >= 0; i--) {
1254 mem_item = &mlxsw_pci->fw_area.items[i];
1255
1256 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1257 mem_item->buf, mem_item->mapaddr);
1258 }
1259 kfree(mlxsw_pci->fw_area.items);
1260 return err;
1261 }
1262
1263 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1264 {
1265 struct mlxsw_pci_mem_item *mem_item;
1266 int i;
1267
1268 mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1269
1270 for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1271 mem_item = &mlxsw_pci->fw_area.items[i];
1272
1273 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1274 mem_item->buf, mem_item->mapaddr);
1275 }
1276 kfree(mlxsw_pci->fw_area.items);
1277 }
1278
1279 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1280 {
1281 struct mlxsw_pci *mlxsw_pci = dev_id;
1282 struct mlxsw_pci_queue *q;
1283 int i;
1284
1285 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1286 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1287 mlxsw_pci_queue_tasklet_schedule(q);
1288 }
1289 return IRQ_HANDLED;
1290 }
1291
1292 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1293 struct mlxsw_pci_mem_item *mbox)
1294 {
1295 struct pci_dev *pdev = mlxsw_pci->pdev;
1296 int err = 0;
1297
1298 mbox->size = MLXSW_CMD_MBOX_SIZE;
1299 mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1300 &mbox->mapaddr);
1301 if (!mbox->buf) {
1302 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1303 err = -ENOMEM;
1304 }
1305
1306 return err;
1307 }
1308
1309 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1310 struct mlxsw_pci_mem_item *mbox)
1311 {
1312 struct pci_dev *pdev = mlxsw_pci->pdev;
1313
1314 pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1315 mbox->mapaddr);
1316 }
1317
1318 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1319 const struct mlxsw_config_profile *profile,
1320 struct mlxsw_res *res)
1321 {
1322 struct mlxsw_pci *mlxsw_pci = bus_priv;
1323 struct pci_dev *pdev = mlxsw_pci->pdev;
1324 char *mbox;
1325 u16 num_pages;
1326 int err;
1327
1328 mutex_init(&mlxsw_pci->cmd.lock);
1329 init_waitqueue_head(&mlxsw_pci->cmd.wait);
1330
1331 mlxsw_pci->core = mlxsw_core;
1332
1333 mbox = mlxsw_cmd_mbox_alloc();
1334 if (!mbox)
1335 return -ENOMEM;
1336
1337 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1338 if (err)
1339 goto mbox_put;
1340
1341 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1342 if (err)
1343 goto err_out_mbox_alloc;
1344
1345 err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1346 if (err)
1347 goto err_query_fw;
1348
1349 mlxsw_pci->bus_info.fw_rev.major =
1350 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1351 mlxsw_pci->bus_info.fw_rev.minor =
1352 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1353 mlxsw_pci->bus_info.fw_rev.subminor =
1354 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1355
1356 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1357 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1358 err = -EINVAL;
1359 goto err_iface_rev;
1360 }
1361 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1362 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1363 err = -EINVAL;
1364 goto err_doorbell_page_bar;
1365 }
1366
1367 mlxsw_pci->doorbell_offset =
1368 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1369
1370 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1371 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1372 if (err)
1373 goto err_fw_area_init;
1374
1375 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1376 if (err)
1377 goto err_boardinfo;
1378
1379 err = mlxsw_pci_resources_query(mlxsw_pci, mbox, res,
1380 profile->resource_query_enable);
1381 if (err)
1382 goto err_query_resources;
1383
1384 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1385 if (err)
1386 goto err_config_profile;
1387
1388 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1389 if (err)
1390 goto err_aqs_init;
1391
1392 err = request_irq(pci_irq_vector(pdev, 0),
1393 mlxsw_pci_eq_irq_handler, 0,
1394 mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1395 if (err) {
1396 dev_err(&pdev->dev, "IRQ request failed\n");
1397 goto err_request_eq_irq;
1398 }
1399
1400 goto mbox_put;
1401
1402 err_request_eq_irq:
1403 mlxsw_pci_aqs_fini(mlxsw_pci);
1404 err_aqs_init:
1405 err_config_profile:
1406 err_query_resources:
1407 err_boardinfo:
1408 mlxsw_pci_fw_area_fini(mlxsw_pci);
1409 err_fw_area_init:
1410 err_doorbell_page_bar:
1411 err_iface_rev:
1412 err_query_fw:
1413 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1414 err_out_mbox_alloc:
1415 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1416 mbox_put:
1417 mlxsw_cmd_mbox_free(mbox);
1418 return err;
1419 }
1420
1421 static void mlxsw_pci_fini(void *bus_priv)
1422 {
1423 struct mlxsw_pci *mlxsw_pci = bus_priv;
1424
1425 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1426 mlxsw_pci_aqs_fini(mlxsw_pci);
1427 mlxsw_pci_fw_area_fini(mlxsw_pci);
1428 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1429 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1430 }
1431
1432 static struct mlxsw_pci_queue *
1433 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1434 const struct mlxsw_tx_info *tx_info)
1435 {
1436 u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1437
1438 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1439 }
1440
1441 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1442 const struct mlxsw_tx_info *tx_info)
1443 {
1444 struct mlxsw_pci *mlxsw_pci = bus_priv;
1445 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1446
1447 return !mlxsw_pci_queue_elem_info_producer_get(q);
1448 }
1449
1450 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1451 const struct mlxsw_tx_info *tx_info)
1452 {
1453 struct mlxsw_pci *mlxsw_pci = bus_priv;
1454 struct mlxsw_pci_queue *q;
1455 struct mlxsw_pci_queue_elem_info *elem_info;
1456 char *wqe;
1457 int i;
1458 int err;
1459
1460 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1461 err = skb_linearize(skb);
1462 if (err)
1463 return err;
1464 }
1465
1466 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1467 spin_lock_bh(&q->lock);
1468 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1469 if (!elem_info) {
1470 /* queue is full */
1471 err = -EAGAIN;
1472 goto unlock;
1473 }
1474 elem_info->u.sdq.skb = skb;
1475
1476 wqe = elem_info->elem;
1477 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1478 mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1479 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1480
1481 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1482 skb_headlen(skb), DMA_TO_DEVICE);
1483 if (err)
1484 goto unlock;
1485
1486 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1487 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1488
1489 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1490 skb_frag_address(frag),
1491 skb_frag_size(frag),
1492 DMA_TO_DEVICE);
1493 if (err)
1494 goto unmap_frags;
1495 }
1496
1497 /* Set unused sq entries byte count to zero. */
1498 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1499 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1500
1501 /* Everything is set up, ring producer doorbell to get HW going */
1502 q->producer_counter++;
1503 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1504
1505 goto unlock;
1506
1507 unmap_frags:
1508 for (; i >= 0; i--)
1509 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1510 unlock:
1511 spin_unlock_bh(&q->lock);
1512 return err;
1513 }
1514
1515 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1516 u32 in_mod, bool out_mbox_direct,
1517 char *in_mbox, size_t in_mbox_size,
1518 char *out_mbox, size_t out_mbox_size,
1519 u8 *p_status)
1520 {
1521 struct mlxsw_pci *mlxsw_pci = bus_priv;
1522 dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1523 dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1524 bool evreq = mlxsw_pci->cmd.nopoll;
1525 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1526 bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1527 int err;
1528
1529 *p_status = MLXSW_CMD_STATUS_OK;
1530
1531 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1532 if (err)
1533 return err;
1534
1535 if (in_mbox)
1536 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1537 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1538 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1539
1540 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1541 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1542
1543 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1544 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1545
1546 *p_wait_done = false;
1547
1548 wmb(); /* all needs to be written before we write control register */
1549 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1550 MLXSW_PCI_CIR_CTRL_GO_BIT |
1551 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1552 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1553 opcode);
1554
1555 if (!evreq) {
1556 unsigned long end;
1557
1558 end = jiffies + timeout;
1559 do {
1560 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1561
1562 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1563 *p_wait_done = true;
1564 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1565 break;
1566 }
1567 cond_resched();
1568 } while (time_before(jiffies, end));
1569 } else {
1570 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1571 *p_status = mlxsw_pci->cmd.comp.status;
1572 }
1573
1574 err = 0;
1575 if (*p_wait_done) {
1576 if (*p_status)
1577 err = -EIO;
1578 } else {
1579 err = -ETIMEDOUT;
1580 }
1581
1582 if (!err && out_mbox && out_mbox_direct) {
1583 /* Some commands don't use output param as address to mailbox
1584 * but they store output directly into registers. In that case,
1585 * copy registers into mbox buffer.
1586 */
1587 __be32 tmp;
1588
1589 if (!evreq) {
1590 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1591 CIR_OUT_PARAM_HI));
1592 memcpy(out_mbox, &tmp, sizeof(tmp));
1593 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1594 CIR_OUT_PARAM_LO));
1595 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1596 }
1597 } else if (!err && out_mbox) {
1598 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1599 }
1600
1601 mutex_unlock(&mlxsw_pci->cmd.lock);
1602
1603 return err;
1604 }
1605
1606 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1607 const struct pci_device_id *id)
1608 {
1609 unsigned long end;
1610
1611 mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1612 if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1613 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1614 return 0;
1615 }
1616
1617 /* Reset needs to be written before we read control register, and
1618 * we must wait for the HW to become responsive once again
1619 */
1620 wmb();
1621 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1622
1623 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1624 do {
1625 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1626
1627 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1628 break;
1629 cond_resched();
1630 } while (time_before(jiffies, end));
1631 return 0;
1632 }
1633
1634 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1635 {
1636 pci_free_irq_vectors(mlxsw_pci->pdev);
1637 }
1638
1639 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1640 {
1641 int err;
1642
1643 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1644 if (err < 0)
1645 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1646 return err;
1647 }
1648
1649 static void mlxsw_pci_reset(void *bus_priv)
1650 {
1651 struct mlxsw_pci *mlxsw_pci = bus_priv;
1652
1653 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1654 mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1655 mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1656 }
1657
1658 static const struct mlxsw_bus mlxsw_pci_bus = {
1659 .kind = "pci",
1660 .init = mlxsw_pci_init,
1661 .fini = mlxsw_pci_fini,
1662 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy,
1663 .skb_transmit = mlxsw_pci_skb_transmit,
1664 .cmd_exec = mlxsw_pci_cmd_exec,
1665 .features = MLXSW_BUS_F_TXRX,
1666 .reset = mlxsw_pci_reset,
1667 };
1668
1669 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1670 {
1671 const char *driver_name = pdev->driver->name;
1672 struct mlxsw_pci *mlxsw_pci;
1673 int err;
1674
1675 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1676 if (!mlxsw_pci)
1677 return -ENOMEM;
1678
1679 err = pci_enable_device(pdev);
1680 if (err) {
1681 dev_err(&pdev->dev, "pci_enable_device failed\n");
1682 goto err_pci_enable_device;
1683 }
1684
1685 err = pci_request_regions(pdev, driver_name);
1686 if (err) {
1687 dev_err(&pdev->dev, "pci_request_regions failed\n");
1688 goto err_pci_request_regions;
1689 }
1690
1691 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1692 if (!err) {
1693 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1694 if (err) {
1695 dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1696 goto err_pci_set_dma_mask;
1697 }
1698 } else {
1699 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1700 if (err) {
1701 dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1702 goto err_pci_set_dma_mask;
1703 }
1704 }
1705
1706 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1707 dev_err(&pdev->dev, "invalid PCI region size\n");
1708 err = -EINVAL;
1709 goto err_pci_resource_len_check;
1710 }
1711
1712 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1713 pci_resource_len(pdev, 0));
1714 if (!mlxsw_pci->hw_addr) {
1715 dev_err(&pdev->dev, "ioremap failed\n");
1716 err = -EIO;
1717 goto err_ioremap;
1718 }
1719 pci_set_master(pdev);
1720
1721 mlxsw_pci->pdev = pdev;
1722 pci_set_drvdata(pdev, mlxsw_pci);
1723
1724 err = mlxsw_pci_sw_reset(mlxsw_pci, id);
1725 if (err) {
1726 dev_err(&pdev->dev, "Software reset failed\n");
1727 goto err_sw_reset;
1728 }
1729
1730 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1731 if (err < 0) {
1732 dev_err(&pdev->dev, "MSI-X init failed\n");
1733 goto err_msix_init;
1734 }
1735
1736 mlxsw_pci->bus_info.device_kind = driver_name;
1737 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1738 mlxsw_pci->bus_info.dev = &pdev->dev;
1739 mlxsw_pci->id = id;
1740
1741 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1742 &mlxsw_pci_bus, mlxsw_pci, false,
1743 NULL);
1744 if (err) {
1745 dev_err(&pdev->dev, "cannot register bus device\n");
1746 goto err_bus_device_register;
1747 }
1748
1749 return 0;
1750
1751 err_bus_device_register:
1752 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1753 err_msix_init:
1754 err_sw_reset:
1755 iounmap(mlxsw_pci->hw_addr);
1756 err_ioremap:
1757 err_pci_resource_len_check:
1758 err_pci_set_dma_mask:
1759 pci_release_regions(pdev);
1760 err_pci_request_regions:
1761 pci_disable_device(pdev);
1762 err_pci_enable_device:
1763 kfree(mlxsw_pci);
1764 return err;
1765 }
1766
1767 static void mlxsw_pci_remove(struct pci_dev *pdev)
1768 {
1769 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1770
1771 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1772 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1773 iounmap(mlxsw_pci->hw_addr);
1774 pci_release_regions(mlxsw_pci->pdev);
1775 pci_disable_device(mlxsw_pci->pdev);
1776 kfree(mlxsw_pci);
1777 }
1778
1779 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1780 {
1781 pci_driver->probe = mlxsw_pci_probe;
1782 pci_driver->remove = mlxsw_pci_remove;
1783 return pci_register_driver(pci_driver);
1784 }
1785 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1786
1787 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1788 {
1789 pci_unregister_driver(pci_driver);
1790 }
1791 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1792
1793 static int __init mlxsw_pci_module_init(void)
1794 {
1795 return 0;
1796 }
1797
1798 static void __exit mlxsw_pci_module_exit(void)
1799 {
1800 }
1801
1802 module_init(mlxsw_pci_module_init);
1803 module_exit(mlxsw_pci_module_exit);
1804
1805 MODULE_LICENSE("Dual BSD/GPL");
1806 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1807 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
CRIS linux kernel tree