drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
   3  * Copyright (c) 2015-2016 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _MLXSW_PCI_HW_H
  36 #define _MLXSW_PCI_HW_H
  37
  38 #include <linux/bitops.h>
  39
  40 #include "item.h"
  41
  42 #define MLXSW_PCI_BAR0_SIZE             (1024 * 1024) /* 1MB */
  43 #define MLXSW_PCI_PAGE_SIZE             4096
  44
  45 #define MLXSW_PCI_CIR_BASE                      0x71000
  46 #define MLXSW_PCI_CIR_IN_PARAM_HI               MLXSW_PCI_CIR_BASE
  47 #define MLXSW_PCI_CIR_IN_PARAM_LO               (MLXSW_PCI_CIR_BASE + 0x04)
  48 #define MLXSW_PCI_CIR_IN_MODIFIER               (MLXSW_PCI_CIR_BASE + 0x08)
  49 #define MLXSW_PCI_CIR_OUT_PARAM_HI              (MLXSW_PCI_CIR_BASE + 0x0C)
  50 #define MLXSW_PCI_CIR_OUT_PARAM_LO              (MLXSW_PCI_CIR_BASE + 0x10)
  51 #define MLXSW_PCI_CIR_TOKEN                     (MLXSW_PCI_CIR_BASE + 0x14)
  52 #define MLXSW_PCI_CIR_CTRL                      (MLXSW_PCI_CIR_BASE + 0x18)
  53 #define MLXSW_PCI_CIR_CTRL_GO_BIT               BIT(23)
  54 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT            BIT(22)
  55 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT     12
  56 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT         24
  57 #define MLXSW_PCI_CIR_TIMEOUT_MSECS             1000
  58
  59 #define MLXSW_PCI_SW_RESET                      0xF0010
  60 #define MLXSW_PCI_SW_RESET_RST_BIT              BIT(0)
  61 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS        5000
  62 #define MLXSW_PCI_SW_RESET_WAIT_MSECS           100
  63 #define MLXSW_PCI_FW_READY                      0xA1844
  64 #define MLXSW_PCI_FW_READY_MASK                 0xFFFF
  65 #define MLXSW_PCI_FW_READY_MAGIC                0x5E
  66
  67 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET           0x000
  68 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET           0x200
  69 #define MLXSW_PCI_DOORBELL_CQ_OFFSET            0x400
  70 #define MLXSW_PCI_DOORBELL_EQ_OFFSET            0x600
  71 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET        0x800
  72 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET        0xA00
  73
  74 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)    \
  75         ((offset) + (type_offset) + (num) * 4)
  76
  77 #define MLXSW_PCI_CQS_MAX       96
  78 #define MLXSW_PCI_EQS_COUNT     2
  79 #define MLXSW_PCI_EQ_ASYNC_NUM  0
  80 #define MLXSW_PCI_EQ_COMP_NUM   1
  81
  82 #define MLXSW_PCI_AQ_PAGES      8
  83 #define MLXSW_PCI_AQ_SIZE       (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
  84 #define MLXSW_PCI_WQE_SIZE      32 /* 32 bytes per element */
  85 #define MLXSW_PCI_CQE_SIZE      16 /* 16 bytes per element */
  86 #define MLXSW_PCI_EQE_SIZE      16 /* 16 bytes per element */
  87 #define MLXSW_PCI_WQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
  88 #define MLXSW_PCI_CQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE)
  89 #define MLXSW_PCI_EQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
  90 #define MLXSW_PCI_EQE_UPDATE_COUNT      0x80
  91
  92 #define MLXSW_PCI_WQE_SG_ENTRIES        3
  93 #define MLXSW_PCI_WQE_TYPE_ETHERNET     0xA
  94
  95 /* pci_wqe_c
  96  * If set it indicates that a completion should be reported upon
  97  * execution of this descriptor.
  98  */
  99 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
 100
 101 /* pci_wqe_lp
 102  * Local Processing, set if packet should be processed by the local
 103  * switch hardware:
 104  * For Ethernet EMAD (Direct Route and non Direct Route) -
 105  * must be set if packet destination is local device
 106  * For InfiniBand CTL - must be set if packet destination is local device
 107  * Otherwise it must be clear
 108  * Local Process packets must not exceed the size of 2K (including payload
 109  * and headers).
 110  */
 111 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
 112
 113 /* pci_wqe_type
 114  * Packet type.
 115  */
 116 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
 117
 118 /* pci_wqe_byte_count
 119  * Size of i-th scatter/gather entry, 0 if entry is unused.
 120  */
 121 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
 122
 123 /* pci_wqe_address
 124  * Physical address of i-th scatter/gather entry.
 125  * Gather Entries must be 2Byte aligned.
 126  */
 127 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
 128
 129 /* pci_cqe_lag
 130  * Packet arrives from a port which is a LAG
 131  */
 132 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1);
 133
 134 /* pci_cqe_system_port/lag_id
 135  * When lag=0: System port on which the packet was received
 136  * When lag=1:
 137  * bits [15:4] LAG ID on which the packet was received
 138  * bits [3:0] sub_port on which the packet was received
 139  */
 140 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
 141 MLXSW_ITEM32(pci, cqe, lag_id, 0x00, 4, 12);
 142 MLXSW_ITEM32(pci, cqe, lag_port_index, 0x00, 0, 4);
 143
 144 /* pci_cqe_wqe_counter
 145  * WQE count of the WQEs completed on the associated dqn
 146  */
 147 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
 148
 149 /* pci_cqe_byte_count
 150  * Byte count of received packets including additional two
 151  * Reserved Bytes that are append to the end of the frame.
 152  * Reserved for Send CQE.
 153  */
 154 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
 155
 156 /* pci_cqe_trap_id
 157  * Trap ID that captured the packet.
 158  */
 159 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
 160
 161 /* pci_cqe_crc
 162  * Length include CRC. Indicates the length field includes
 163  * the packet's CRC.
 164  */
 165 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1);
 166
 167 /* pci_cqe_e
 168  * CQE with Error.
 169  */
 170 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1);
 171
 172 /* pci_cqe_sr
 173  * 1 - Send Queue
 174  * 0 - Receive Queue
 175  */
 176 MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1);
 177
 178 /* pci_cqe_dqn
 179  * Descriptor Queue (DQ) Number.
 180  */
 181 MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5);
 182
 183 /* pci_cqe_owner
 184  * Ownership bit.
 185  */
 186 MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1);
 187
 188 /* pci_eqe_event_type
 189  * Event type.
 190  */
 191 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
 192 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP   0x00
 193 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD    0x0A
 194
 195 /* pci_eqe_event_sub_type
 196  * Event type.
 197  */
 198 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
 199
 200 /* pci_eqe_cqn
 201  * Completion Queue that triggeret this EQE.
 202  */
 203 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
 204
 205 /* pci_eqe_owner
 206  * Ownership bit.
 207  */
 208 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
 209
 210 /* pci_eqe_cmd_token
 211  * Command completion event - token
 212  */
 213 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
 214
 215 /* pci_eqe_cmd_status
 216  * Command completion event - status
 217  */
 218 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
 219
 220 /* pci_eqe_cmd_out_param_h
 221  * Command completion event - output parameter - higher part
 222  */
 223 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
 224
 225 /* pci_eqe_cmd_out_param_l
 226  * Command completion event - output parameter - lower part
 227  */
 228 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
 229
 230 #endif