drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_flex_keys.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_flex_keys.h
   3  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2017 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _MLXSW_SPECTRUM_ACL_FLEX_KEYS_H
  36 #define _MLXSW_SPECTRUM_ACL_FLEX_KEYS_H
  37
  38 #include "core_acl_flex_keys.h"
  39
  40 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_dmac[] = {
  41         MLXSW_AFK_ELEMENT_INST_BUF(DMAC, 0x00, 6),
  42         MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
  43         MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
  44         MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
  45 };
  46
  47 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac[] = {
  48         MLXSW_AFK_ELEMENT_INST_BUF(SMAC, 0x00, 6),
  49         MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
  50         MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
  51         MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
  52 };
  53
  54 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac_ex[] = {
  55         MLXSW_AFK_ELEMENT_INST_BUF(SMAC, 0x02, 6),
  56         MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x0C, 0, 16),
  57 };
  58
  59 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_sip[] = {
  60         MLXSW_AFK_ELEMENT_INST_U32(SRC_IP4, 0x00, 0, 32),
  61         MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
  62         MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
  63 };
  64
  65 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_dip[] = {
  66         MLXSW_AFK_ELEMENT_INST_U32(DST_IP4, 0x00, 0, 32),
  67         MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
  68         MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 16),
  69 };
  70
  71 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4[] = {
  72         MLXSW_AFK_ELEMENT_INST_U32(SRC_IP4, 0x00, 0, 32),
  73         MLXSW_AFK_ELEMENT_INST_U32(IP_ECN, 0x04, 4, 2),
  74         MLXSW_AFK_ELEMENT_INST_U32(IP_TTL_, 0x04, 24, 8),
  75         MLXSW_AFK_ELEMENT_INST_U32(IP_DSCP, 0x08, 0, 6),
  76         MLXSW_AFK_ELEMENT_INST_U32(TCP_FLAGS, 0x08, 8, 9), /* TCP_CONTROL+TCP_ECN */
  77 };
  78
  79 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_ex[] = {
  80         MLXSW_AFK_ELEMENT_INST_U32(VID, 0x00, 0, 12),
  81         MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 29, 3),
  82         MLXSW_AFK_ELEMENT_INST_U32(SRC_L4_PORT, 0x08, 0, 16),
  83         MLXSW_AFK_ELEMENT_INST_U32(DST_L4_PORT, 0x0C, 0, 16),
  84 };
  85
  86 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_dip[] = {
  87         MLXSW_AFK_ELEMENT_INST_BUF(DST_IP6_LO, 0x00, 8),
  88 };
  89
  90 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_ex1[] = {
  91         MLXSW_AFK_ELEMENT_INST_BUF(DST_IP6_HI, 0x00, 8),
  92         MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
  93 };
  94
  95 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip[] = {
  96         MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP6_LO, 0x00, 8),
  97 };
  98
  99 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip_ex[] = {
 100         MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP6_HI, 0x00, 8),
 101 };
 102
 103 static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_packet_type[] = {
 104         MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x00, 0, 16),
 105 };
 106
 107 static const struct mlxsw_afk_block mlxsw_sp_afk_blocks[] = {
 108         MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_l2_dmac),
 109         MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_l2_smac),
 110         MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_l2_smac_ex),
 111         MLXSW_AFK_BLOCK(0x30, mlxsw_sp_afk_element_info_ipv4_sip),
 112         MLXSW_AFK_BLOCK(0x31, mlxsw_sp_afk_element_info_ipv4_dip),
 113         MLXSW_AFK_BLOCK(0x32, mlxsw_sp_afk_element_info_ipv4),
 114         MLXSW_AFK_BLOCK(0x33, mlxsw_sp_afk_element_info_ipv4_ex),
 115         MLXSW_AFK_BLOCK(0x60, mlxsw_sp_afk_element_info_ipv6_dip),
 116         MLXSW_AFK_BLOCK(0x65, mlxsw_sp_afk_element_info_ipv6_ex1),
 117         MLXSW_AFK_BLOCK(0x62, mlxsw_sp_afk_element_info_ipv6_sip),
 118         MLXSW_AFK_BLOCK(0x63, mlxsw_sp_afk_element_info_ipv6_sip_ex),
 119         MLXSW_AFK_BLOCK(0xB0, mlxsw_sp_afk_element_info_packet_type),
 120 };
 121
 122 #define MLXSW_SP_AFK_BLOCKS_COUNT ARRAY_SIZE(mlxsw_sp_afk_blocks)
 123
 124 #endif