| blob | c63c76381af66fcd70c6f3972329c8a38793c6be |
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 ***************************************************************************
19 */
21 #ifndef _SMSC9420_H
22 #define _SMSC9420_H
24 #define TX_RING_SIZE (32)
25 #define RX_RING_SIZE (128)
27 /* interrupt deassertion in multiples of 10us */
28 #define INT_DEAS_TIME (50)
30 #define NAPI_WEIGHT (64)
31 #define SMSC_BAR (3)
33 #ifdef __BIG_ENDIAN
34 /* Register set is duplicated for BE at an offset of 0x200 */
35 #define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
36 #else
37 #define LAN9420_CPSR_ENDIAN_OFFSET (0)
38 #endif
40 #define PCI_VENDOR_ID_9420 (0x1055)
41 #define PCI_DEVICE_ID_9420 (0xE420)
43 #define LAN_REGISTER_EXTENT (0x400)
45 #define SMSC9420_EEPROM_SIZE ((u32)11)
46 #define SMSC9420_EEPROM_MAGIC (0x9420)
48 #define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
50 /***********************************************/
51 /* DMA Controller Control and Status Registers */
52 /***********************************************/
53 #define BUS_MODE (0x00)
54 #define BUS_MODE_SWR_ (BIT(0))
55 #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
56 #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
57 #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
58 #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
59 #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
60 #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
61 #define BUS_MODE_DBO_ (BIT(20))
63 #define TX_POLL_DEMAND (0x04)
65 #define RX_POLL_DEMAND (0x08)
67 #define RX_BASE_ADDR (0x0C)
69 #define TX_BASE_ADDR (0x10)
71 #define DMAC_STATUS (0x14)
72 #define DMAC_STS_TS_ (7 << 20)
73 #define DMAC_STS_RS_ (7 << 17)
74 #define DMAC_STS_NIS_ (BIT(16))
75 #define DMAC_STS_AIS_ (BIT(15))
76 #define DMAC_STS_RWT_ (BIT(9))
77 #define DMAC_STS_RXPS_ (BIT(8))
78 #define DMAC_STS_RXBU_ (BIT(7))
79 #define DMAC_STS_RX_ (BIT(6))
80 #define DMAC_STS_TXUNF_ (BIT(5))
81 #define DMAC_STS_TXBU_ (BIT(2))
82 #define DMAC_STS_TXPS_ (BIT(1))
83 #define DMAC_STS_TX_ (BIT(0))
85 #define DMAC_CONTROL (0x18)
86 #define DMAC_CONTROL_TTM_ (BIT(22))
87 #define DMAC_CONTROL_SF_ (BIT(21))
88 #define DMAC_CONTROL_ST_ (BIT(13))
89 #define DMAC_CONTROL_OSF_ (BIT(2))
90 #define DMAC_CONTROL_SR_ (BIT(1))
92 #define DMAC_INTR_ENA (0x1C)
93 #define DMAC_INTR_ENA_NIS_ (BIT(16))
94 #define DMAC_INTR_ENA_AIS_ (BIT(15))
95 #define DMAC_INTR_ENA_RWT_ (BIT(9))
96 #define DMAC_INTR_ENA_RXPS_ (BIT(8))
97 #define DMAC_INTR_ENA_RXBU_ (BIT(7))
98 #define DMAC_INTR_ENA_RX_ (BIT(6))
99 #define DMAC_INTR_ENA_TXBU_ (BIT(2))
100 #define DMAC_INTR_ENA_TXPS_ (BIT(1))
101 #define DMAC_INTR_ENA_TX_ (BIT(0))
103 #define MISS_FRAME_CNTR (0x20)
105 #define TX_BUFF_ADDR (0x50)
107 #define RX_BUFF_ADDR (0x54)
109 /* Transmit Descriptor Bit Defs */
110 #define TDES0_OWN_ (0x80000000)
111 #define TDES0_ERROR_SUMMARY_ (0x00008000)
112 #define TDES0_LOSS_OF_CARRIER_ (0x00000800)
113 #define TDES0_NO_CARRIER_ (0x00000400)
114 #define TDES0_LATE_COLLISION_ (0x00000200)
115 #define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100)
116 #define TDES0_HEARTBEAT_FAIL_ (0x00000080)
117 #define TDES0_COLLISION_COUNT_MASK_ (0x00000078)
118 #define TDES0_COLLISION_COUNT_SHFT_ (3)
119 #define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004)
120 #define TDES0_DEFERRED_ (0x00000001)
122 #define TDES1_IC_ 0x80000000
123 #define TDES1_LS_ 0x40000000
124 #define TDES1_FS_ 0x20000000
125 #define TDES1_TXCSEN_ 0x08000000
126 #define TDES1_TER_ (BIT(25))
127 #define TDES1_TCH_ 0x01000000
129 /* Receive Descriptor 0 Bit Defs */
130 #define RDES0_OWN_ (0x80000000)
131 #define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000)
132 #define RDES0_FRAME_LENGTH_SHFT_ (16)
133 #define RDES0_ERROR_SUMMARY_ (0x00008000)
134 #define RDES0_DESCRIPTOR_ERROR_ (0x00004000)
135 #define RDES0_LENGTH_ERROR_ (0x00001000)
136 #define RDES0_RUNT_FRAME_ (0x00000800)
137 #define RDES0_MULTICAST_FRAME_ (0x00000400)
138 #define RDES0_FIRST_DESCRIPTOR_ (0x00000200)
139 #define RDES0_LAST_DESCRIPTOR_ (0x00000100)
140 #define RDES0_FRAME_TOO_LONG_ (0x00000080)
141 #define RDES0_COLLISION_SEEN_ (0x00000040)
142 #define RDES0_FRAME_TYPE_ (0x00000020)
143 #define RDES0_WATCHDOG_TIMEOUT_ (0x00000010)
144 #define RDES0_MII_ERROR_ (0x00000008)
145 #define RDES0_DRIBBLING_BIT_ (0x00000004)
146 #define RDES0_CRC_ERROR_ (0x00000002)
148 /* Receive Descriptor 1 Bit Defs */
149 #define RDES1_RER_ (0x02000000)
151 /***********************************************/
152 /* MAC Control and Status Registers */
153 /***********************************************/
154 #define MAC_CR (0x80)
155 #define MAC_CR_RXALL_ (0x80000000)
156 #define MAC_CR_DIS_RXOWN_ (0x00800000)
157 #define MAC_CR_LOOPBK_ (0x00200000)
158 #define MAC_CR_FDPX_ (0x00100000)
159 #define MAC_CR_MCPAS_ (0x00080000)
160 #define MAC_CR_PRMS_ (0x00040000)
161 #define MAC_CR_INVFILT_ (0x00020000)
162 #define MAC_CR_PASSBAD_ (0x00010000)
163 #define MAC_CR_HFILT_ (0x00008000)
164 #define MAC_CR_HPFILT_ (0x00002000)
165 #define MAC_CR_LCOLL_ (0x00001000)
166 #define MAC_CR_DIS_BCAST_ (0x00000800)
167 #define MAC_CR_DIS_RTRY_ (0x00000400)
168 #define MAC_CR_PADSTR_ (0x00000100)
169 #define MAC_CR_BOLMT_MSK (0x000000C0)
170 #define MAC_CR_MFCHK_ (0x00000020)
171 #define MAC_CR_TXEN_ (0x00000008)
172 #define MAC_CR_RXEN_ (0x00000004)
174 #define ADDRH (0x84)
176 #define ADDRL (0x88)
178 #define HASHH (0x8C)
180 #define HASHL (0x90)
182 #define MII_ACCESS (0x94)
183 #define MII_ACCESS_MII_BUSY_ (0x00000001)
184 #define MII_ACCESS_MII_WRITE_ (0x00000002)
185 #define MII_ACCESS_MII_READ_ (0x00000000)
186 #define MII_ACCESS_INDX_MSK_ (0x000007C0)
187 #define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0)
188 #define MII_ACCESS_INDX_SHFT_CNT (6)
189 #define MII_ACCESS_PHYADDR_SHFT_CNT (11)
191 #define MII_DATA (0x98)
193 #define FLOW (0x9C)
195 #define VLAN1 (0xA0)
197 #define VLAN2 (0xA4)
199 #define WUFF (0xA8)
201 #define WUCSR (0xAC)
203 #define COE_CR (0xB0)
204 #define TX_COE_EN (0x00010000)
205 #define RX_COE_MODE (0x00000002)
206 #define RX_COE_EN (0x00000001)
208 /***********************************************/
209 /* System Control and Status Registers */
210 /***********************************************/
211 #define ID_REV (0xC0)
213 #define INT_CTL (0xC4)
214 #define INT_CTL_SW_INT_EN_ (0x00008000)
215 #define INT_CTL_SBERR_INT_EN_ (1 << 12)
216 #define INT_CTL_MBERR_INT_EN_ (1 << 13)
217 #define INT_CTL_GPT_INT_EN_ (0x00000008)
218 #define INT_CTL_PHY_INT_EN_ (0x00000004)
219 #define INT_CTL_WAKE_INT_EN_ (0x00000002)
221 #define INT_STAT (0xC8)
222 #define INT_STAT_SW_INT_ (1 << 15)
223 #define INT_STAT_MBERR_INT_ (1 << 13)
224 #define INT_STAT_SBERR_INT_ (1 << 12)
225 #define INT_STAT_GPT_INT_ (1 << 3)
226 #define INT_STAT_PHY_INT_ (0x00000004)
227 #define INT_STAT_WAKE_INT_ (0x00000002)
228 #define INT_STAT_DMAC_INT_ (0x00000001)
230 #define INT_CFG (0xCC)
231 #define INT_CFG_IRQ_INT_ (0x00080000)
232 #define INT_CFG_IRQ_EN_ (0x00040000)
233 #define INT_CFG_INT_DEAS_CLR_ (0x00000200)
234 #define INT_CFG_INT_DEAS_MASK (0x000000FF)
236 #define GPIO_CFG (0xD0)
237 #define GPIO_CFG_LED_3_ (0x40000000)
238 #define GPIO_CFG_LED_2_ (0x20000000)
239 #define GPIO_CFG_LED_1_ (0x10000000)
240 #define GPIO_CFG_EEPR_EN_ (0x00700000)
242 #define GPT_CFG (0xD4)
243 #define GPT_CFG_TIMER_EN_ (0x20000000)
245 #define GPT_CNT (0xD8)
247 #define BUS_CFG (0xDC)
248 #define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25)
249 #define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25)
250 #define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25)
251 #define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25)
253 #define PMT_CTRL (0xE0)
255 #define FREE_RUN (0xF4)
257 #define E2P_CMD (0xF8)
258 #define E2P_CMD_EPC_BUSY_ (0x80000000)
259 #define E2P_CMD_EPC_CMD_ (0x70000000)
260 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
261 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
262 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
263 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
264 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
265 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
266 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
267 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
268 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200)
269 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100)
270 #define E2P_CMD_EPC_ADDR_ (0x000000FF)
272 #define E2P_DATA (0xFC)
273 #define E2P_DATA_EEPROM_DATA_ (0x000000FF)