drivers/net/ethernet/stmicro/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   The full GNU General Public License is included in this distribution in
  16   the file called "COPYING".
  17
  18   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  19 *******************************************************************************/
  20
  21 #ifndef __COMMON_H__
  22 #define __COMMON_H__
  23
  24 #include <linux/etherdevice.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/stmmac.h>
  27 #include <linux/phy.h>
  28 #include <linux/module.h>
  29 #if IS_ENABLED(CONFIG_VLAN_8021Q)
  30 #define STMMAC_VLAN_TAG_USED
  31 #include <linux/if_vlan.h>
  32 #endif
  33
  34 #include "descs.h"
  35 #include "mmc.h"
  36
  37 /* Synopsys Core versions */
  38 #define DWMAC_CORE_3_40 0x34
  39 #define DWMAC_CORE_3_50 0x35
  40 #define DWMAC_CORE_4_00 0x40
  41 #define STMMAC_CHAN0    0       /* Always supported and default for all chips */
  42
  43 /* These need to be power of two, and >= 4 */
  44 #define DMA_TX_SIZE 512
  45 #define DMA_RX_SIZE 512
  46 #define STMMAC_GET_ENTRY(x, size)       ((x + 1) & (size - 1))
  47
  48 #undef FRAME_FILTER_DEBUG
  49 /* #define FRAME_FILTER_DEBUG */
  50
  51 /* Extra statistic and debug information exposed by ethtool */
  52 struct stmmac_extra_stats {
  53         /* Transmit errors */
  54         unsigned long tx_underflow ____cacheline_aligned;
  55         unsigned long tx_carrier;
  56         unsigned long tx_losscarrier;
  57         unsigned long vlan_tag;
  58         unsigned long tx_deferred;
  59         unsigned long tx_vlan;
  60         unsigned long tx_jabber;
  61         unsigned long tx_frame_flushed;
  62         unsigned long tx_payload_error;
  63         unsigned long tx_ip_header_error;
  64         /* Receive errors */
  65         unsigned long rx_desc;
  66         unsigned long sa_filter_fail;
  67         unsigned long overflow_error;
  68         unsigned long ipc_csum_error;
  69         unsigned long rx_collision;
  70         unsigned long rx_crc_errors;
  71         unsigned long dribbling_bit;
  72         unsigned long rx_length;
  73         unsigned long rx_mii;
  74         unsigned long rx_multicast;
  75         unsigned long rx_gmac_overflow;
  76         unsigned long rx_watchdog;
  77         unsigned long da_rx_filter_fail;
  78         unsigned long sa_rx_filter_fail;
  79         unsigned long rx_missed_cntr;
  80         unsigned long rx_overflow_cntr;
  81         unsigned long rx_vlan;
  82         /* Tx/Rx IRQ error info */
  83         unsigned long tx_undeflow_irq;
  84         unsigned long tx_process_stopped_irq;
  85         unsigned long tx_jabber_irq;
  86         unsigned long rx_overflow_irq;
  87         unsigned long rx_buf_unav_irq;
  88         unsigned long rx_process_stopped_irq;
  89         unsigned long rx_watchdog_irq;
  90         unsigned long tx_early_irq;
  91         unsigned long fatal_bus_error_irq;
  92         /* Tx/Rx IRQ Events */
  93         unsigned long rx_early_irq;
  94         unsigned long threshold;
  95         unsigned long tx_pkt_n;
  96         unsigned long rx_pkt_n;
  97         unsigned long normal_irq_n;
  98         unsigned long rx_normal_irq_n;
  99         unsigned long napi_poll;
 100         unsigned long tx_normal_irq_n;
 101         unsigned long tx_clean;
 102         unsigned long tx_set_ic_bit;
 103         unsigned long irq_receive_pmt_irq_n;
 104         /* MMC info */
 105         unsigned long mmc_tx_irq_n;
 106         unsigned long mmc_rx_irq_n;
 107         unsigned long mmc_rx_csum_offload_irq_n;
 108         /* EEE */
 109         unsigned long irq_tx_path_in_lpi_mode_n;
 110         unsigned long irq_tx_path_exit_lpi_mode_n;
 111         unsigned long irq_rx_path_in_lpi_mode_n;
 112         unsigned long irq_rx_path_exit_lpi_mode_n;
 113         unsigned long phy_eee_wakeup_error_n;
 114         /* Extended RDES status */
 115         unsigned long ip_hdr_err;
 116         unsigned long ip_payload_err;
 117         unsigned long ip_csum_bypassed;
 118         unsigned long ipv4_pkt_rcvd;
 119         unsigned long ipv6_pkt_rcvd;
 120         unsigned long no_ptp_rx_msg_type_ext;
 121         unsigned long ptp_rx_msg_type_sync;
 122         unsigned long ptp_rx_msg_type_follow_up;
 123         unsigned long ptp_rx_msg_type_delay_req;
 124         unsigned long ptp_rx_msg_type_delay_resp;
 125         unsigned long ptp_rx_msg_type_pdelay_req;
 126         unsigned long ptp_rx_msg_type_pdelay_resp;
 127         unsigned long ptp_rx_msg_type_pdelay_follow_up;
 128         unsigned long ptp_rx_msg_type_announce;
 129         unsigned long ptp_rx_msg_type_management;
 130         unsigned long ptp_rx_msg_pkt_reserved_type;
 131         unsigned long ptp_frame_type;
 132         unsigned long ptp_ver;
 133         unsigned long timestamp_dropped;
 134         unsigned long av_pkt_rcvd;
 135         unsigned long av_tagged_pkt_rcvd;
 136         unsigned long vlan_tag_priority_val;
 137         unsigned long l3_filter_match;
 138         unsigned long l4_filter_match;
 139         unsigned long l3_l4_filter_no_match;
 140         /* PCS */
 141         unsigned long irq_pcs_ane_n;
 142         unsigned long irq_pcs_link_n;
 143         unsigned long irq_rgmii_n;
 144         unsigned long pcs_link;
 145         unsigned long pcs_duplex;
 146         unsigned long pcs_speed;
 147         /* debug register */
 148         unsigned long mtl_tx_status_fifo_full;
 149         unsigned long mtl_tx_fifo_not_empty;
 150         unsigned long mmtl_fifo_ctrl;
 151         unsigned long mtl_tx_fifo_read_ctrl_write;
 152         unsigned long mtl_tx_fifo_read_ctrl_wait;
 153         unsigned long mtl_tx_fifo_read_ctrl_read;
 154         unsigned long mtl_tx_fifo_read_ctrl_idle;
 155         unsigned long mac_tx_in_pause;
 156         unsigned long mac_tx_frame_ctrl_xfer;
 157         unsigned long mac_tx_frame_ctrl_idle;
 158         unsigned long mac_tx_frame_ctrl_wait;
 159         unsigned long mac_tx_frame_ctrl_pause;
 160         unsigned long mac_gmii_tx_proto_engine;
 161         unsigned long mtl_rx_fifo_fill_level_full;
 162         unsigned long mtl_rx_fifo_fill_above_thresh;
 163         unsigned long mtl_rx_fifo_fill_below_thresh;
 164         unsigned long mtl_rx_fifo_fill_level_empty;
 165         unsigned long mtl_rx_fifo_read_ctrl_flush;
 166         unsigned long mtl_rx_fifo_read_ctrl_read_data;
 167         unsigned long mtl_rx_fifo_read_ctrl_status;
 168         unsigned long mtl_rx_fifo_read_ctrl_idle;
 169         unsigned long mtl_rx_fifo_ctrl_active;
 170         unsigned long mac_rx_frame_ctrl_fifo;
 171         unsigned long mac_gmii_rx_proto_engine;
 172         /* TSO */
 173         unsigned long tx_tso_frames;
 174         unsigned long tx_tso_nfrags;
 175 };
 176
 177 /* CSR Frequency Access Defines*/
 178 #define CSR_F_35M       35000000
 179 #define CSR_F_60M       60000000
 180 #define CSR_F_100M      100000000
 181 #define CSR_F_150M      150000000
 182 #define CSR_F_250M      250000000
 183 #define CSR_F_300M      300000000
 184
 185 #define MAC_CSR_H_FRQ_MASK      0x20
 186
 187 #define HASH_TABLE_SIZE 64
 188 #define PAUSE_TIME 0xffff
 189
 190 /* Flow Control defines */
 191 #define FLOW_OFF        0
 192 #define FLOW_RX         1
 193 #define FLOW_TX         2
 194 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 195
 196 /* PCS defines */
 197 #define STMMAC_PCS_RGMII        (1 << 0)
 198 #define STMMAC_PCS_SGMII        (1 << 1)
 199 #define STMMAC_PCS_TBI          (1 << 2)
 200 #define STMMAC_PCS_RTBI         (1 << 3)
 201
 202 #define SF_DMA_MODE 1           /* DMA STORE-AND-FORWARD Operation Mode */
 203
 204 /* DAM HW feature register fields */
 205 #define DMA_HW_FEAT_MIISEL      0x00000001      /* 10/100 Mbps Support */
 206 #define DMA_HW_FEAT_GMIISEL     0x00000002      /* 1000 Mbps Support */
 207 #define DMA_HW_FEAT_HDSEL       0x00000004      /* Half-Duplex Support */
 208 #define DMA_HW_FEAT_EXTHASHEN   0x00000008      /* Expanded DA Hash Filter */
 209 #define DMA_HW_FEAT_HASHSEL     0x00000010      /* HASH Filter */
 210 #define DMA_HW_FEAT_ADDMAC      0x00000020      /* Multiple MAC Addr Reg */
 211 #define DMA_HW_FEAT_PCSSEL      0x00000040      /* PCS registers */
 212 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080      /* Layer 3 & Layer 4 Feature */
 213 #define DMA_HW_FEAT_SMASEL      0x00000100      /* SMA(MDIO) Interface */
 214 #define DMA_HW_FEAT_RWKSEL      0x00000200      /* PMT Remote Wakeup */
 215 #define DMA_HW_FEAT_MGKSEL      0x00000400      /* PMT Magic Packet */
 216 #define DMA_HW_FEAT_MMCSEL      0x00000800      /* RMON Module */
 217 #define DMA_HW_FEAT_TSVER1SEL   0x00001000      /* Only IEEE 1588-2002 */
 218 #define DMA_HW_FEAT_TSVER2SEL   0x00002000      /* IEEE 1588-2008 PTPv2 */
 219 #define DMA_HW_FEAT_EEESEL      0x00004000      /* Energy Efficient Ethernet */
 220 #define DMA_HW_FEAT_AVSEL       0x00008000      /* AV Feature */
 221 #define DMA_HW_FEAT_TXCOESEL    0x00010000      /* Checksum Offload in Tx */
 222 #define DMA_HW_FEAT_RXTYP1COE   0x00020000      /* IP COE (Type 1) in Rx */
 223 #define DMA_HW_FEAT_RXTYP2COE   0x00040000      /* IP COE (Type 2) in Rx */
 224 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000      /* Rx FIFO > 2048 Bytes */
 225 #define DMA_HW_FEAT_RXCHCNT     0x00300000      /* No. additional Rx Channels */
 226 #define DMA_HW_FEAT_TXCHCNT     0x00c00000      /* No. additional Tx Channels */
 227 #define DMA_HW_FEAT_ENHDESSEL   0x01000000      /* Alternate Descriptor */
 228 /* Timestamping with Internal System Time */
 229 #define DMA_HW_FEAT_INTTSEN     0x02000000
 230 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000      /* Flexible PPS Output */
 231 #define DMA_HW_FEAT_SAVLANINS   0x08000000      /* Source Addr or VLAN */
 232 #define DMA_HW_FEAT_ACTPHYIF    0x70000000      /* Active/selected PHY iface */
 233 #define DEFAULT_DMA_PBL         8
 234
 235 /* PCS status and mask defines */
 236 #define PCS_ANE_IRQ             BIT(2)  /* PCS Auto-Negotiation */
 237 #define PCS_LINK_IRQ            BIT(1)  /* PCS Link */
 238 #define PCS_RGSMIIIS_IRQ        BIT(0)  /* RGMII or SMII Interrupt */
 239
 240 /* Max/Min RI Watchdog Timer count value */
 241 #define MAX_DMA_RIWT            0xff
 242 #define MIN_DMA_RIWT            0x20
 243 /* Tx coalesce parameters */
 244 #define STMMAC_COAL_TX_TIMER    40000
 245 #define STMMAC_MAX_COAL_TX_TICK 100000
 246 #define STMMAC_TX_MAX_FRAMES    256
 247 #define STMMAC_TX_FRAMES        64
 248
 249 /* Packets types */
 250 enum packets_types {
 251         PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
 252         PACKET_PTPQ = 0x2, /* PTP Packets */
 253         PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
 254         PACKET_UPQ = 0x4, /* Untagged Packets */
 255         PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
 256 };
 257
 258 /* Rx IPC status */
 259 enum rx_frame_status {
 260         good_frame = 0x0,
 261         discard_frame = 0x1,
 262         csum_none = 0x2,
 263         llc_snap = 0x4,
 264         dma_own = 0x8,
 265         rx_not_ls = 0x10,
 266 };
 267
 268 /* Tx status */
 269 enum tx_frame_status {
 270         tx_done = 0x0,
 271         tx_not_ls = 0x1,
 272         tx_err = 0x2,
 273         tx_dma_own = 0x4,
 274 };
 275
 276 enum dma_irq_status {
 277         tx_hard_error = 0x1,
 278         tx_hard_error_bump_tc = 0x2,
 279         handle_rx = 0x4,
 280         handle_tx = 0x8,
 281 };
 282
 283 /* EEE and LPI defines */
 284 #define CORE_IRQ_TX_PATH_IN_LPI_MODE    (1 << 0)
 285 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE  (1 << 1)
 286 #define CORE_IRQ_RX_PATH_IN_LPI_MODE    (1 << 2)
 287 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE  (1 << 3)
 288
 289 #define CORE_IRQ_MTL_RX_OVERFLOW        BIT(8)
 290
 291 /* Physical Coding Sublayer */
 292 struct rgmii_adv {
 293         unsigned int pause;
 294         unsigned int duplex;
 295         unsigned int lp_pause;
 296         unsigned int lp_duplex;
 297 };
 298
 299 #define STMMAC_PCS_PAUSE        1
 300 #define STMMAC_PCS_ASYM_PAUSE   2
 301
 302 /* DMA HW capabilities */
 303 struct dma_features {
 304         unsigned int mbps_10_100;
 305         unsigned int mbps_1000;
 306         unsigned int half_duplex;
 307         unsigned int hash_filter;
 308         unsigned int multi_addr;
 309         unsigned int pcs;
 310         unsigned int sma_mdio;
 311         unsigned int pmt_remote_wake_up;
 312         unsigned int pmt_magic_frame;
 313         unsigned int rmon;
 314         /* IEEE 1588-2002 */
 315         unsigned int time_stamp;
 316         /* IEEE 1588-2008 */
 317         unsigned int atime_stamp;
 318         /* 802.3az - Energy-Efficient Ethernet (EEE) */
 319         unsigned int eee;
 320         unsigned int av;
 321         unsigned int tsoen;
 322         /* TX and RX csum */
 323         unsigned int tx_coe;
 324         unsigned int rx_coe;
 325         unsigned int rx_coe_type1;
 326         unsigned int rx_coe_type2;
 327         unsigned int rxfifo_over_2048;
 328         /* TX and RX number of channels */
 329         unsigned int number_rx_channel;
 330         unsigned int number_tx_channel;
 331         /* TX and RX number of queues */
 332         unsigned int number_rx_queues;
 333         unsigned int number_tx_queues;
 334         /* Alternate (enhanced) DESC mode */
 335         unsigned int enh_desc;
 336         /* TX and RX FIFO sizes */
 337         unsigned int tx_fifo_size;
 338         unsigned int rx_fifo_size;
 339 };
 340
 341 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 342 #define BUF_SIZE_16KiB 16384
 343 #define BUF_SIZE_8KiB 8192
 344 #define BUF_SIZE_4KiB 4096
 345 #define BUF_SIZE_2KiB 2048
 346
 347 /* Power Down and WOL */
 348 #define PMT_NOT_SUPPORTED 0
 349 #define PMT_SUPPORTED 1
 350
 351 /* Common MAC defines */
 352 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 353 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 354 #define MAC_ENABLE_RX           0x00000004      /* Receiver Enable */
 355
 356 /* Default LPI timers */
 357 #define STMMAC_DEFAULT_LIT_LS   0x3E8
 358 #define STMMAC_DEFAULT_TWT_LS   0x1E
 359
 360 #define STMMAC_CHAIN_MODE       0x1
 361 #define STMMAC_RING_MODE        0x2
 362
 363 #define JUMBO_LEN               9000
 364
 365 /* Descriptors helpers */
 366 struct stmmac_desc_ops {
 367         /* DMA RX descriptor ring initialization */
 368         void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
 369                               int end);
 370         /* DMA TX descriptor ring initialization */
 371         void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
 372
 373         /* Invoked by the xmit function to prepare the tx descriptor */
 374         void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
 375                                  bool csum_flag, int mode, bool tx_own,
 376                                  bool ls, unsigned int tot_pkt_len);
 377         void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
 378                                     int len2, bool tx_own, bool ls,
 379                                     unsigned int tcphdrlen,
 380                                     unsigned int tcppayloadlen);
 381         /* Set/get the owner of the descriptor */
 382         void (*set_tx_owner) (struct dma_desc *p);
 383         int (*get_tx_owner) (struct dma_desc *p);
 384         /* Clean the tx descriptor as soon as the tx irq is received */
 385         void (*release_tx_desc) (struct dma_desc *p, int mode);
 386         /* Clear interrupt on tx frame completion. When this bit is
 387          * set an interrupt happens as soon as the frame is transmitted */
 388         void (*set_tx_ic)(struct dma_desc *p);
 389         /* Last tx segment reports the transmit status */
 390         int (*get_tx_ls) (struct dma_desc *p);
 391         /* Return the transmit status looking at the TDES1 */
 392         int (*tx_status) (void *data, struct stmmac_extra_stats *x,
 393                           struct dma_desc *p, void __iomem *ioaddr);
 394         /* Get the buffer size from the descriptor */
 395         int (*get_tx_len) (struct dma_desc *p);
 396         /* Handle extra events on specific interrupts hw dependent */
 397         void (*set_rx_owner) (struct dma_desc *p);
 398         /* Get the receive frame size */
 399         int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
 400         /* Return the reception status looking at the RDES1 */
 401         int (*rx_status) (void *data, struct stmmac_extra_stats *x,
 402                           struct dma_desc *p);
 403         void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
 404                                     struct dma_extended_desc *p);
 405         /* Set tx timestamp enable bit */
 406         void (*enable_tx_timestamp) (struct dma_desc *p);
 407         /* get tx timestamp status */
 408         int (*get_tx_timestamp_status) (struct dma_desc *p);
 409         /* get timestamp value */
 410          u64(*get_timestamp) (void *desc, u32 ats);
 411         /* get rx timestamp status */
 412         int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
 413         /* Display ring */
 414         void (*display_ring)(void *head, unsigned int size, bool rx);
 415         /* set MSS via context descriptor */
 416         void (*set_mss)(struct dma_desc *p, unsigned int mss);
 417 };
 418
 419 extern const struct stmmac_desc_ops enh_desc_ops;
 420 extern const struct stmmac_desc_ops ndesc_ops;
 421
 422 /* Specific DMA helpers */
 423 struct stmmac_dma_ops {
 424         /* DMA core initialization */
 425         int (*reset)(void __iomem *ioaddr);
 426         void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
 427                      u32 dma_tx, u32 dma_rx, int atds);
 428         void (*init_chan)(void __iomem *ioaddr,
 429                           struct stmmac_dma_cfg *dma_cfg, u32 chan);
 430         void (*init_rx_chan)(void __iomem *ioaddr,
 431                              struct stmmac_dma_cfg *dma_cfg,
 432                              u32 dma_rx_phy, u32 chan);
 433         void (*init_tx_chan)(void __iomem *ioaddr,
 434                              struct stmmac_dma_cfg *dma_cfg,
 435                              u32 dma_tx_phy, u32 chan);
 436         /* Configure the AXI Bus Mode Register */
 437         void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
 438         /* Dump DMA registers */
 439         void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
 440         /* Set tx/rx threshold in the csr6 register
 441          * An invalid value enables the store-and-forward mode */
 442         void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
 443                          int rxfifosz);
 444         void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,
 445                             int fifosz, u8 qmode);
 446         void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel,
 447                             int fifosz, u8 qmode);
 448         /* To track extra statistic (if supported) */
 449         void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
 450                                    void __iomem *ioaddr);
 451         void (*enable_dma_transmission) (void __iomem *ioaddr);
 452         void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
 453         void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
 454         void (*start_tx)(void __iomem *ioaddr, u32 chan);
 455         void (*stop_tx)(void __iomem *ioaddr, u32 chan);
 456         void (*start_rx)(void __iomem *ioaddr, u32 chan);
 457         void (*stop_rx)(void __iomem *ioaddr, u32 chan);
 458         int (*dma_interrupt) (void __iomem *ioaddr,
 459                               struct stmmac_extra_stats *x, u32 chan);
 460         /* If supported then get the optional core features */
 461         void (*get_hw_feature)(void __iomem *ioaddr,
 462                                struct dma_features *dma_cap);
 463         /* Program the HW RX Watchdog */
 464         void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt, u32 number_chan);
 465         void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
 466         void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
 467         void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 468         void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
 469         void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
 470 };
 471
 472 struct mac_device_info;
 473
 474 /* Helpers to program the MAC core */
 475 struct stmmac_ops {
 476         /* MAC core initialization */
 477         void (*core_init)(struct mac_device_info *hw, struct net_device *dev);
 478         /* Enable the MAC RX/TX */
 479         void (*set_mac)(void __iomem *ioaddr, bool enable);
 480         /* Enable and verify that the IPC module is supported */
 481         int (*rx_ipc)(struct mac_device_info *hw);
 482         /* Enable RX Queues */
 483         void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
 484         /* RX Queues Priority */
 485         void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 486         /* TX Queues Priority */
 487         void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 488         /* RX Queues Routing */
 489         void (*rx_queue_routing)(struct mac_device_info *hw, u8 packet,
 490                                  u32 queue);
 491         /* Program RX Algorithms */
 492         void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
 493         /* Program TX Algorithms */
 494         void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
 495         /* Set MTL TX queues weight */
 496         void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
 497                                         u32 weight, u32 queue);
 498         /* RX MTL queue to RX dma mapping */
 499         void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
 500         /* Configure AV Algorithm */
 501         void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
 502                            u32 idle_slope, u32 high_credit, u32 low_credit,
 503                            u32 queue);
 504         /* Dump MAC registers */
 505         void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
 506         /* Handle extra events on specific interrupts hw dependent */
 507         int (*host_irq_status)(struct mac_device_info *hw,
 508                                struct stmmac_extra_stats *x);
 509         /* Handle MTL interrupts */
 510         int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
 511         /* Multicast filter setting */
 512         void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
 513         /* Flow control setting */
 514         void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
 515                           unsigned int fc, unsigned int pause_time, u32 tx_cnt);
 516         /* Set power management mode (e.g. magic frame) */
 517         void (*pmt)(struct mac_device_info *hw, unsigned long mode);
 518         /* Set/Get Unicast MAC addresses */
 519         void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
 520                               unsigned int reg_n);
 521         void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
 522                               unsigned int reg_n);
 523         void (*set_eee_mode)(struct mac_device_info *hw,
 524                              bool en_tx_lpi_clockgating);
 525         void (*reset_eee_mode)(struct mac_device_info *hw);
 526         void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
 527         void (*set_eee_pls)(struct mac_device_info *hw, int link);
 528         void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 529                       u32 rx_queues, u32 tx_queues);
 530         /* PCS calls */
 531         void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 532                              bool loopback);
 533         void (*pcs_rane)(void __iomem *ioaddr, bool restart);
 534         void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
 535 };
 536
 537 /* PTP and HW Timer helpers */
 538 struct stmmac_hwtimestamp {
 539         void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
 540         u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
 541                                            int gmac4);
 542         int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
 543         int (*config_addend) (void __iomem *ioaddr, u32 addend);
 544         int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
 545                                int add_sub, int gmac4);
 546          u64(*get_systime) (void __iomem *ioaddr);
 547 };
 548
 549 extern const struct stmmac_hwtimestamp stmmac_ptp;
 550 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
 551
 552 struct mac_link {
 553         u32 speed_mask;
 554         u32 speed10;
 555         u32 speed100;
 556         u32 speed1000;
 557         u32 duplex;
 558 };
 559
 560 struct mii_regs {
 561         unsigned int addr;      /* MII Address */
 562         unsigned int data;      /* MII Data */
 563         unsigned int addr_shift;        /* MII address shift */
 564         unsigned int reg_shift;         /* MII reg shift */
 565         unsigned int addr_mask;         /* MII address mask */
 566         unsigned int reg_mask;          /* MII reg mask */
 567         unsigned int clk_csr_shift;
 568         unsigned int clk_csr_mask;
 569 };
 570
 571 /* Helpers to manage the descriptors for chain and ring modes */
 572 struct stmmac_mode_ops {
 573         void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
 574                       unsigned int extend_desc);
 575         unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
 576         int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
 577         int (*set_16kib_bfsize)(int mtu);
 578         void (*init_desc3)(struct dma_desc *p);
 579         void (*refill_desc3) (void *priv, struct dma_desc *p);
 580         void (*clean_desc3) (void *priv, struct dma_desc *p);
 581 };
 582
 583 struct mac_device_info {
 584         const struct stmmac_ops *mac;
 585         const struct stmmac_desc_ops *desc;
 586         const struct stmmac_dma_ops *dma;
 587         const struct stmmac_mode_ops *mode;
 588         const struct stmmac_hwtimestamp *ptp;
 589         struct mii_regs mii;    /* MII register Addresses */
 590         struct mac_link link;
 591         void __iomem *pcsr;     /* vpointer to device CSRs */
 592         int multicast_filter_bins;
 593         int unicast_filter_entries;
 594         int mcast_bits_log2;
 595         unsigned int rx_csum;
 596         unsigned int pcs;
 597         unsigned int pmt;
 598         unsigned int ps;
 599 };
 600
 601 struct stmmac_rx_routing {
 602         u32 reg_mask;
 603         u32 reg_shift;
 604 };
 605
 606 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 607                                         int perfect_uc_entries,
 608                                         int *synopsys_id);
 609 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
 610 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 611                                      int perfect_uc_entries, int *synopsys_id);
 612
 613 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 614                          unsigned int high, unsigned int low);
 615 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 616                          unsigned int high, unsigned int low);
 617 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
 618
 619 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 620                                 unsigned int high, unsigned int low);
 621 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 622                                 unsigned int high, unsigned int low);
 623 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
 624
 625 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
 626
 627 extern const struct stmmac_mode_ops ring_mode_ops;
 628 extern const struct stmmac_mode_ops chain_mode_ops;
 629 extern const struct stmmac_desc_ops dwmac4_desc_ops;
 630
 631 /**
 632  * stmmac_get_synopsys_id - return the SYINID.
 633  * @priv: driver private structure
 634  * Description: this simple function is to decode and return the SYINID
 635  * starting from the HW core register.
 636  */
 637 static inline u32 stmmac_get_synopsys_id(u32 hwid)
 638 {
 639         /* Check Synopsys Id (not available on old chips) */
 640         if (likely(hwid)) {
 641                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 642                 u32 synid = (hwid & 0x000000ff);
 643
 644                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 645                         uid, synid);
 646
 647                 return synid;
 648         }
 649         return 0;
 650 }
 651 #endif /* __COMMON_H__ */