drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

   1 /*******************************************************************************
   2   This is the driver for the MAC 10/100 on-chip Ethernet controller
   3   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6   this code.
   7
   8   This only implements the mac core functions for this chip.
   9
  10   Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms and conditions of the GNU General Public License,
  14   version 2, as published by the Free Software Foundation.
  15
  16   This program is distributed in the hope it will be useful, but WITHOUT
  17   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19   more details.
  20
  21   The full GNU General Public License is included in this distribution in
  22   the file called "COPYING".
  23
  24   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  25 *******************************************************************************/
  26
  27 #include <linux/crc32.h>
  28 #include <net/dsa.h>
  29 #include <asm/io.h>
  30 #include "dwmac100.h"
  31
  32 static void dwmac100_core_init(struct mac_device_info *hw,
  33                                struct net_device *dev)
  34 {
  35         void __iomem *ioaddr = hw->pcsr;
  36         u32 value = readl(ioaddr + MAC_CONTROL);
  37
  38         value |= MAC_CORE_INIT;
  39
  40         /* Clear ASTP bit because Ethernet switch tagging formats such as
  41          * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  42          * hardware to truncate packets on reception.
  43          */
  44         if (netdev_uses_dsa(dev))
  45                 value &= ~MAC_CONTROL_ASTP;
  46
  47         writel(value, ioaddr + MAC_CONTROL);
  48
  49 #ifdef STMMAC_VLAN_TAG_USED
  50         writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  51 #endif
  52 }
  53
  54 static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
  55 {
  56         void __iomem *ioaddr = hw->pcsr;
  57
  58         reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
  59         reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
  60         reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
  61         reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
  62         reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
  63         reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
  64         reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
  65         reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
  66 }
  67
  68 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
  69 {
  70         return 0;
  71 }
  72
  73 static int dwmac100_irq_status(struct mac_device_info *hw,
  74                                struct stmmac_extra_stats *x)
  75 {
  76         return 0;
  77 }
  78
  79 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
  80                                    unsigned char *addr,
  81                                    unsigned int reg_n)
  82 {
  83         void __iomem *ioaddr = hw->pcsr;
  84         stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  85 }
  86
  87 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
  88                                    unsigned char *addr,
  89                                    unsigned int reg_n)
  90 {
  91         void __iomem *ioaddr = hw->pcsr;
  92         stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  93 }
  94
  95 static void dwmac100_set_filter(struct mac_device_info *hw,
  96                                 struct net_device *dev)
  97 {
  98         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
  99         u32 value = readl(ioaddr + MAC_CONTROL);
 100
 101         if (dev->flags & IFF_PROMISC) {
 102                 value |= MAC_CONTROL_PR;
 103                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
 104                            MAC_CONTROL_HP);
 105         } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
 106                    || (dev->flags & IFF_ALLMULTI)) {
 107                 value |= MAC_CONTROL_PM;
 108                 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
 109                 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
 110                 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
 111         } else if (netdev_mc_empty(dev)) {      /* no multicast */
 112                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
 113                            MAC_CONTROL_HO | MAC_CONTROL_HP);
 114         } else {
 115                 u32 mc_filter[2];
 116                 struct netdev_hw_addr *ha;
 117
 118                 /* Perfect filter mode for physical address and Hash
 119                  * filter for multicast
 120                  */
 121                 value |= MAC_CONTROL_HP;
 122                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
 123                            MAC_CONTROL_IF | MAC_CONTROL_HO);
 124
 125                 memset(mc_filter, 0, sizeof(mc_filter));
 126                 netdev_for_each_mc_addr(ha, dev) {
 127                         /* The upper 6 bits of the calculated CRC are used to
 128                          * index the contens of the hash table
 129                          */
 130                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 131                         /* The most significant bit determines the register to
 132                          * use (H/L) while the other 5 bits determine the bit
 133                          * within the register.
 134                          */
 135                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 136                 }
 137                 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
 138                 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
 139         }
 140
 141         writel(value, ioaddr + MAC_CONTROL);
 142 }
 143
 144 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 145                                unsigned int fc, unsigned int pause_time,
 146                                u32 tx_cnt)
 147 {
 148         void __iomem *ioaddr = hw->pcsr;
 149         unsigned int flow = MAC_FLOW_CTRL_ENABLE;
 150
 151         if (duplex)
 152                 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
 153         writel(flow, ioaddr + MAC_FLOW_CTRL);
 154 }
 155
 156 /* No PMT module supported on ST boards with this Eth chip. */
 157 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
 158 {
 159         return;
 160 }
 161
 162 static const struct stmmac_ops dwmac100_ops = {
 163         .core_init = dwmac100_core_init,
 164         .set_mac = stmmac_set_mac,
 165         .rx_ipc = dwmac100_rx_ipc_enable,
 166         .dump_regs = dwmac100_dump_mac_regs,
 167         .host_irq_status = dwmac100_irq_status,
 168         .set_filter = dwmac100_set_filter,
 169         .flow_ctrl = dwmac100_flow_ctrl,
 170         .pmt = dwmac100_pmt,
 171         .set_umac_addr = dwmac100_set_umac_addr,
 172         .get_umac_addr = dwmac100_get_umac_addr,
 173 };
 174
 175 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id)
 176 {
 177         struct mac_device_info *mac;
 178
 179         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 180         if (!mac)
 181                 return NULL;
 182
 183         pr_info("\tDWMAC100\n");
 184
 185         mac->pcsr = ioaddr;
 186         mac->mac = &dwmac100_ops;
 187         mac->dma = &dwmac100_dma_ops;
 188
 189         mac->link.duplex = MAC_CONTROL_F;
 190         mac->link.speed10 = 0;
 191         mac->link.speed100 = 0;
 192         mac->link.speed1000 = 0;
 193         mac->link.speed_mask = MAC_CONTROL_PS;
 194         mac->mii.addr = MAC_MII_ADDR;
 195         mac->mii.data = MAC_MII_DATA;
 196         mac->mii.addr_shift = 11;
 197         mac->mii.addr_mask = 0x0000F800;
 198         mac->mii.reg_shift = 6;
 199         mac->mii.reg_mask = 0x000007C0;
 200         mac->mii.clk_csr_shift = 2;
 201         mac->mii.clk_csr_mask = GENMASK(5, 2);
 202
 203         /* Synopsys Id is not available on old chips */
 204         *synopsys_id = 0;
 205
 206         return mac;
 207 }