drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include <net/dsa.h>
  21 #include "stmmac_pcs.h"
  22 #include "dwmac4.h"
  23
  24 static void dwmac4_core_init(struct mac_device_info *hw,
  25                              struct net_device *dev)
  26 {
  27         void __iomem *ioaddr = hw->pcsr;
  28         u32 value = readl(ioaddr + GMAC_CONFIG);
  29         int mtu = dev->mtu;
  30
  31         value |= GMAC_CORE_INIT;
  32
  33         /* Clear ACS bit because Ethernet switch tagging formats such as
  34          * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  35          * hardware to truncate packets on reception.
  36          */
  37         if (netdev_uses_dsa(dev))
  38                 value &= ~GMAC_CONFIG_ACS;
  39
  40         if (mtu > 1500)
  41                 value |= GMAC_CONFIG_2K;
  42         if (mtu > 2000)
  43                 value |= GMAC_CONFIG_JE;
  44
  45         if (hw->ps) {
  46                 value |= GMAC_CONFIG_TE;
  47
  48                 value &= hw->link.speed_mask;
  49                 switch (hw->ps) {
  50                 case SPEED_1000:
  51                         value |= hw->link.speed1000;
  52                         break;
  53                 case SPEED_100:
  54                         value |= hw->link.speed100;
  55                         break;
  56                 case SPEED_10:
  57                         value |= hw->link.speed10;
  58                         break;
  59                 }
  60         }
  61
  62         writel(value, ioaddr + GMAC_CONFIG);
  63
  64         /* Enable GMAC interrupts */
  65         value = GMAC_INT_DEFAULT_ENABLE;
  66
  67         if (hw->pcs)
  68                 value |= GMAC_PCS_IRQ_DEFAULT;
  69
  70         writel(value, ioaddr + GMAC_INT_EN);
  71 }
  72
  73 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  74                                    u8 mode, u32 queue)
  75 {
  76         void __iomem *ioaddr = hw->pcsr;
  77         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  78
  79         value &= GMAC_RX_QUEUE_CLEAR(queue);
  80         if (mode == MTL_QUEUE_AVB)
  81                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  82         else if (mode == MTL_QUEUE_DCB)
  83                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  84
  85         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  86 }
  87
  88 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  89                                      u32 prio, u32 queue)
  90 {
  91         void __iomem *ioaddr = hw->pcsr;
  92         u32 base_register;
  93         u32 value;
  94
  95         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  96
  97         value = readl(ioaddr + base_register);
  98
  99         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
 100         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 101                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 102         writel(value, ioaddr + base_register);
 103 }
 104
 105 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 106                                      u32 prio, u32 queue)
 107 {
 108         void __iomem *ioaddr = hw->pcsr;
 109         u32 base_register;
 110         u32 value;
 111
 112         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 113
 114         value = readl(ioaddr + base_register);
 115
 116         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 117         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 118                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 119
 120         writel(value, ioaddr + base_register);
 121 }
 122
 123 static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
 124                                     u8 packet, u32 queue)
 125 {
 126         void __iomem *ioaddr = hw->pcsr;
 127         u32 value;
 128
 129         static const struct stmmac_rx_routing route_possibilities[] = {
 130                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 131                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 132                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 133                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 134                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 135         };
 136
 137         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 138
 139         /* routing configuration */
 140         value &= ~route_possibilities[packet - 1].reg_mask;
 141         value |= (queue << route_possibilities[packet-1].reg_shift) &
 142                  route_possibilities[packet - 1].reg_mask;
 143
 144         /* some packets require extra ops */
 145         if (packet == PACKET_AVCPQ) {
 146                 value &= ~GMAC_RXQCTRL_TACPQE;
 147                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 148         } else if (packet == PACKET_MCBCQ) {
 149                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 150                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 151         }
 152
 153         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 154 }
 155
 156 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 157                                           u32 rx_alg)
 158 {
 159         void __iomem *ioaddr = hw->pcsr;
 160         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 161
 162         value &= ~MTL_OPERATION_RAA;
 163         switch (rx_alg) {
 164         case MTL_RX_ALGORITHM_SP:
 165                 value |= MTL_OPERATION_RAA_SP;
 166                 break;
 167         case MTL_RX_ALGORITHM_WSP:
 168                 value |= MTL_OPERATION_RAA_WSP;
 169                 break;
 170         default:
 171                 break;
 172         }
 173
 174         writel(value, ioaddr + MTL_OPERATION_MODE);
 175 }
 176
 177 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 178                                           u32 tx_alg)
 179 {
 180         void __iomem *ioaddr = hw->pcsr;
 181         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 182
 183         value &= ~MTL_OPERATION_SCHALG_MASK;
 184         switch (tx_alg) {
 185         case MTL_TX_ALGORITHM_WRR:
 186                 value |= MTL_OPERATION_SCHALG_WRR;
 187                 break;
 188         case MTL_TX_ALGORITHM_WFQ:
 189                 value |= MTL_OPERATION_SCHALG_WFQ;
 190                 break;
 191         case MTL_TX_ALGORITHM_DWRR:
 192                 value |= MTL_OPERATION_SCHALG_DWRR;
 193                 break;
 194         case MTL_TX_ALGORITHM_SP:
 195                 value |= MTL_OPERATION_SCHALG_SP;
 196                 break;
 197         default:
 198                 break;
 199         }
 200 }
 201
 202 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 203                                            u32 weight, u32 queue)
 204 {
 205         void __iomem *ioaddr = hw->pcsr;
 206         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 207
 208         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 209         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 210         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 211 }
 212
 213 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 214 {
 215         void __iomem *ioaddr = hw->pcsr;
 216         u32 value;
 217
 218         if (queue < 4)
 219                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 220         else
 221                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 222
 223         if (queue == 0 || queue == 4) {
 224                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 225                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 226         } else {
 227                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 228                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 229         }
 230
 231         if (queue < 4)
 232                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 233         else
 234                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 235 }
 236
 237 static void dwmac4_config_cbs(struct mac_device_info *hw,
 238                               u32 send_slope, u32 idle_slope,
 239                               u32 high_credit, u32 low_credit, u32 queue)
 240 {
 241         void __iomem *ioaddr = hw->pcsr;
 242         u32 value;
 243
 244         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 245         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 246         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 247         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 248         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 249
 250         /* enable AV algorithm */
 251         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 252         value |= MTL_ETS_CTRL_AVALG;
 253         value |= MTL_ETS_CTRL_CC;
 254         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 255
 256         /* configure send slope */
 257         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 258         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 259         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 260         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 261
 262         /* configure idle slope (same register as tx weight) */
 263         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 264
 265         /* configure high credit */
 266         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 267         value &= ~MTL_HIGH_CRED_HC_MASK;
 268         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 269         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 270
 271         /* configure high credit */
 272         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 273         value &= ~MTL_HIGH_CRED_LC_MASK;
 274         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 275         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 276 }
 277
 278 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 279 {
 280         void __iomem *ioaddr = hw->pcsr;
 281         int i;
 282
 283         for (i = 0; i < GMAC_REG_NUM; i++)
 284                 reg_space[i] = readl(ioaddr + i * 4);
 285 }
 286
 287 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 288 {
 289         void __iomem *ioaddr = hw->pcsr;
 290         u32 value = readl(ioaddr + GMAC_CONFIG);
 291
 292         if (hw->rx_csum)
 293                 value |= GMAC_CONFIG_IPC;
 294         else
 295                 value &= ~GMAC_CONFIG_IPC;
 296
 297         writel(value, ioaddr + GMAC_CONFIG);
 298
 299         value = readl(ioaddr + GMAC_CONFIG);
 300
 301         return !!(value & GMAC_CONFIG_IPC);
 302 }
 303
 304 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 305 {
 306         void __iomem *ioaddr = hw->pcsr;
 307         unsigned int pmt = 0;
 308         u32 config;
 309
 310         if (mode & WAKE_MAGIC) {
 311                 pr_debug("GMAC: WOL Magic frame\n");
 312                 pmt |= power_down | magic_pkt_en;
 313         }
 314         if (mode & WAKE_UCAST) {
 315                 pr_debug("GMAC: WOL on global unicast\n");
 316                 pmt |= power_down | global_unicast | wake_up_frame_en;
 317         }
 318
 319         if (pmt) {
 320                 /* The receiver must be enabled for WOL before powering down */
 321                 config = readl(ioaddr + GMAC_CONFIG);
 322                 config |= GMAC_CONFIG_RE;
 323                 writel(config, ioaddr + GMAC_CONFIG);
 324         }
 325         writel(pmt, ioaddr + GMAC_PMT);
 326 }
 327
 328 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 329                                  unsigned char *addr, unsigned int reg_n)
 330 {
 331         void __iomem *ioaddr = hw->pcsr;
 332
 333         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 334                                    GMAC_ADDR_LOW(reg_n));
 335 }
 336
 337 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 338                                  unsigned char *addr, unsigned int reg_n)
 339 {
 340         void __iomem *ioaddr = hw->pcsr;
 341
 342         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 343                                    GMAC_ADDR_LOW(reg_n));
 344 }
 345
 346 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 347                                 bool en_tx_lpi_clockgating)
 348 {
 349         void __iomem *ioaddr = hw->pcsr;
 350         u32 value;
 351
 352         /* Enable the link status receive on RGMII, SGMII ore SMII
 353          * receive path and instruct the transmit to enter in LPI
 354          * state.
 355          */
 356         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 357         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 358
 359         if (en_tx_lpi_clockgating)
 360                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 361
 362         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 363 }
 364
 365 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 366 {
 367         void __iomem *ioaddr = hw->pcsr;
 368         u32 value;
 369
 370         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 371         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 372         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 373 }
 374
 375 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 376 {
 377         void __iomem *ioaddr = hw->pcsr;
 378         u32 value;
 379
 380         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 381
 382         if (link)
 383                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 384         else
 385                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 386
 387         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 388 }
 389
 390 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 391 {
 392         void __iomem *ioaddr = hw->pcsr;
 393         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 394
 395         /* Program the timers in the LPI timer control register:
 396          * LS: minimum time (ms) for which the link
 397          *  status from PHY should be ok before transmitting
 398          *  the LPI pattern.
 399          * TW: minimum time (us) for which the core waits
 400          *  after it has stopped transmitting the LPI pattern.
 401          */
 402         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 403 }
 404
 405 static void dwmac4_set_filter(struct mac_device_info *hw,
 406                               struct net_device *dev)
 407 {
 408         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 409         unsigned int value = 0;
 410
 411         if (dev->flags & IFF_PROMISC) {
 412                 value = GMAC_PACKET_FILTER_PR;
 413         } else if ((dev->flags & IFF_ALLMULTI) ||
 414                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 415                 /* Pass all multi */
 416                 value = GMAC_PACKET_FILTER_PM;
 417                 /* Set the 64 bits of the HASH tab. To be updated if taller
 418                  * hash table is used
 419                  */
 420                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 421                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 422         } else if (!netdev_mc_empty(dev)) {
 423                 u32 mc_filter[2];
 424                 struct netdev_hw_addr *ha;
 425
 426                 /* Hash filter for multicast */
 427                 value = GMAC_PACKET_FILTER_HMC;
 428
 429                 memset(mc_filter, 0, sizeof(mc_filter));
 430                 netdev_for_each_mc_addr(ha, dev) {
 431                         /* The upper 6 bits of the calculated CRC are used to
 432                          * index the content of the Hash Table Reg 0 and 1.
 433                          */
 434                         int bit_nr =
 435                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 436                         /* The most significant bit determines the register
 437                          * to use while the other 5 bits determines the bit
 438                          * within the selected register
 439                          */
 440                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 441                 }
 442                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 443                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 444         }
 445
 446         /* Handle multiple unicast addresses */
 447         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 448                 /* Switch to promiscuous mode if more than 128 addrs
 449                  * are required
 450                  */
 451                 value |= GMAC_PACKET_FILTER_PR;
 452         } else if (!netdev_uc_empty(dev)) {
 453                 int reg = 1;
 454                 struct netdev_hw_addr *ha;
 455
 456                 netdev_for_each_uc_addr(ha, dev) {
 457                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 458                         reg++;
 459                 }
 460         }
 461
 462         writel(value, ioaddr + GMAC_PACKET_FILTER);
 463 }
 464
 465 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 466                              unsigned int fc, unsigned int pause_time,
 467                              u32 tx_cnt)
 468 {
 469         void __iomem *ioaddr = hw->pcsr;
 470         unsigned int flow = 0;
 471         u32 queue = 0;
 472
 473         pr_debug("GMAC Flow-Control:\n");
 474         if (fc & FLOW_RX) {
 475                 pr_debug("\tReceive Flow-Control ON\n");
 476                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 477                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 478         }
 479         if (fc & FLOW_TX) {
 480                 pr_debug("\tTransmit Flow-Control ON\n");
 481
 482                 if (duplex)
 483                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 484
 485                 for (queue = 0; queue < tx_cnt; queue++) {
 486                         flow |= GMAC_TX_FLOW_CTRL_TFE;
 487
 488                         if (duplex)
 489                                 flow |=
 490                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 491
 492                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 493                 }
 494         }
 495 }
 496
 497 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 498                             bool loopback)
 499 {
 500         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 501 }
 502
 503 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 504 {
 505         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 506 }
 507
 508 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 509 {
 510         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 511 }
 512
 513 /* RGMII or SMII interface */
 514 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 515 {
 516         u32 status;
 517
 518         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 519         x->irq_rgmii_n++;
 520
 521         /* Check the link status */
 522         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 523                 int speed_value;
 524
 525                 x->pcs_link = 1;
 526
 527                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 528                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 529                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 530                         x->pcs_speed = SPEED_1000;
 531                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 532                         x->pcs_speed = SPEED_100;
 533                 else
 534                         x->pcs_speed = SPEED_10;
 535
 536                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 537
 538                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 539                         x->pcs_duplex ? "Full" : "Half");
 540         } else {
 541                 x->pcs_link = 0;
 542                 pr_info("Link is Down\n");
 543         }
 544 }
 545
 546 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 547 {
 548         void __iomem *ioaddr = hw->pcsr;
 549         u32 mtl_int_qx_status;
 550         int ret = 0;
 551
 552         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 553
 554         /* Check MTL Interrupt */
 555         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 556                 /* read Queue x Interrupt status */
 557                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 558
 559                 if (status & MTL_RX_OVERFLOW_INT) {
 560                         /*  clear Interrupt */
 561                         writel(status | MTL_RX_OVERFLOW_INT,
 562                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 563                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 564                 }
 565         }
 566
 567         return ret;
 568 }
 569
 570 static int dwmac4_irq_status(struct mac_device_info *hw,
 571                              struct stmmac_extra_stats *x)
 572 {
 573         void __iomem *ioaddr = hw->pcsr;
 574         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 575         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 576         int ret = 0;
 577
 578         /* Discard disabled bits */
 579         intr_status &= intr_enable;
 580
 581         /* Not used events (e.g. MMC interrupts) are not handled. */
 582         if ((intr_status & mmc_tx_irq))
 583                 x->mmc_tx_irq_n++;
 584         if (unlikely(intr_status & mmc_rx_irq))
 585                 x->mmc_rx_irq_n++;
 586         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 587                 x->mmc_rx_csum_offload_irq_n++;
 588         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 589         if (unlikely(intr_status & pmt_irq)) {
 590                 readl(ioaddr + GMAC_PMT);
 591                 x->irq_receive_pmt_irq_n++;
 592         }
 593
 594         /* MAC tx/rx EEE LPI entry/exit interrupts */
 595         if (intr_status & lpi_irq) {
 596                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 597                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 598
 599                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 600                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 601                         x->irq_tx_path_in_lpi_mode_n++;
 602                 }
 603                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 604                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 605                         x->irq_tx_path_exit_lpi_mode_n++;
 606                 }
 607                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 608                         x->irq_rx_path_in_lpi_mode_n++;
 609                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 610                         x->irq_rx_path_exit_lpi_mode_n++;
 611         }
 612
 613         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 614         if (intr_status & PCS_RGSMIIIS_IRQ)
 615                 dwmac4_phystatus(ioaddr, x);
 616
 617         return ret;
 618 }
 619
 620 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 621                          u32 rx_queues, u32 tx_queues)
 622 {
 623         u32 value;
 624         u32 queue;
 625
 626         for (queue = 0; queue < tx_queues; queue++) {
 627                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 628
 629                 if (value & MTL_DEBUG_TXSTSFSTS)
 630                         x->mtl_tx_status_fifo_full++;
 631                 if (value & MTL_DEBUG_TXFSTS)
 632                         x->mtl_tx_fifo_not_empty++;
 633                 if (value & MTL_DEBUG_TWCSTS)
 634                         x->mmtl_fifo_ctrl++;
 635                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 636                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 637                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 638                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 639                                 x->mtl_tx_fifo_read_ctrl_write++;
 640                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 641                                 x->mtl_tx_fifo_read_ctrl_wait++;
 642                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 643                                 x->mtl_tx_fifo_read_ctrl_read++;
 644                         else
 645                                 x->mtl_tx_fifo_read_ctrl_idle++;
 646                 }
 647                 if (value & MTL_DEBUG_TXPAUSED)
 648                         x->mac_tx_in_pause++;
 649         }
 650
 651         for (queue = 0; queue < rx_queues; queue++) {
 652                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 653
 654                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 655                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 656                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 657
 658                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 659                                 x->mtl_rx_fifo_fill_level_full++;
 660                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 661                                 x->mtl_rx_fifo_fill_above_thresh++;
 662                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 663                                 x->mtl_rx_fifo_fill_below_thresh++;
 664                         else
 665                                 x->mtl_rx_fifo_fill_level_empty++;
 666                 }
 667                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 668                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 669                                      MTL_DEBUG_RRCSTS_SHIFT;
 670
 671                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 672                                 x->mtl_rx_fifo_read_ctrl_flush++;
 673                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 674                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 675                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 676                                 x->mtl_rx_fifo_read_ctrl_status++;
 677                         else
 678                                 x->mtl_rx_fifo_read_ctrl_idle++;
 679                 }
 680                 if (value & MTL_DEBUG_RWCSTS)
 681                         x->mtl_rx_fifo_ctrl_active++;
 682         }
 683
 684         /* GMAC debug */
 685         value = readl(ioaddr + GMAC_DEBUG);
 686
 687         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 688                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 689                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 690
 691                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 692                         x->mac_tx_frame_ctrl_xfer++;
 693                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 694                         x->mac_tx_frame_ctrl_pause++;
 695                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 696                         x->mac_tx_frame_ctrl_wait++;
 697                 else
 698                         x->mac_tx_frame_ctrl_idle++;
 699         }
 700         if (value & GMAC_DEBUG_TPESTS)
 701                 x->mac_gmii_tx_proto_engine++;
 702         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 703                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 704                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 705         if (value & GMAC_DEBUG_RPESTS)
 706                 x->mac_gmii_rx_proto_engine++;
 707 }
 708
 709 static const struct stmmac_ops dwmac4_ops = {
 710         .core_init = dwmac4_core_init,
 711         .set_mac = stmmac_set_mac,
 712         .rx_ipc = dwmac4_rx_ipc_enable,
 713         .rx_queue_enable = dwmac4_rx_queue_enable,
 714         .rx_queue_prio = dwmac4_rx_queue_priority,
 715         .tx_queue_prio = dwmac4_tx_queue_priority,
 716         .rx_queue_routing = dwmac4_tx_queue_routing,
 717         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 718         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 719         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 720         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 721         .config_cbs = dwmac4_config_cbs,
 722         .dump_regs = dwmac4_dump_regs,
 723         .host_irq_status = dwmac4_irq_status,
 724         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 725         .flow_ctrl = dwmac4_flow_ctrl,
 726         .pmt = dwmac4_pmt,
 727         .set_umac_addr = dwmac4_set_umac_addr,
 728         .get_umac_addr = dwmac4_get_umac_addr,
 729         .set_eee_mode = dwmac4_set_eee_mode,
 730         .reset_eee_mode = dwmac4_reset_eee_mode,
 731         .set_eee_timer = dwmac4_set_eee_timer,
 732         .set_eee_pls = dwmac4_set_eee_pls,
 733         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 734         .pcs_rane = dwmac4_rane,
 735         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 736         .debug = dwmac4_debug,
 737         .set_filter = dwmac4_set_filter,
 738 };
 739
 740 static const struct stmmac_ops dwmac410_ops = {
 741         .core_init = dwmac4_core_init,
 742         .set_mac = stmmac_dwmac4_set_mac,
 743         .rx_ipc = dwmac4_rx_ipc_enable,
 744         .rx_queue_enable = dwmac4_rx_queue_enable,
 745         .rx_queue_prio = dwmac4_rx_queue_priority,
 746         .tx_queue_prio = dwmac4_tx_queue_priority,
 747         .rx_queue_routing = dwmac4_tx_queue_routing,
 748         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 749         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 750         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 751         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 752         .config_cbs = dwmac4_config_cbs,
 753         .dump_regs = dwmac4_dump_regs,
 754         .host_irq_status = dwmac4_irq_status,
 755         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 756         .flow_ctrl = dwmac4_flow_ctrl,
 757         .pmt = dwmac4_pmt,
 758         .set_umac_addr = dwmac4_set_umac_addr,
 759         .get_umac_addr = dwmac4_get_umac_addr,
 760         .set_eee_mode = dwmac4_set_eee_mode,
 761         .reset_eee_mode = dwmac4_reset_eee_mode,
 762         .set_eee_timer = dwmac4_set_eee_timer,
 763         .set_eee_pls = dwmac4_set_eee_pls,
 764         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 765         .pcs_rane = dwmac4_rane,
 766         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 767         .debug = dwmac4_debug,
 768         .set_filter = dwmac4_set_filter,
 769 };
 770
 771 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 772                                      int perfect_uc_entries, int *synopsys_id)
 773 {
 774         struct mac_device_info *mac;
 775         u32 hwid = readl(ioaddr + GMAC_VERSION);
 776
 777         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 778         if (!mac)
 779                 return NULL;
 780
 781         mac->pcsr = ioaddr;
 782         mac->multicast_filter_bins = mcbins;
 783         mac->unicast_filter_entries = perfect_uc_entries;
 784         mac->mcast_bits_log2 = 0;
 785
 786         if (mac->multicast_filter_bins)
 787                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 788
 789         mac->link.duplex = GMAC_CONFIG_DM;
 790         mac->link.speed10 = GMAC_CONFIG_PS;
 791         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 792         mac->link.speed1000 = 0;
 793         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 794         mac->mii.addr = GMAC_MDIO_ADDR;
 795         mac->mii.data = GMAC_MDIO_DATA;
 796         mac->mii.addr_shift = 21;
 797         mac->mii.addr_mask = GENMASK(25, 21);
 798         mac->mii.reg_shift = 16;
 799         mac->mii.reg_mask = GENMASK(20, 16);
 800         mac->mii.clk_csr_shift = 8;
 801         mac->mii.clk_csr_mask = GENMASK(11, 8);
 802
 803         /* Get and dump the chip ID */
 804         *synopsys_id = stmmac_get_synopsys_id(hwid);
 805
 806         if (*synopsys_id > DWMAC_CORE_4_00)
 807                 mac->dma = &dwmac410_dma_ops;
 808         else
 809                 mac->dma = &dwmac4_dma_ops;
 810
 811         if (*synopsys_id >= DWMAC_CORE_4_00)
 812                 mac->mac = &dwmac410_ops;
 813         else
 814                 mac->mac = &dwmac4_ops;
 815
 816         return mac;
 817 }