drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h

   1 /*
   2  * Header File to describe the DMA descriptors and related definitions specific
   3  * for DesignWare databook 4.xx.
   4  *
   5  * Copyright (C) 2015  STMicroelectronics Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  12  */
  13
  14 #ifndef __DWMAC4_DESCS_H__
  15 #define __DWMAC4_DESCS_H__
  16
  17 #include <linux/bitops.h>
  18
  19 /* Normal transmit descriptor defines (without split feature) */
  20
  21 /* TDES2 (read format) */
  22 #define TDES2_BUFFER1_SIZE_MASK         GENMASK(13, 0)
  23 #define TDES2_VLAN_TAG_MASK             GENMASK(15, 14)
  24 #define TDES2_BUFFER2_SIZE_MASK         GENMASK(29, 16)
  25 #define TDES2_BUFFER2_SIZE_MASK_SHIFT   16
  26 #define TDES2_TIMESTAMP_ENABLE          BIT(30)
  27 #define TDES2_INTERRUPT_ON_COMPLETION   BIT(31)
  28
  29 /* TDES3 (read format) */
  30 #define TDES3_PACKET_SIZE_MASK          GENMASK(14, 0)
  31 #define TDES3_CHECKSUM_INSERTION_MASK   GENMASK(17, 16)
  32 #define TDES3_CHECKSUM_INSERTION_SHIFT  16
  33 #define TDES3_TCP_PKT_PAYLOAD_MASK      GENMASK(17, 0)
  34 #define TDES3_TCP_SEGMENTATION_ENABLE   BIT(18)
  35 #define TDES3_HDR_LEN_SHIFT             19
  36 #define TDES3_SLOT_NUMBER_MASK          GENMASK(22, 19)
  37 #define TDES3_SA_INSERT_CTRL_MASK       GENMASK(25, 23)
  38 #define TDES3_CRC_PAD_CTRL_MASK         GENMASK(27, 26)
  39
  40 /* TDES3 (write back format) */
  41 #define TDES3_IP_HDR_ERROR              BIT(0)
  42 #define TDES3_DEFERRED                  BIT(1)
  43 #define TDES3_UNDERFLOW_ERROR           BIT(2)
  44 #define TDES3_EXCESSIVE_DEFERRAL        BIT(3)
  45 #define TDES3_COLLISION_COUNT_MASK      GENMASK(7, 4)
  46 #define TDES3_COLLISION_COUNT_SHIFT     4
  47 #define TDES3_EXCESSIVE_COLLISION       BIT(8)
  48 #define TDES3_LATE_COLLISION            BIT(9)
  49 #define TDES3_NO_CARRIER                BIT(10)
  50 #define TDES3_LOSS_CARRIER              BIT(11)
  51 #define TDES3_PAYLOAD_ERROR             BIT(12)
  52 #define TDES3_PACKET_FLUSHED            BIT(13)
  53 #define TDES3_JABBER_TIMEOUT            BIT(14)
  54 #define TDES3_ERROR_SUMMARY             BIT(15)
  55 #define TDES3_TIMESTAMP_STATUS          BIT(17)
  56 #define TDES3_TIMESTAMP_STATUS_SHIFT    17
  57
  58 /* TDES3 context */
  59 #define TDES3_CTXT_TCMSSV               BIT(26)
  60
  61 /* TDES3 Common */
  62 #define TDES3_RS1V                      BIT(26)
  63 #define TDES3_RS1V_SHIFT                26
  64 #define TDES3_LAST_DESCRIPTOR           BIT(28)
  65 #define TDES3_LAST_DESCRIPTOR_SHIFT     28
  66 #define TDES3_FIRST_DESCRIPTOR          BIT(29)
  67 #define TDES3_CONTEXT_TYPE              BIT(30)
  68 #define TDES3_CONTEXT_TYPE_SHIFT        30
  69
  70 /* TDS3 use for both format (read and write back) */
  71 #define TDES3_OWN                       BIT(31)
  72 #define TDES3_OWN_SHIFT                 31
  73
  74 /* Normal receive descriptor defines (without split feature) */
  75
  76 /* RDES0 (write back format) */
  77 #define RDES0_VLAN_TAG_MASK             GENMASK(15, 0)
  78
  79 /* RDES1 (write back format) */
  80 #define RDES1_IP_PAYLOAD_TYPE_MASK      GENMASK(2, 0)
  81 #define RDES1_IP_HDR_ERROR              BIT(3)
  82 #define RDES1_IPV4_HEADER               BIT(4)
  83 #define RDES1_IPV6_HEADER               BIT(5)
  84 #define RDES1_IP_CSUM_BYPASSED          BIT(6)
  85 #define RDES1_IP_CSUM_ERROR             BIT(7)
  86 #define RDES1_PTP_MSG_TYPE_MASK         GENMASK(11, 8)
  87 #define RDES1_PTP_PACKET_TYPE           BIT(12)
  88 #define RDES1_PTP_VER                   BIT(13)
  89 #define RDES1_TIMESTAMP_AVAILABLE       BIT(14)
  90 #define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14
  91 #define RDES1_TIMESTAMP_DROPPED         BIT(15)
  92 #define RDES1_IP_TYPE1_CSUM_MASK        GENMASK(31, 16)
  93
  94 /* RDES2 (write back format) */
  95 #define RDES2_L3_L4_HEADER_SIZE_MASK    GENMASK(9, 0)
  96 #define RDES2_VLAN_FILTER_STATUS        BIT(15)
  97 #define RDES2_SA_FILTER_FAIL            BIT(16)
  98 #define RDES2_DA_FILTER_FAIL            BIT(17)
  99 #define RDES2_HASH_FILTER_STATUS        BIT(18)
 100 #define RDES2_MAC_ADDR_MATCH_MASK       GENMASK(26, 19)
 101 #define RDES2_HASH_VALUE_MATCH_MASK     GENMASK(26, 19)
 102 #define RDES2_L3_FILTER_MATCH           BIT(27)
 103 #define RDES2_L4_FILTER_MATCH           BIT(28)
 104 #define RDES2_L3_L4_FILT_NB_MATCH_MASK  GENMASK(27, 26)
 105 #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26
 106
 107 /* RDES3 (write back format) */
 108 #define RDES3_PACKET_SIZE_MASK          GENMASK(14, 0)
 109 #define RDES3_ERROR_SUMMARY             BIT(15)
 110 #define RDES3_PACKET_LEN_TYPE_MASK      GENMASK(18, 16)
 111 #define RDES3_DRIBBLE_ERROR             BIT(19)
 112 #define RDES3_RECEIVE_ERROR             BIT(20)
 113 #define RDES3_OVERFLOW_ERROR            BIT(21)
 114 #define RDES3_RECEIVE_WATCHDOG          BIT(22)
 115 #define RDES3_GIANT_PACKET              BIT(23)
 116 #define RDES3_CRC_ERROR                 BIT(24)
 117 #define RDES3_RDES0_VALID               BIT(25)
 118 #define RDES3_RDES1_VALID               BIT(26)
 119 #define RDES3_RDES2_VALID               BIT(27)
 120 #define RDES3_LAST_DESCRIPTOR           BIT(28)
 121 #define RDES3_FIRST_DESCRIPTOR          BIT(29)
 122 #define RDES3_CONTEXT_DESCRIPTOR        BIT(30)
 123 #define RDES3_CONTEXT_DESCRIPTOR_SHIFT  30
 124
 125 /* RDES3 (read format) */
 126 #define RDES3_BUFFER1_VALID_ADDR        BIT(24)
 127 #define RDES3_BUFFER2_VALID_ADDR        BIT(25)
 128 #define RDES3_INT_ON_COMPLETION_EN      BIT(30)
 129
 130 /* TDS3 use for both format (read and write back) */
 131 #define RDES3_OWN                       BIT(31)
 132
 133 #endif /* __DWMAC4_DESCS_H__ */