drivers/net/phy/marvell10g.c

   1 /*
   2  * Marvell 10G 88x3310 PHY driver
   3  *
   4  * Based upon the ID registers, this PHY appears to be a mixture of IPs
   5  * from two different companies.
   6  *
   7  * There appears to be several different data paths through the PHY which
   8  * are automatically managed by the PHY.  The following has been determined
   9  * via observation and experimentation for a setup using single-lane Serdes:
  10  *
  11  *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
  12  *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
  13  *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
  14  *
  15  * With XAUI, observation shows:
  16  *
  17  *        XAUI PHYXS -- <appropriate PCS as above>
  18  *
  19  * and no switching of the host interface mode occurs.
  20  *
  21  * If both the fiber and copper ports are connected, the first to gain
  22  * link takes priority and the other port is completely locked out.
  23  */
  24 #include <linux/phy.h>
  25 #include <linux/marvell_phy.h>
  26
  27 enum {
  28         MV_PCS_BASE_T           = 0x0000,
  29         MV_PCS_BASE_R           = 0x1000,
  30         MV_PCS_1000BASEX        = 0x2000,
  31
  32         MV_PCS_PAIRSWAP         = 0x8182,
  33         MV_PCS_PAIRSWAP_MASK    = 0x0003,
  34         MV_PCS_PAIRSWAP_AB      = 0x0002,
  35         MV_PCS_PAIRSWAP_NONE    = 0x0003,
  36
  37         /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
  38          * registers appear to set themselves to the 0x800X when AN is
  39          * restarted, but status registers appear readable from either.
  40          */
  41         MV_AN_CTRL1000          = 0x8000, /* 1000base-T control register */
  42         MV_AN_STAT1000          = 0x8001, /* 1000base-T status register */
  43 };
  44
  45 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
  46                          u16 mask, u16 bits)
  47 {
  48         int old, val, ret;
  49
  50         old = phy_read_mmd(phydev, devad, reg);
  51         if (old < 0)
  52                 return old;
  53
  54         val = (old & ~mask) | (bits & mask);
  55         if (val == old)
  56                 return 0;
  57
  58         ret = phy_write_mmd(phydev, devad, reg, val);
  59
  60         return ret < 0 ? ret : 1;
  61 }
  62
  63 static int mv3310_probe(struct phy_device *phydev)
  64 {
  65         u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
  66
  67         if (!phydev->is_c45 ||
  68             (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
  69                 return -ENODEV;
  70
  71         return 0;
  72 }
  73
  74 /*
  75  * Resetting the MV88X3310 causes it to become non-responsive.  Avoid
  76  * setting the reset bit(s).
  77  */
  78 static int mv3310_soft_reset(struct phy_device *phydev)
  79 {
  80         return 0;
  81 }
  82
  83 static int mv3310_config_init(struct phy_device *phydev)
  84 {
  85         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
  86         u32 mask;
  87         int val;
  88
  89         /* Check that the PHY interface type is compatible */
  90         if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
  91             phydev->interface != PHY_INTERFACE_MODE_XAUI &&
  92             phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
  93             phydev->interface != PHY_INTERFACE_MODE_10GKR)
  94                 return -ENODEV;
  95
  96         __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
  97         __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
  98
  99         if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
 100                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 101                 if (val < 0)
 102                         return val;
 103
 104                 if (val & MDIO_AN_STAT1_ABLE)
 105                         __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
 106         }
 107
 108         val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 109         if (val < 0)
 110                 return val;
 111
 112         /* Ethtool does not support the WAN mode bits */
 113         if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
 114                    MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
 115                    MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
 116                    MDIO_PMA_STAT2_10GBEW))
 117                 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 118         if (val & MDIO_PMA_STAT2_10GBSR)
 119                 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
 120         if (val & MDIO_PMA_STAT2_10GBLR)
 121                 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
 122         if (val & MDIO_PMA_STAT2_10GBER)
 123                 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
 124
 125         if (val & MDIO_PMA_STAT2_EXTABLE) {
 126                 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 127                 if (val < 0)
 128                         return val;
 129
 130                 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
 131                            MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
 132                         __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
 133                 if (val & MDIO_PMA_EXTABLE_10GBLRM)
 134                         __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 135                 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
 136                            MDIO_PMA_EXTABLE_1000BKX))
 137                         __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
 138                 if (val & MDIO_PMA_EXTABLE_10GBLRM)
 139                         __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 140                                   supported);
 141                 if (val & MDIO_PMA_EXTABLE_10GBT)
 142                         __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 143                                   supported);
 144                 if (val & MDIO_PMA_EXTABLE_10GBKX4)
 145                         __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 146                                   supported);
 147                 if (val & MDIO_PMA_EXTABLE_10GBKR)
 148                         __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 149                                   supported);
 150                 if (val & MDIO_PMA_EXTABLE_1000BT)
 151                         __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 152                                   supported);
 153                 if (val & MDIO_PMA_EXTABLE_1000BKX)
 154                         __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 155                                   supported);
 156                 if (val & MDIO_PMA_EXTABLE_100BTX) {
 157                         __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 158                                   supported);
 159                         __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 160                                   supported);
 161                 }
 162                 if (val & MDIO_PMA_EXTABLE_10BT) {
 163                         __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 164                                   supported);
 165                         __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 166                                   supported);
 167                 }
 168         }
 169
 170         if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
 171                 dev_warn(&phydev->mdio.dev,
 172                          "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
 173                          __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
 174
 175         phydev->supported &= mask;
 176         phydev->advertising &= phydev->supported;
 177
 178         return 0;
 179 }
 180
 181 static int mv3310_config_aneg(struct phy_device *phydev)
 182 {
 183         bool changed = false;
 184         u32 advertising;
 185         int ret;
 186
 187         /* We don't support manual MDI control */
 188         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 189
 190         if (phydev->autoneg == AUTONEG_DISABLE) {
 191                 ret = genphy_c45_pma_setup_forced(phydev);
 192                 if (ret < 0)
 193                         return ret;
 194
 195                 return genphy_c45_an_disable_aneg(phydev);
 196         }
 197
 198         phydev->advertising &= phydev->supported;
 199         advertising = phydev->advertising;
 200
 201         ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 202                             ADVERTISE_ALL | ADVERTISE_100BASE4 |
 203                             ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 204                             ethtool_adv_to_mii_adv_t(advertising));
 205         if (ret < 0)
 206                 return ret;
 207         if (ret > 0)
 208                 changed = true;
 209
 210         ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
 211                             ADVERTISE_1000FULL | ADVERTISE_1000HALF,
 212                             ethtool_adv_to_mii_ctrl1000_t(advertising));
 213         if (ret < 0)
 214                 return ret;
 215         if (ret > 0)
 216                 changed = true;
 217
 218         /* 10G control register */
 219         ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 220                             MDIO_AN_10GBT_CTRL_ADV10G,
 221                             advertising & ADVERTISED_10000baseT_Full ?
 222                                 MDIO_AN_10GBT_CTRL_ADV10G : 0);
 223         if (ret < 0)
 224                 return ret;
 225         if (ret > 0)
 226                 changed = true;
 227
 228         if (changed)
 229                 ret = genphy_c45_restart_aneg(phydev);
 230
 231         return ret;
 232 }
 233
 234 static int mv3310_aneg_done(struct phy_device *phydev)
 235 {
 236         int val;
 237
 238         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 239         if (val < 0)
 240                 return val;
 241
 242         if (val & MDIO_STAT1_LSTATUS)
 243                 return 1;
 244
 245         return genphy_c45_aneg_done(phydev);
 246 }
 247
 248 static void mv3310_update_interface(struct phy_device *phydev)
 249 {
 250         if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
 251              phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
 252                 /* The PHY automatically switches its serdes interface (and
 253                  * active PHYXS instance) between Cisco SGMII and 10GBase-KR
 254                  * modes according to the speed.  Florian suggests setting
 255                  * phydev->interface to communicate this to the MAC. Only do
 256                  * this if we are already in either SGMII or 10GBase-KR mode.
 257                  */
 258                 if (phydev->speed == SPEED_10000)
 259                         phydev->interface = PHY_INTERFACE_MODE_10GKR;
 260                 else if (phydev->speed >= SPEED_10 &&
 261                          phydev->speed < SPEED_10000)
 262                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
 263         }
 264 }
 265
 266 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
 267 static int mv3310_read_10gbr_status(struct phy_device *phydev)
 268 {
 269         phydev->link = 1;
 270         phydev->speed = SPEED_10000;
 271         phydev->duplex = DUPLEX_FULL;
 272
 273         mv3310_update_interface(phydev);
 274
 275         return 0;
 276 }
 277
 278 static int mv3310_read_status(struct phy_device *phydev)
 279 {
 280         u32 mmd_mask = phydev->c45_ids.devices_in_package;
 281         int val;
 282
 283         /* The vendor devads do not report link status.  Avoid the PHYXS
 284          * instance as there are three, and its status depends on the MAC
 285          * being appropriately configured for the negotiated speed.
 286          */
 287         mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
 288                       BIT(MDIO_MMD_PHYXS));
 289
 290         phydev->speed = SPEED_UNKNOWN;
 291         phydev->duplex = DUPLEX_UNKNOWN;
 292         phydev->lp_advertising = 0;
 293         phydev->link = 0;
 294         phydev->pause = 0;
 295         phydev->asym_pause = 0;
 296         phydev->mdix = 0;
 297
 298         val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
 299         if (val < 0)
 300                 return val;
 301
 302         if (val & MDIO_STAT1_LSTATUS)
 303                 return mv3310_read_10gbr_status(phydev);
 304
 305         val = genphy_c45_read_link(phydev, mmd_mask);
 306         if (val < 0)
 307                 return val;
 308
 309         phydev->link = val > 0 ? 1 : 0;
 310
 311         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 312         if (val < 0)
 313                 return val;
 314
 315         if (val & MDIO_AN_STAT1_COMPLETE) {
 316                 val = genphy_c45_read_lpa(phydev);
 317                 if (val < 0)
 318                         return val;
 319
 320                 /* Read the link partner's 1G advertisment */
 321                 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
 322                 if (val < 0)
 323                         return val;
 324
 325                 phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
 326
 327                 if (phydev->autoneg == AUTONEG_ENABLE)
 328                         phy_resolve_aneg_linkmode(phydev);
 329         }
 330
 331         if (phydev->autoneg != AUTONEG_ENABLE) {
 332                 val = genphy_c45_read_pma(phydev);
 333                 if (val < 0)
 334                         return val;
 335         }
 336
 337         if (phydev->speed == SPEED_10000) {
 338                 val = genphy_c45_read_mdix(phydev);
 339                 if (val < 0)
 340                         return val;
 341         } else {
 342                 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
 343                 if (val < 0)
 344                         return val;
 345
 346                 switch (val & MV_PCS_PAIRSWAP_MASK) {
 347                 case MV_PCS_PAIRSWAP_AB:
 348                         phydev->mdix = ETH_TP_MDI_X;
 349                         break;
 350                 case MV_PCS_PAIRSWAP_NONE:
 351                         phydev->mdix = ETH_TP_MDI;
 352                         break;
 353                 default:
 354                         phydev->mdix = ETH_TP_MDI_INVALID;
 355                         break;
 356                 }
 357         }
 358
 359         mv3310_update_interface(phydev);
 360
 361         return 0;
 362 }
 363
 364 static struct phy_driver mv3310_drivers[] = {
 365         {
 366                 .phy_id         = 0x002b09aa,
 367                 .phy_id_mask    = MARVELL_PHY_ID_MASK,
 368                 .name           = "mv88x3310",
 369                 .features       = SUPPORTED_10baseT_Full |
 370                                   SUPPORTED_10baseT_Half |
 371                                   SUPPORTED_100baseT_Full |
 372                                   SUPPORTED_100baseT_Half |
 373                                   SUPPORTED_1000baseT_Full |
 374                                   SUPPORTED_Autoneg |
 375                                   SUPPORTED_TP |
 376                                   SUPPORTED_FIBRE |
 377                                   SUPPORTED_10000baseT_Full |
 378                                   SUPPORTED_Backplane,
 379                 .probe          = mv3310_probe,
 380                 .soft_reset     = mv3310_soft_reset,
 381                 .config_init    = mv3310_config_init,
 382                 .config_aneg    = mv3310_config_aneg,
 383                 .aneg_done      = mv3310_aneg_done,
 384                 .read_status    = mv3310_read_status,
 385         },
 386 };
 387
 388 module_phy_driver(mv3310_drivers);
 389
 390 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
 391         { 0x002b09aa, MARVELL_PHY_ID_MASK },
 392         { },
 393 };
 394 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
 395 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
 396 MODULE_LICENSE("GPL");