1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
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8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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61 *****************************************************************************/
63 #ifndef __iwl_fw_api_config_h__
64 #define __iwl_fw_api_config_h__
67 * struct iwl_dqa_enable_cmd
68 * @cmd_queue: the TXQ number of the command queue
70 struct iwl_dqa_enable_cmd
{
72 } __packed
; /* DQA_CONTROL_CMD_API_S_VER_1 */
75 * struct iwl_tx_ant_cfg_cmd
76 * @valid: valid antenna configuration
78 struct iwl_tx_ant_cfg_cmd
{
83 * struct iwl_calib_ctrl - Calibration control struct.
84 * Sent as part of the phy configuration command.
85 * @flow_trigger: bitmap for which calibrations to perform according to
86 * flow triggers, using &enum iwl_calib_cfg
87 * @event_trigger: bitmap for which calibrations to perform according to
88 * event triggers, using &enum iwl_calib_cfg
90 struct iwl_calib_ctrl
{
95 /* This enum defines the bitmap of various calibrations to enable in both
96 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
99 IWL_CALIB_CFG_XTAL_IDX
= BIT(0),
100 IWL_CALIB_CFG_TEMPERATURE_IDX
= BIT(1),
101 IWL_CALIB_CFG_VOLTAGE_READ_IDX
= BIT(2),
102 IWL_CALIB_CFG_PAPD_IDX
= BIT(3),
103 IWL_CALIB_CFG_TX_PWR_IDX
= BIT(4),
104 IWL_CALIB_CFG_DC_IDX
= BIT(5),
105 IWL_CALIB_CFG_BB_FILTER_IDX
= BIT(6),
106 IWL_CALIB_CFG_LO_LEAKAGE_IDX
= BIT(7),
107 IWL_CALIB_CFG_TX_IQ_IDX
= BIT(8),
108 IWL_CALIB_CFG_TX_IQ_SKEW_IDX
= BIT(9),
109 IWL_CALIB_CFG_RX_IQ_IDX
= BIT(10),
110 IWL_CALIB_CFG_RX_IQ_SKEW_IDX
= BIT(11),
111 IWL_CALIB_CFG_SENSITIVITY_IDX
= BIT(12),
112 IWL_CALIB_CFG_CHAIN_NOISE_IDX
= BIT(13),
113 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX
= BIT(14),
114 IWL_CALIB_CFG_ANT_COUPLING_IDX
= BIT(15),
115 IWL_CALIB_CFG_DAC_IDX
= BIT(16),
116 IWL_CALIB_CFG_ABS_IDX
= BIT(17),
117 IWL_CALIB_CFG_AGC_IDX
= BIT(18),
121 * struct iwl_phy_cfg_cmd - Phy configuration command
122 * @phy_cfg: PHY configuration value, uses &enum iwl_fw_phy_cfg
123 * @calib_control: calibration control data
125 struct iwl_phy_cfg_cmd
{
127 struct iwl_calib_ctrl calib_control
;
130 #define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
131 #define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
132 #define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
133 #define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
134 #define PHY_CFG_TX_CHAIN_A BIT(8)
135 #define PHY_CFG_TX_CHAIN_B BIT(9)
136 #define PHY_CFG_TX_CHAIN_C BIT(10)
137 #define PHY_CFG_RX_CHAIN_A BIT(12)
138 #define PHY_CFG_RX_CHAIN_B BIT(13)
139 #define PHY_CFG_RX_CHAIN_C BIT(14)
142 * enum iwl_dc2dc_config_id - flag ids
144 * Ids of dc2dc configuration flags
146 enum iwl_dc2dc_config_id
{
147 DCDC_LOW_POWER_MODE_MSK_SET
= 0x1, /* not used */
148 DCDC_FREQ_TUNE_SET
= 0x2,
149 }; /* MARKER_ID_API_E_VER_1 */
152 * struct iwl_dc2dc_config_cmd - configure dc2dc values
154 * (DC2DC_CONFIG_CMD = 0x83)
156 * Set/Get & configure dc2dc values.
157 * The command always returns the current dc2dc values.
159 * @flags: set/get dc2dc
160 * @enable_low_power_mode: not used.
161 * @dc2dc_freq_tune0: frequency divider - digital domain
162 * @dc2dc_freq_tune1: frequency divider - analog domain
164 struct iwl_dc2dc_config_cmd
{
166 __le32 enable_low_power_mode
; /* not used */
167 __le32 dc2dc_freq_tune0
;
168 __le32 dc2dc_freq_tune1
;
169 } __packed
; /* DC2DC_CONFIG_CMD_API_S_VER_1 */
172 * struct iwl_dc2dc_config_resp - response for iwl_dc2dc_config_cmd
174 * Current dc2dc values returned by the FW.
176 * @dc2dc_freq_tune0: frequency divider - digital domain
177 * @dc2dc_freq_tune1: frequency divider - analog domain
179 struct iwl_dc2dc_config_resp
{
180 __le32 dc2dc_freq_tune0
;
181 __le32 dc2dc_freq_tune1
;
182 } __packed
; /* DC2DC_CONFIG_RESP_API_S_VER_1 */
184 #endif /* __iwl_fw_api_config_h__ */