drivers/net/wireless/intel/iwlwifi/fw/api/rx.h

   1 /******************************************************************************
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   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
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  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called COPYING.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <linuxwifi@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  30  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
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  32  * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
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  61  *****************************************************************************/
  62
  63 #ifndef __iwl_fw_api_rx_h__
  64 #define __iwl_fw_api_rx_h__
  65
  66 /* API for pre-9000 hardware */
  67
  68 #define IWL_RX_INFO_PHY_CNT 8
  69 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
  70 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
  71 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
  72 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
  73 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
  74 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
  75 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
  76
  77 enum iwl_mac_context_info {
  78         MAC_CONTEXT_INFO_NONE,
  79         MAC_CONTEXT_INFO_GSCAN,
  80 };
  81
  82 /**
  83  * struct iwl_rx_phy_info - phy info
  84  * (REPLY_RX_PHY_CMD = 0xc0)
  85  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
  86  * @cfg_phy_cnt: configurable DSP phy data byte count
  87  * @stat_id: configurable DSP phy data set ID
  88  * @reserved1: reserved
  89  * @system_timestamp: GP2  at on air rise
  90  * @timestamp: TSF at on air rise
  91  * @beacon_time_stamp: beacon at on-air rise
  92  * @phy_flags: general phy flags: band, modulation, ...
  93  * @channel: channel number
  94  * @non_cfg_phy: for various implementations of non_cfg_phy
  95  * @rate_n_flags: RATE_MCS_*
  96  * @byte_count: frame's byte-count
  97  * @frame_time: frame's time on the air, based on byte count and frame rate
  98  *      calculation
  99  * @mac_active_msk: what MACs were active when the frame was received
 100  * @mac_context_info: additional info on the context in which the frame was
 101  *      received as defined in &enum iwl_mac_context_info
 102  *
 103  * Before each Rx, the device sends this data. It contains PHY information
 104  * about the reception of the packet.
 105  */
 106 struct iwl_rx_phy_info {
 107         u8 non_cfg_phy_cnt;
 108         u8 cfg_phy_cnt;
 109         u8 stat_id;
 110         u8 reserved1;
 111         __le32 system_timestamp;
 112         __le64 timestamp;
 113         __le32 beacon_time_stamp;
 114         __le16 phy_flags;
 115         __le16 channel;
 116         __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
 117         __le32 rate_n_flags;
 118         __le32 byte_count;
 119         u8 mac_active_msk;
 120         u8 mac_context_info;
 121         __le16 frame_time;
 122 } __packed;
 123
 124 /*
 125  * TCP offload Rx assist info
 126  *
 127  * bits 0:3 - reserved
 128  * bits 4:7 - MIC CRC length
 129  * bits 8:12 - MAC header length
 130  * bit 13 - Padding indication
 131  * bit 14 - A-AMSDU indication
 132  * bit 15 - Offload enabled
 133  */
 134 enum iwl_csum_rx_assist_info {
 135         CSUM_RXA_RESERVED_MASK  = 0x000f,
 136         CSUM_RXA_MICSIZE_MASK   = 0x00f0,
 137         CSUM_RXA_HEADERLEN_MASK = 0x1f00,
 138         CSUM_RXA_PADD           = BIT(13),
 139         CSUM_RXA_AMSDU          = BIT(14),
 140         CSUM_RXA_ENA            = BIT(15)
 141 };
 142
 143 /**
 144  * struct iwl_rx_mpdu_res_start - phy info
 145  * @byte_count: byte count of the frame
 146  * @assist: see &enum iwl_csum_rx_assist_info
 147  */
 148 struct iwl_rx_mpdu_res_start {
 149         __le16 byte_count;
 150         __le16 assist;
 151 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
 152
 153 /**
 154  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
 155  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
 156  * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK
 157  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
 158  * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive
 159  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
 160  * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position
 161  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
 162  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
 163  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
 164  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
 165  */
 166 enum iwl_rx_phy_flags {
 167         RX_RES_PHY_FLAGS_BAND_24        = BIT(0),
 168         RX_RES_PHY_FLAGS_MOD_CCK        = BIT(1),
 169         RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
 170         RX_RES_PHY_FLAGS_NARROW_BAND    = BIT(3),
 171         RX_RES_PHY_FLAGS_ANTENNA        = (0x7 << 4),
 172         RX_RES_PHY_FLAGS_ANTENNA_POS    = 4,
 173         RX_RES_PHY_FLAGS_AGG            = BIT(7),
 174         RX_RES_PHY_FLAGS_OFDM_HT        = BIT(8),
 175         RX_RES_PHY_FLAGS_OFDM_GF        = BIT(9),
 176         RX_RES_PHY_FLAGS_OFDM_VHT       = BIT(10),
 177 };
 178
 179 /**
 180  * enum iwl_mvm_rx_status - written by fw for each Rx packet
 181  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
 182  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
 183  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found
 184  * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid
 185  * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable
 186  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
 187  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
 188  *      in the driver.
 189  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
 190  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
 191  *      alg = CCM only. Checks replay attack for 11w frames. Relevant only if
 192  *      %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
 193  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
 194  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
 195  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
 196  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
 197  * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension
 198  *      algorithm
 199  * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
 200  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
 201  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
 202  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
 203  * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP)
 204  * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done
 205  * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
 206  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
 207  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
 208  * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
 209  * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
 210  * @RX_MPDU_RES_STATUS_FILTERING_MSK: filter status
 211  * @RX_MPDU_RES_STATUS2_FILTERING_MSK: filter status 2
 212  */
 213 enum iwl_mvm_rx_status {
 214         RX_MPDU_RES_STATUS_CRC_OK                       = BIT(0),
 215         RX_MPDU_RES_STATUS_OVERRUN_OK                   = BIT(1),
 216         RX_MPDU_RES_STATUS_SRC_STA_FOUND                = BIT(2),
 217         RX_MPDU_RES_STATUS_KEY_VALID                    = BIT(3),
 218         RX_MPDU_RES_STATUS_KEY_PARAM_OK                 = BIT(4),
 219         RX_MPDU_RES_STATUS_ICV_OK                       = BIT(5),
 220         RX_MPDU_RES_STATUS_MIC_OK                       = BIT(6),
 221         RX_MPDU_RES_STATUS_TTAK_OK                      = BIT(7),
 222         RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR         = BIT(7),
 223         RX_MPDU_RES_STATUS_SEC_NO_ENC                   = (0 << 8),
 224         RX_MPDU_RES_STATUS_SEC_WEP_ENC                  = (1 << 8),
 225         RX_MPDU_RES_STATUS_SEC_CCM_ENC                  = (2 << 8),
 226         RX_MPDU_RES_STATUS_SEC_TKIP_ENC                 = (3 << 8),
 227         RX_MPDU_RES_STATUS_SEC_EXT_ENC                  = (4 << 8),
 228         RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC             = (6 << 8),
 229         RX_MPDU_RES_STATUS_SEC_ENC_ERR                  = (7 << 8),
 230         RX_MPDU_RES_STATUS_SEC_ENC_MSK                  = (7 << 8),
 231         RX_MPDU_RES_STATUS_DEC_DONE                     = BIT(11),
 232         RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP               = BIT(13),
 233         RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT               = BIT(14),
 234         RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME             = BIT(15),
 235         RX_MPDU_RES_STATUS_CSUM_DONE                    = BIT(16),
 236         RX_MPDU_RES_STATUS_CSUM_OK                      = BIT(17),
 237         RX_MDPU_RES_STATUS_STA_ID_SHIFT                 = 24,
 238         RX_MPDU_RES_STATUS_STA_ID_MSK                   = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
 239         RX_MPDU_RES_STATUS_FILTERING_MSK                = (0xc00000),
 240         RX_MPDU_RES_STATUS2_FILTERING_MSK               = (0xc0000000),
 241 };
 242
 243 /* 9000 series API */
 244 enum iwl_rx_mpdu_mac_flags1 {
 245         IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK         = 0x03,
 246         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK      = 0xf0,
 247         /* shift should be 4, but the length is measured in 2-byte
 248          * words, so shifting only by 3 gives a byte result
 249          */
 250         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT     = 3,
 251 };
 252
 253 enum iwl_rx_mpdu_mac_flags2 {
 254         /* in 2-byte words */
 255         IWL_RX_MPDU_MFLG2_HDR_LEN_MASK          = 0x1f,
 256         IWL_RX_MPDU_MFLG2_PAD                   = 0x20,
 257         IWL_RX_MPDU_MFLG2_AMSDU                 = 0x40,
 258 };
 259
 260 enum iwl_rx_mpdu_amsdu_info {
 261         IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK     = 0x7f,
 262         IWL_RX_MPDU_AMSDU_LAST_SUBFRAME         = 0x80,
 263 };
 264
 265 enum iwl_rx_l3_proto_values {
 266         IWL_RX_L3_TYPE_NONE,
 267         IWL_RX_L3_TYPE_IPV4,
 268         IWL_RX_L3_TYPE_IPV4_FRAG,
 269         IWL_RX_L3_TYPE_IPV6_FRAG,
 270         IWL_RX_L3_TYPE_IPV6,
 271         IWL_RX_L3_TYPE_IPV6_IN_IPV4,
 272         IWL_RX_L3_TYPE_ARP,
 273         IWL_RX_L3_TYPE_EAPOL,
 274 };
 275
 276 #define IWL_RX_L3_PROTO_POS 4
 277
 278 enum iwl_rx_l3l4_flags {
 279         IWL_RX_L3L4_IP_HDR_CSUM_OK              = BIT(0),
 280         IWL_RX_L3L4_TCP_UDP_CSUM_OK             = BIT(1),
 281         IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH         = BIT(2),
 282         IWL_RX_L3L4_TCP_ACK                     = BIT(3),
 283         IWL_RX_L3L4_L3_PROTO_MASK               = 0xf << IWL_RX_L3_PROTO_POS,
 284         IWL_RX_L3L4_L4_PROTO_MASK               = 0xf << 8,
 285         IWL_RX_L3L4_RSS_HASH_MASK               = 0xf << 12,
 286 };
 287
 288 enum iwl_rx_mpdu_status {
 289         IWL_RX_MPDU_STATUS_CRC_OK               = BIT(0),
 290         IWL_RX_MPDU_STATUS_OVERRUN_OK           = BIT(1),
 291         IWL_RX_MPDU_STATUS_SRC_STA_FOUND        = BIT(2),
 292         IWL_RX_MPDU_STATUS_KEY_VALID            = BIT(3),
 293         IWL_RX_MPDU_STATUS_KEY_PARAM_OK         = BIT(4),
 294         IWL_RX_MPDU_STATUS_ICV_OK               = BIT(5),
 295         IWL_RX_MPDU_STATUS_MIC_OK               = BIT(6),
 296         IWL_RX_MPDU_RES_STATUS_TTAK_OK          = BIT(7),
 297         IWL_RX_MPDU_STATUS_SEC_MASK             = 0x7 << 8,
 298         IWL_RX_MPDU_STATUS_SEC_NONE             = 0x0 << 8,
 299         IWL_RX_MPDU_STATUS_SEC_WEP              = 0x1 << 8,
 300         IWL_RX_MPDU_STATUS_SEC_CCM              = 0x2 << 8,
 301         IWL_RX_MPDU_STATUS_SEC_TKIP             = 0x3 << 8,
 302         IWL_RX_MPDU_STATUS_SEC_EXT_ENC          = 0x4 << 8,
 303         IWL_RX_MPDU_STATUS_SEC_GCM              = 0x5 << 8,
 304         IWL_RX_MPDU_STATUS_DECRYPTED            = BIT(11),
 305         IWL_RX_MPDU_STATUS_WEP_MATCH            = BIT(12),
 306         IWL_RX_MPDU_STATUS_EXT_IV_MATCH         = BIT(13),
 307         IWL_RX_MPDU_STATUS_KEY_ID_MATCH         = BIT(14),
 308         IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME     = BIT(15),
 309 };
 310
 311 enum iwl_rx_mpdu_hash_filter {
 312         IWL_RX_MPDU_HF_A1_HASH_MASK             = 0x3f,
 313         IWL_RX_MPDU_HF_FILTER_STATUS_MASK       = 0xc0,
 314 };
 315
 316 enum iwl_rx_mpdu_sta_id_flags {
 317         IWL_RX_MPDU_SIF_STA_ID_MASK             = 0x1f,
 318         IWL_RX_MPDU_SIF_RRF_ABORT               = 0x20,
 319         IWL_RX_MPDU_SIF_FILTER_STATUS_MASK      = 0xc0,
 320 };
 321
 322 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
 323
 324 enum iwl_rx_mpdu_reorder_data {
 325         IWL_RX_MPDU_REORDER_NSSN_MASK           = 0x00000fff,
 326         IWL_RX_MPDU_REORDER_SN_MASK             = 0x00fff000,
 327         IWL_RX_MPDU_REORDER_SN_SHIFT            = 12,
 328         IWL_RX_MPDU_REORDER_BAID_MASK           = 0x7f000000,
 329         IWL_RX_MPDU_REORDER_BAID_SHIFT          = 24,
 330         IWL_RX_MPDU_REORDER_BA_OLD_SN           = 0x80000000,
 331 };
 332
 333 enum iwl_rx_mpdu_phy_info {
 334         IWL_RX_MPDU_PHY_AMPDU           = BIT(5),
 335         IWL_RX_MPDU_PHY_AMPDU_TOGGLE    = BIT(6),
 336         IWL_RX_MPDU_PHY_SHORT_PREAMBLE  = BIT(7),
 337         IWL_RX_MPDU_PHY_TSF_OVERLOAD    = BIT(8),
 338 };
 339
 340 enum iwl_rx_mpdu_mac_info {
 341         IWL_RX_MPDU_PHY_MAC_INDEX_MASK          = 0x0f,
 342         IWL_RX_MPDU_PHY_PHY_INDEX_MASK          = 0xf0,
 343 };
 344
 345 /**
 346  * struct iwl_rx_mpdu_desc - RX MPDU descriptor
 347  */
 348 struct iwl_rx_mpdu_desc {
 349         /* DW2 */
 350         /**
 351          * @mpdu_len: MPDU length
 352          */
 353         __le16 mpdu_len;
 354         /**
 355          * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1
 356          */
 357         u8 mac_flags1;
 358         /**
 359          * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2
 360          */
 361         u8 mac_flags2;
 362         /* DW3 */
 363         /**
 364          * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info
 365          */
 366         u8 amsdu_info;
 367         /**
 368          * @phy_info: &enum iwl_rx_mpdu_phy_info
 369          */
 370         __le16 phy_info;
 371         /**
 372          * @mac_phy_idx: MAC/PHY index
 373          */
 374         u8 mac_phy_idx;
 375         /* DW4 - carries csum data only when rpa_en == 1 */
 376         /**
 377          * @raw_csum: raw checksum (alledgedly unreliable)
 378          */
 379         __le16 raw_csum;
 380         /**
 381          * @l3l4_flags: &enum iwl_rx_l3l4_flags
 382          */
 383         __le16 l3l4_flags;
 384         /* DW5 */
 385         /**
 386          * @status: &enum iwl_rx_mpdu_status
 387          */
 388         __le16 status;
 389         /**
 390          * @hash_filter: hash filter value
 391          */
 392         u8 hash_filter;
 393         /**
 394          * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags
 395          */
 396         u8 sta_id_flags;
 397         /* DW6 */
 398         /**
 399          * @reorder_data: &enum iwl_rx_mpdu_reorder_data
 400          */
 401         __le32 reorder_data;
 402         /* DW7 - carries rss_hash only when rpa_en == 1 */
 403         /**
 404          * @rss_hash: RSS hash value
 405          */
 406         __le32 rss_hash;
 407         /* DW8 - carries filter_match only when rpa_en == 1 */
 408         /**
 409          * @filter_match: filter match value
 410          */
 411         __le32 filter_match;
 412         /* DW9 */
 413         /**
 414          * @rate_n_flags: RX rate/flags encoding
 415          */
 416         __le32 rate_n_flags;
 417         /* DW10 */
 418         /**
 419          * @energy_a: energy chain A
 420          */
 421         u8 energy_a;
 422         /**
 423          * @energy_b: energy chain B
 424          */
 425         u8 energy_b;
 426         /**
 427          * @channel: channel number
 428          */
 429         u8 channel;
 430         /**
 431          * @mac_context: MAC context mask
 432          */
 433         u8 mac_context;
 434         /* DW11 */
 435         /**
 436          * @gp2_on_air_rise: GP2 timer value on air rise (INA)
 437          */
 438         __le32 gp2_on_air_rise;
 439         /* DW12 & DW13 */
 440         /**
 441          * @tsf_on_air_rise:
 442          * TSF value on air rise (INA), only valid if
 443          * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
 444          */
 445         __le64 tsf_on_air_rise;
 446 } __packed;
 447
 448 struct iwl_frame_release {
 449         u8 baid;
 450         u8 reserved;
 451         __le16 nssn;
 452 };
 453
 454 enum iwl_rss_hash_func_en {
 455         IWL_RSS_HASH_TYPE_IPV4_TCP,
 456         IWL_RSS_HASH_TYPE_IPV4_UDP,
 457         IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
 458         IWL_RSS_HASH_TYPE_IPV6_TCP,
 459         IWL_RSS_HASH_TYPE_IPV6_UDP,
 460         IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
 461 };
 462
 463 #define IWL_RSS_HASH_KEY_CNT 10
 464 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
 465 #define IWL_RSS_ENABLE 1
 466
 467 /**
 468  * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
 469  *
 470  * @flags: 1 - enable, 0 - disable
 471  * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
 472  * @reserved: reserved
 473  * @secret_key: 320 bit input of random key configuration from driver
 474  * @indirection_table: indirection table
 475  */
 476 struct iwl_rss_config_cmd {
 477         __le32 flags;
 478         u8 hash_mask;
 479         u8 reserved[3];
 480         __le32 secret_key[IWL_RSS_HASH_KEY_CNT];
 481         u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
 482 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
 483
 484 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128
 485 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
 486 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
 487
 488 /**
 489  * struct iwl_rxq_sync_cmd - RXQ notification trigger
 490  *
 491  * @flags: flags of the notification. bit 0:3 are the sender queue
 492  * @rxq_mask: rx queues to send the notification on
 493  * @count: number of bytes in payload, should be DWORD aligned
 494  * @payload: data to send to rx queues
 495  */
 496 struct iwl_rxq_sync_cmd {
 497         __le32 flags;
 498         __le32 rxq_mask;
 499         __le32 count;
 500         u8 payload[];
 501 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 502
 503 /**
 504  * struct iwl_rxq_sync_notification - Notification triggered by RXQ
 505  * sync command
 506  *
 507  * @count: number of bytes in payload
 508  * @payload: data to send to rx queues
 509  */
 510 struct iwl_rxq_sync_notification {
 511         __le32 count;
 512         u8 payload[];
 513 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 514
 515 /**
 516  * enum iwl_mvm_rxq_notif_type - Internal message identifier
 517  *
 518  * @IWL_MVM_RXQ_EMPTY: empty sync notification
 519  * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
 520  */
 521 enum iwl_mvm_rxq_notif_type {
 522         IWL_MVM_RXQ_EMPTY,
 523         IWL_MVM_RXQ_NOTIF_DEL_BA,
 524 };
 525
 526 /**
 527  * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
 528  * in &iwl_rxq_sync_cmd. Should be DWORD aligned.
 529  * FW is agnostic to the payload, so there are no endianity requirements.
 530  *
 531  * @type: value from &iwl_mvm_rxq_notif_type
 532  * @sync: ctrl path is waiting for all notifications to be received
 533  * @cookie: internal cookie to identify old notifications
 534  * @data: payload
 535  */
 536 struct iwl_mvm_internal_rxq_notif {
 537         u16 type;
 538         u16 sync;
 539         u32 cookie;
 540         u8 data[];
 541 } __packed;
 542
 543 /**
 544  * enum iwl_mvm_pm_event - type of station PM event
 545  * @IWL_MVM_PM_EVENT_AWAKE: station woke up
 546  * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep
 547  * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger
 548  * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll
 549  */
 550 enum iwl_mvm_pm_event {
 551         IWL_MVM_PM_EVENT_AWAKE,
 552         IWL_MVM_PM_EVENT_ASLEEP,
 553         IWL_MVM_PM_EVENT_UAPSD,
 554         IWL_MVM_PM_EVENT_PS_POLL,
 555 }; /* PEER_PM_NTFY_API_E_VER_1 */
 556
 557 /**
 558  * struct iwl_mvm_pm_state_notification - station PM state notification
 559  * @sta_id: station ID of the station changing state
 560  * @type: the new powersave state, see &enum iwl_mvm_pm_event
 561  */
 562 struct iwl_mvm_pm_state_notification {
 563         u8 sta_id;
 564         u8 type;
 565         /* private: */
 566         __le16 reserved;
 567 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */
 568
 569 #define BA_WINDOW_STREAMS_MAX           16
 570 #define BA_WINDOW_STATUS_TID_MSK        0x000F
 571 #define BA_WINDOW_STATUS_STA_ID_POS     4
 572 #define BA_WINDOW_STATUS_STA_ID_MSK     0x01F0
 573 #define BA_WINDOW_STATUS_VALID_MSK      BIT(9)
 574
 575 /**
 576  * struct iwl_ba_window_status_notif - reordering window's status notification
 577  * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
 578  * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid
 579  * @start_seq_num: the start sequence number of the bitmap
 580  * @mpdu_rx_count: the number of received MPDUs since entering D0i3
 581  */
 582 struct iwl_ba_window_status_notif {
 583         __le64 bitmap[BA_WINDOW_STREAMS_MAX];
 584         __le16 ra_tid[BA_WINDOW_STREAMS_MAX];
 585         __le32 start_seq_num[BA_WINDOW_STREAMS_MAX];
 586         __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX];
 587 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */
 588
 589 #endif /* __iwl_fw_api_rx_h__ */