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62 #ifndef __iwl_fw_api_txq_h__
63 #define __iwl_fw_api_txq_h__
68 * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW
69 * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames
70 * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames
71 * @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using
72 * monitor mode. Note this queue is the same as the queue for P2P device
73 * but we can't have active monitor mode along with P2P device anyway.
74 * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames
75 * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure
76 * that we are never left without the possibility to connect to an AP.
77 * @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames.
78 * Each MGMT queue is mapped to a single STA
79 * MGMT frames are frames that return true on ieee80211_is_mgmt()
80 * @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames
81 * @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe
83 * @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames.
84 * DATA frames are intended for !ieee80211_is_mgmt() frames, but if
85 * the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues
87 * @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames
89 enum iwl_mvm_dqa_txq
{
90 IWL_MVM_DQA_CMD_QUEUE
= 0,
91 IWL_MVM_DQA_AUX_QUEUE
= 1,
92 IWL_MVM_DQA_P2P_DEVICE_QUEUE
= 2,
93 IWL_MVM_DQA_INJECT_MONITOR_QUEUE
= 2,
94 IWL_MVM_DQA_GCAST_QUEUE
= 3,
95 IWL_MVM_DQA_BSS_CLIENT_QUEUE
= 4,
96 IWL_MVM_DQA_MIN_MGMT_QUEUE
= 5,
97 IWL_MVM_DQA_MAX_MGMT_QUEUE
= 8,
98 IWL_MVM_DQA_AP_PROBE_RESP_QUEUE
= 9,
99 IWL_MVM_DQA_MIN_DATA_QUEUE
= 10,
100 IWL_MVM_DQA_MAX_DATA_QUEUE
= 31,
103 enum iwl_mvm_tx_fifo
{
104 IWL_MVM_TX_FIFO_BK
= 0,
108 IWL_MVM_TX_FIFO_MCAST
= 5,
109 IWL_MVM_TX_FIFO_CMD
= 7,
112 enum iwl_gen2_tx_fifo
{
113 IWL_GEN2_TX_FIFO_CMD
= 0,
114 IWL_GEN2_EDCA_TX_FIFO_BK
,
115 IWL_GEN2_EDCA_TX_FIFO_BE
,
116 IWL_GEN2_EDCA_TX_FIFO_VI
,
117 IWL_GEN2_EDCA_TX_FIFO_VO
,
118 IWL_GEN2_TRIG_TX_FIFO_BK
,
119 IWL_GEN2_TRIG_TX_FIFO_BE
,
120 IWL_GEN2_TRIG_TX_FIFO_VI
,
121 IWL_GEN2_TRIG_TX_FIFO_VO
,
125 * enum iwl_tx_queue_cfg_actions - TXQ config options
126 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue
127 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format
129 enum iwl_tx_queue_cfg_actions
{
130 TX_QUEUE_CFG_ENABLE_QUEUE
= BIT(0),
131 TX_QUEUE_CFG_TFD_SHORT_FORMAT
= BIT(1),
135 * struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command
136 * @sta_id: station id
137 * @tid: tid of the queue
138 * @flags: see &enum iwl_tx_queue_cfg_actions
139 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.
140 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)
141 * @byte_cnt_addr: address of byte count table
142 * @tfdq_addr: address of TFD circular buffer
144 struct iwl_tx_queue_cfg_cmd
{
149 __le64 byte_cnt_addr
;
151 } __packed
; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */
154 * struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config
155 * @queue_number: queue number assigned to this RA -TID
156 * @flags: set on failure
157 * @write_pointer: initial value for write pointer
158 * @reserved: reserved
160 struct iwl_tx_queue_cfg_rsp
{
163 __le16 write_pointer
;
165 } __packed
; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */
167 #endif /* __iwl_fw_api_txq_h__ */