drivers/net/wireless/mediatek/mt76/mt76x2_dfs.h

   1 /*
   2  * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __MT76x2_DFS_H
  18 #define __MT76x2_DFS_H
  19
  20 #include <linux/types.h>
  21 #include <linux/nl80211.h>
  22
  23 #define MT_DFS_GP_INTERVAL              (10 << 4) /* 64 us unit */
  24 #define MT_DFS_NUM_ENGINES              4
  25
  26 /* bbp params */
  27 #define MT_DFS_SYM_ROUND                0
  28 #define MT_DFS_DELTA_DELAY              2
  29 #define MT_DFS_VGA_MASK                 0
  30 #define MT_DFS_PWR_GAIN_OFFSET          3
  31 #define MT_DFS_PWR_DOWN_TIME            0xf
  32 #define MT_DFS_RX_PE_MASK               0xff
  33 #define MT_DFS_PKT_END_MASK             0
  34 #define MT_DFS_CH_EN                    0xf
  35
  36 struct mt76x2_radar_specs {
  37         u8 mode;
  38         u16 avg_len;
  39         u16 e_low;
  40         u16 e_high;
  41         u16 w_low;
  42         u16 w_high;
  43         u16 w_margin;
  44         u32 t_low;
  45         u32 t_high;
  46         u16 t_margin;
  47         u32 b_low;
  48         u32 b_high;
  49         u32 event_expiration;
  50         u16 pwr_jmp;
  51 };
  52
  53 struct mt76x2_dfs_hw_pulse {
  54         u8 engine;
  55         u32 period;
  56         u32 w1;
  57         u32 w2;
  58         u32 burst;
  59 };
  60
  61 struct mt76x2_dfs_engine_stats {
  62         u32 hw_pattern;
  63         u32 hw_pulse_discarded;
  64 };
  65
  66 struct mt76x2_dfs_pattern_detector {
  67         enum nl80211_dfs_regions region;
  68
  69         u8 chirp_pulse_cnt;
  70         u32 chirp_pulse_ts;
  71
  72         struct mt76x2_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];
  73         struct tasklet_struct dfs_tasklet;
  74 };
  75
  76 void mt76x2_dfs_init_params(struct mt76x2_dev *dev);
  77 void mt76x2_dfs_init_detector(struct mt76x2_dev *dev);
  78 void mt76x2_dfs_adjust_agc(struct mt76x2_dev *dev);
  79 void mt76x2_dfs_set_domain(struct mt76x2_dev *dev,
  80                            enum nl80211_dfs_regions region);
  81
  82 #endif /* __MT76x2_DFS_H */