drivers/pci/dwc/pci-keystone-dw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DesignWare application register space functions for Keystone PCI controller
   4  *
   5  * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   6  *              http://www.ti.com
   7  *
   8  * Author: Murali Karicheri <m-karicheri2@ti.com>
   9  */
  10
  11 #include <linux/irq.h>
  12 #include <linux/irqdomain.h>
  13 #include <linux/irqreturn.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_pci.h>
  17 #include <linux/pci.h>
  18 #include <linux/platform_device.h>
  19
  20 #include "pcie-designware.h"
  21 #include "pci-keystone.h"
  22
  23 /* Application register defines */
  24 #define LTSSM_EN_VAL                    1
  25 #define LTSSM_STATE_MASK                0x1f
  26 #define LTSSM_STATE_L0                  0x11
  27 #define DBI_CS2_EN_VAL                  0x20
  28 #define OB_XLAT_EN_VAL                  2
  29
  30 /* Application registers */
  31 #define CMD_STATUS                      0x004
  32 #define CFG_SETUP                       0x008
  33 #define OB_SIZE                         0x030
  34 #define CFG_PCIM_WIN_SZ_IDX             3
  35 #define CFG_PCIM_WIN_CNT                32
  36 #define SPACE0_REMOTE_CFG_OFFSET        0x1000
  37 #define OB_OFFSET_INDEX(n)              (0x200 + (8 * n))
  38 #define OB_OFFSET_HI(n)                 (0x204 + (8 * n))
  39
  40 /* IRQ register defines */
  41 #define IRQ_EOI                         0x050
  42 #define IRQ_STATUS                      0x184
  43 #define IRQ_ENABLE_SET                  0x188
  44 #define IRQ_ENABLE_CLR                  0x18c
  45
  46 #define MSI_IRQ                         0x054
  47 #define MSI0_IRQ_STATUS                 0x104
  48 #define MSI0_IRQ_ENABLE_SET             0x108
  49 #define MSI0_IRQ_ENABLE_CLR             0x10c
  50 #define IRQ_STATUS                      0x184
  51 #define MSI_IRQ_OFFSET                  4
  52
  53 /* Error IRQ bits */
  54 #define ERR_AER         BIT(5)  /* ECRC error */
  55 #define ERR_AXI         BIT(4)  /* AXI tag lookup fatal error */
  56 #define ERR_CORR        BIT(3)  /* Correctable error */
  57 #define ERR_NONFATAL    BIT(2)  /* Non-fatal error */
  58 #define ERR_FATAL       BIT(1)  /* Fatal error */
  59 #define ERR_SYS         BIT(0)  /* System (fatal, non-fatal, or correctable) */
  60 #define ERR_IRQ_ALL     (ERR_AER | ERR_AXI | ERR_CORR | \
  61                          ERR_NONFATAL | ERR_FATAL | ERR_SYS)
  62 #define ERR_FATAL_IRQ   (ERR_FATAL | ERR_AXI)
  63 #define ERR_IRQ_STATUS_RAW              0x1c0
  64 #define ERR_IRQ_STATUS                  0x1c4
  65 #define ERR_IRQ_ENABLE_SET              0x1c8
  66 #define ERR_IRQ_ENABLE_CLR              0x1cc
  67
  68 /* Config space registers */
  69 #define DEBUG0                          0x728
  70
  71 #define to_keystone_pcie(x)     dev_get_drvdata((x)->dev)
  72
  73 static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
  74                                              u32 *bit_pos)
  75 {
  76         *reg_offset = offset % 8;
  77         *bit_pos = offset >> 3;
  78 }
  79
  80 phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
  81 {
  82         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  83         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  84
  85         return ks_pcie->app.start + MSI_IRQ;
  86 }
  87
  88 static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
  89 {
  90         return readl(ks_pcie->va_app_base + offset);
  91 }
  92
  93 static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
  94 {
  95         writel(val, ks_pcie->va_app_base + offset);
  96 }
  97
  98 void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
  99 {
 100         struct dw_pcie *pci = ks_pcie->pci;
 101         struct pcie_port *pp = &pci->pp;
 102         struct device *dev = pci->dev;
 103         u32 pending, vector;
 104         int src, virq;
 105
 106         pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
 107
 108         /*
 109          * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
 110          * shows 1, 9, 17, 25 and so forth
 111          */
 112         for (src = 0; src < 4; src++) {
 113                 if (BIT(src) & pending) {
 114                         vector = offset + (src << 3);
 115                         virq = irq_linear_revmap(pp->irq_domain, vector);
 116                         dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
 117                                 src, vector, virq);
 118                         generic_handle_irq(virq);
 119                 }
 120         }
 121 }
 122
 123 static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
 124 {
 125         u32 offset, reg_offset, bit_pos;
 126         struct keystone_pcie *ks_pcie;
 127         struct msi_desc *msi;
 128         struct pcie_port *pp;
 129         struct dw_pcie *pci;
 130
 131         msi = irq_data_get_msi_desc(d);
 132         pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 133         pci = to_dw_pcie_from_pp(pp);
 134         ks_pcie = to_keystone_pcie(pci);
 135         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 136         update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
 137
 138         ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
 139                          BIT(bit_pos));
 140         ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
 141 }
 142
 143 void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 144 {
 145         u32 reg_offset, bit_pos;
 146         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 147         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 148
 149         update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 150         ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
 151                          BIT(bit_pos));
 152 }
 153
 154 void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 155 {
 156         u32 reg_offset, bit_pos;
 157         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 158         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 159
 160         update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 161         ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
 162                          BIT(bit_pos));
 163 }
 164
 165 static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
 166 {
 167         struct msi_desc *msi;
 168         struct pcie_port *pp;
 169         u32 offset;
 170
 171         msi = irq_data_get_msi_desc(d);
 172         pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 173         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 174
 175         /* Mask the end point if PVM implemented */
 176         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 177                 if (msi->msi_attrib.maskbit)
 178                         pci_msi_mask_irq(d);
 179         }
 180
 181         ks_dw_pcie_msi_clear_irq(pp, offset);
 182 }
 183
 184 static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
 185 {
 186         struct msi_desc *msi;
 187         struct pcie_port *pp;
 188         u32 offset;
 189
 190         msi = irq_data_get_msi_desc(d);
 191         pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 192         offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 193
 194         /* Mask the end point if PVM implemented */
 195         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 196                 if (msi->msi_attrib.maskbit)
 197                         pci_msi_unmask_irq(d);
 198         }
 199
 200         ks_dw_pcie_msi_set_irq(pp, offset);
 201 }
 202
 203 static struct irq_chip ks_dw_pcie_msi_irq_chip = {
 204         .name = "Keystone-PCIe-MSI-IRQ",
 205         .irq_ack = ks_dw_pcie_msi_irq_ack,
 206         .irq_mask = ks_dw_pcie_msi_irq_mask,
 207         .irq_unmask = ks_dw_pcie_msi_irq_unmask,
 208 };
 209
 210 static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 211                               irq_hw_number_t hwirq)
 212 {
 213         irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
 214                                  handle_level_irq);
 215         irq_set_chip_data(irq, domain->host_data);
 216
 217         return 0;
 218 }
 219
 220 static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
 221         .map = ks_dw_pcie_msi_map,
 222 };
 223
 224 int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
 225 {
 226         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 227         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 228         struct device *dev = pci->dev;
 229         int i;
 230
 231         pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
 232                                         MAX_MSI_IRQS,
 233                                         &ks_dw_pcie_msi_domain_ops,
 234                                         chip);
 235         if (!pp->irq_domain) {
 236                 dev_err(dev, "irq domain init failed\n");
 237                 return -ENXIO;
 238         }
 239
 240         for (i = 0; i < MAX_MSI_IRQS; i++)
 241                 irq_create_mapping(pp->irq_domain, i);
 242
 243         return 0;
 244 }
 245
 246 void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
 247 {
 248         int i;
 249
 250         for (i = 0; i < PCI_NUM_INTX; i++)
 251                 ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
 252 }
 253
 254 void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
 255 {
 256         struct dw_pcie *pci = ks_pcie->pci;
 257         struct device *dev = pci->dev;
 258         u32 pending;
 259         int virq;
 260
 261         pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
 262
 263         if (BIT(0) & pending) {
 264                 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
 265                 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
 266                 generic_handle_irq(virq);
 267         }
 268
 269         /* EOI the INTx interrupt */
 270         ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
 271 }
 272
 273 void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
 274 {
 275         ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
 276 }
 277
 278 irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
 279 {
 280         u32 status;
 281
 282         status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
 283         if (!status)
 284                 return IRQ_NONE;
 285
 286         if (status & ERR_FATAL_IRQ)
 287                 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
 288                         status);
 289
 290         /* Ack the IRQ; status bits are RW1C */
 291         ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
 292         return IRQ_HANDLED;
 293 }
 294
 295 static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
 296 {
 297 }
 298
 299 static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
 300 {
 301 }
 302
 303 static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
 304 {
 305 }
 306
 307 static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
 308         .name = "Keystone-PCI-Legacy-IRQ",
 309         .irq_ack = ks_dw_pcie_ack_legacy_irq,
 310         .irq_mask = ks_dw_pcie_mask_legacy_irq,
 311         .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
 312 };
 313
 314 static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
 315                                 unsigned int irq, irq_hw_number_t hw_irq)
 316 {
 317         irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
 318                                  handle_level_irq);
 319         irq_set_chip_data(irq, d->host_data);
 320
 321         return 0;
 322 }
 323
 324 static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
 325         .map = ks_dw_pcie_init_legacy_irq_map,
 326         .xlate = irq_domain_xlate_onetwocell,
 327 };
 328
 329 /**
 330  * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
 331  * registers
 332  *
 333  * Since modification of dbi_cs2 involves different clock domain, read the
 334  * status back to ensure the transition is complete.
 335  */
 336 static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
 337 {
 338         u32 val;
 339
 340         val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 341         ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
 342
 343         do {
 344                 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 345         } while (!(val & DBI_CS2_EN_VAL));
 346 }
 347
 348 /**
 349  * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
 350  *
 351  * Since modification of dbi_cs2 involves different clock domain, read the
 352  * status back to ensure the transition is complete.
 353  */
 354 static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
 355 {
 356         u32 val;
 357
 358         val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 359         ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
 360
 361         do {
 362                 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 363         } while (val & DBI_CS2_EN_VAL);
 364 }
 365
 366 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 367 {
 368         struct dw_pcie *pci = ks_pcie->pci;
 369         struct pcie_port *pp = &pci->pp;
 370         u32 start = pp->mem->start, end = pp->mem->end;
 371         int i, tr_size;
 372         u32 val;
 373
 374         /* Disable BARs for inbound access */
 375         ks_dw_pcie_set_dbi_mode(ks_pcie);
 376         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
 377         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
 378         ks_dw_pcie_clear_dbi_mode(ks_pcie);
 379
 380         /* Set outbound translation size per window division */
 381         ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
 382
 383         tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
 384
 385         /* Using Direct 1:1 mapping of RC <-> PCI memory space */
 386         for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
 387                 ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
 388                 ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
 389                 start += tr_size;
 390         }
 391
 392         /* Enable OB translation */
 393         val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 394         ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
 395 }
 396
 397 /**
 398  * ks_pcie_cfg_setup() - Set up configuration space address for a device
 399  *
 400  * @ks_pcie: ptr to keystone_pcie structure
 401  * @bus: Bus number the device is residing on
 402  * @devfn: device, function number info
 403  *
 404  * Forms and returns the address of configuration space mapped in PCIESS
 405  * address space 0.  Also configures CFG_SETUP for remote configuration space
 406  * access.
 407  *
 408  * The address space has two regions to access configuration - local and remote.
 409  * We access local region for bus 0 (as RC is attached on bus 0) and remote
 410  * region for others with TYPE 1 access when bus > 1.  As for device on bus = 1,
 411  * we will do TYPE 0 access as it will be on our secondary bus (logical).
 412  * CFG_SETUP is needed only for remote configuration access.
 413  */
 414 static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
 415                                        unsigned int devfn)
 416 {
 417         u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
 418         struct dw_pcie *pci = ks_pcie->pci;
 419         struct pcie_port *pp = &pci->pp;
 420         u32 regval;
 421
 422         if (bus == 0)
 423                 return pci->dbi_base;
 424
 425         regval = (bus << 16) | (device << 8) | function;
 426
 427         /*
 428          * Since Bus#1 will be a virtual bus, we need to have TYPE0
 429          * access only.
 430          * TYPE 1
 431          */
 432         if (bus != 1)
 433                 regval |= BIT(24);
 434
 435         ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
 436         return pp->va_cfg0_base;
 437 }
 438
 439 int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 440                              unsigned int devfn, int where, int size, u32 *val)
 441 {
 442         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 443         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 444         u8 bus_num = bus->number;
 445         void __iomem *addr;
 446
 447         addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 448
 449         return dw_pcie_read(addr + where, size, val);
 450 }
 451
 452 int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 453                              unsigned int devfn, int where, int size, u32 val)
 454 {
 455         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 456         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 457         u8 bus_num = bus->number;
 458         void __iomem *addr;
 459
 460         addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 461
 462         return dw_pcie_write(addr + where, size, val);
 463 }
 464
 465 /**
 466  * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
 467  *
 468  * This sets BAR0 to enable inbound access for MSI_IRQ register
 469  */
 470 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
 471 {
 472         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 473         struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 474
 475         /* Configure and set up BAR0 */
 476         ks_dw_pcie_set_dbi_mode(ks_pcie);
 477
 478         /* Enable BAR0 */
 479         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
 480         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
 481
 482         ks_dw_pcie_clear_dbi_mode(ks_pcie);
 483
 484          /*
 485           * For BAR0, just setting bus address for inbound writes (MSI) should
 486           * be sufficient.  Use physical address to avoid any conflicts.
 487           */
 488         dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
 489 }
 490
 491 /**
 492  * ks_dw_pcie_link_up() - Check if link up
 493  */
 494 int ks_dw_pcie_link_up(struct dw_pcie *pci)
 495 {
 496         u32 val;
 497
 498         val = dw_pcie_readl_dbi(pci, DEBUG0);
 499         return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
 500 }
 501
 502 void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
 503 {
 504         u32 val;
 505
 506         /* Disable Link training */
 507         val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 508         val &= ~LTSSM_EN_VAL;
 509         ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
 510
 511         /* Initiate Link Training */
 512         val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 513         ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
 514 }
 515
 516 /**
 517  * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
 518  *
 519  * Ioremap the register resources, initialize legacy irq domain
 520  * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
 521  * PCI host controller.
 522  */
 523 int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
 524                                 struct device_node *msi_intc_np)
 525 {
 526         struct dw_pcie *pci = ks_pcie->pci;
 527         struct pcie_port *pp = &pci->pp;
 528         struct device *dev = pci->dev;
 529         struct platform_device *pdev = to_platform_device(dev);
 530         struct resource *res;
 531
 532         /* Index 0 is the config reg. space address */
 533         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 534         pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
 535         if (IS_ERR(pci->dbi_base))
 536                 return PTR_ERR(pci->dbi_base);
 537
 538         /*
 539          * We set these same and is used in pcie rd/wr_other_conf
 540          * functions
 541          */
 542         pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
 543         pp->va_cfg1_base = pp->va_cfg0_base;
 544
 545         /* Index 1 is the application reg. space address */
 546         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 547         ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
 548         if (IS_ERR(ks_pcie->va_app_base))
 549                 return PTR_ERR(ks_pcie->va_app_base);
 550
 551         ks_pcie->app = *res;
 552
 553         /* Create legacy IRQ domain */
 554         ks_pcie->legacy_irq_domain =
 555                         irq_domain_add_linear(ks_pcie->legacy_intc_np,
 556                                         PCI_NUM_INTX,
 557                                         &ks_dw_pcie_legacy_irq_domain_ops,
 558                                         NULL);
 559         if (!ks_pcie->legacy_irq_domain) {
 560                 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
 561                 return -EINVAL;
 562         }
 563
 564         return dw_pcie_host_init(pp);
 565 }