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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / pci / host / pci-aardvark.c
blobb04d37b3c5deea7b2aafdf34f636adb720a978bd
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
4 * 3700.
5 *
6 * Copyright (C) 2016 Marvell
7 *
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21
22 /* PCIe core registers */
23 #define PCIE_CORE_CMD_STATUS_REG 0x4
24 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
25 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
26 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
27 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
28 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
29 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
30 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
31 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
32 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
33 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
34 #define PCIE_CORE_LINK_TRAINING BIT(5)
35 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
36 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
41
42 /* PIO registers base address and register offsets */
43 #define PIO_BASE_ADDR 0x4000
44 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
45 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
46 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
47 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
48 #define PIO_COMPLETION_STATUS_SHIFT 7
49 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
50 #define PIO_COMPLETION_STATUS_OK 0
51 #define PIO_COMPLETION_STATUS_UR 1
52 #define PIO_COMPLETION_STATUS_CRS 2
53 #define PIO_COMPLETION_STATUS_CA 4
54 #define PIO_NON_POSTED_REQ BIT(0)
55 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
56 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
57 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
58 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
59 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
60 #define PIO_START (PIO_BASE_ADDR + 0x1c)
61 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
62 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
63
64 /* Aardvark Control registers */
65 #define CONTROL_BASE_ADDR 0x4800
66 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
67 #define PCIE_GEN_SEL_MSK 0x3
68 #define PCIE_GEN_SEL_SHIFT 0x0
69 #define SPEED_GEN_1 0
70 #define SPEED_GEN_2 1
71 #define SPEED_GEN_3 2
72 #define IS_RC_MSK 1
73 #define IS_RC_SHIFT 2
74 #define LANE_CNT_MSK 0x18
75 #define LANE_CNT_SHIFT 0x3
76 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
77 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
78 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
79 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
80 #define LINK_TRAINING_EN BIT(6)
81 #define LEGACY_INTA BIT(28)
82 #define LEGACY_INTB BIT(29)
83 #define LEGACY_INTC BIT(30)
84 #define LEGACY_INTD BIT(31)
85 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
86 #define HOT_RESET_GEN BIT(0)
87 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
88 #define PCIE_CORE_CTRL2_RESERVED 0x7
89 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
90 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
91 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
92 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
93 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
94 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
95 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
96 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
97 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
98 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
99 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
100 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
101 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
102 #define PCIE_ISR1_FLUSH BIT(5)
103 #define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
104 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
105 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
106 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
107 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
108 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
109
110 /* PCIe window configuration */
111 #define OB_WIN_BASE_ADDR 0x4c00
112 #define OB_WIN_BLOCK_SIZE 0x20
113 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
114 OB_WIN_BLOCK_SIZE * (win) + \
115 (offset))
116 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
117 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
118 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
119 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
120 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
121 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
122 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
123
124 /* PCIe window types */
125 #define OB_PCIE_MEM 0x0
126 #define OB_PCIE_IO 0x4
127
128 /* LMI registers base address and register offsets */
129 #define LMI_BASE_ADDR 0x6000
130 #define CFG_REG (LMI_BASE_ADDR + 0x0)
131 #define LTSSM_SHIFT 24
132 #define LTSSM_MASK 0x3f
133 #define LTSSM_L0 0x10
134 #define RC_BAR_CONFIG 0x300
135
136 /* PCIe core controller registers */
137 #define CTRL_CORE_BASE_ADDR 0x18000
138 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
139 #define CTRL_MODE_SHIFT 0x0
140 #define CTRL_MODE_MASK 0x1
141 #define PCIE_CORE_MODE_DIRECT 0x0
142 #define PCIE_CORE_MODE_COMMAND 0x1
143
144 /* PCIe Central Interrupts Registers */
145 #define CENTRAL_INT_BASE_ADDR 0x1b000
146 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
147 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
148 #define PCIE_IRQ_CMDQ_INT BIT(0)
149 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
150 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
151 #define PCIE_IRQ_DMA_INT BIT(4)
152 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
153 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
154 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
155 #define PCIE_IRQ_COMPQ_INT BIT(12)
156 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
157 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
158 #define PCIE_IRQ_CORE_INT BIT(16)
159 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
160 #define PCIE_IRQ_DPMU_INT BIT(18)
161 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
162 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
163 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
164 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
165 #define PCIE_IRQ_EP_STATUS BIT(23)
166 #define PCIE_IRQ_ALL_MASK 0xfff0fb
167 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
168
169 /* Transaction types */
170 #define PCIE_CONFIG_RD_TYPE0 0x8
171 #define PCIE_CONFIG_RD_TYPE1 0x9
172 #define PCIE_CONFIG_WR_TYPE0 0xa
173 #define PCIE_CONFIG_WR_TYPE1 0xb
174
175 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
176 #define PCIE_BDF(dev) (dev << 4)
177 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
178 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
179 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
180 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
181 #define PCIE_CONF_ADDR(bus, devfn, where) \
182 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
183 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
184
185 #define PIO_TIMEOUT_MS 1
186
187 #define LINK_WAIT_MAX_RETRIES 10
188 #define LINK_WAIT_USLEEP_MIN 90000
189 #define LINK_WAIT_USLEEP_MAX 100000
190
191 #define MSI_IRQ_NUM 32
192
193 struct advk_pcie {
194 struct platform_device *pdev;
195 void __iomem *base;
196 struct list_head resources;
197 struct irq_domain *irq_domain;
198 struct irq_chip irq_chip;
199 struct irq_domain *msi_domain;
200 struct irq_domain *msi_inner_domain;
201 struct irq_chip msi_bottom_irq_chip;
202 struct irq_chip msi_irq_chip;
203 struct msi_domain_info msi_domain_info;
204 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
205 struct mutex msi_used_lock;
206 u16 msi_msg;
207 int root_bus_nr;
208 };
209
210 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
211 {
212 writel(val, pcie->base + reg);
213 }
214
215 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
216 {
217 return readl(pcie->base + reg);
218 }
219
220 static int advk_pcie_link_up(struct advk_pcie *pcie)
221 {
222 u32 val, ltssm_state;
223
224 val = advk_readl(pcie, CFG_REG);
225 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
226 return ltssm_state >= LTSSM_L0;
227 }
228
229 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
230 {
231 struct device *dev = &pcie->pdev->dev;
232 int retries;
233
234 /* check if the link is up or not */
235 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
236 if (advk_pcie_link_up(pcie)) {
237 dev_info(dev, "link up\n");
238 return 0;
239 }
240
241 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
242 }
243
244 dev_err(dev, "link never came up\n");
245 return -ETIMEDOUT;
246 }
247
248 /*
249 * Set PCIe address window register which could be used for memory
250 * mapping.
251 */
252 static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
253 u32 win_num, u32 match_ms,
254 u32 match_ls, u32 mask_ms,
255 u32 mask_ls, u32 remap_ms,
256 u32 remap_ls, u32 action)
257 {
258 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
259 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
260 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
261 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
262 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
263 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
264 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
265 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
266 }
267
268 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
269 {
270 u32 reg;
271 int i;
272
273 /* Point PCIe unit MBUS decode windows to DRAM space */
274 for (i = 0; i < 8; i++)
275 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
276
277 /* Set to Direct mode */
278 reg = advk_readl(pcie, CTRL_CONFIG_REG);
279 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
280 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
281 advk_writel(pcie, reg, CTRL_CONFIG_REG);
282
283 /* Set PCI global control register to RC mode */
284 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
285 reg |= (IS_RC_MSK << IS_RC_SHIFT);
286 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
287
288 /* Set Advanced Error Capabilities and Control PF0 register */
289 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
290 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
291 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
292 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
293 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
294
295 /* Set PCIe Device Control and Status 1 PF0 register */
296 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
297 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
298 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
299 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
300 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
301
302 /* Program PCIe Control 2 to disable strict ordering */
303 reg = PCIE_CORE_CTRL2_RESERVED |
304 PCIE_CORE_CTRL2_TD_ENABLE;
305 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
306
307 /* Set GEN2 */
308 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
309 reg &= ~PCIE_GEN_SEL_MSK;
310 reg |= SPEED_GEN_2;
311 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
312
313 /* Set lane X1 */
314 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
315 reg &= ~LANE_CNT_MSK;
316 reg |= LANE_COUNT_1;
317 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
318
319 /* Enable link training */
320 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
321 reg |= LINK_TRAINING_EN;
322 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
323
324 /* Enable MSI */
325 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
326 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
327 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
328
329 /* Clear all interrupts */
330 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
331 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
332 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
333
334 /* Disable All ISR0/1 Sources */
335 reg = PCIE_ISR0_ALL_MASK;
336 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
337 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
338
339 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
340
341 /* Unmask all MSI's */
342 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
343
344 /* Enable summary interrupt for GIC SPI source */
345 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
346 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
347
348 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
349 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
350 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
351
352 /* Bypass the address window mapping for PIO */
353 reg = advk_readl(pcie, PIO_CTRL);
354 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
355 advk_writel(pcie, reg, PIO_CTRL);
356
357 /* Start link training */
358 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
359 reg |= PCIE_CORE_LINK_TRAINING;
360 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
361
362 advk_pcie_wait_for_link(pcie);
363
364 reg = PCIE_CORE_LINK_L0S_ENTRY |
365 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
366 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
367
368 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
369 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
370 PCIE_CORE_CMD_IO_ACCESS_EN |
371 PCIE_CORE_CMD_MEM_IO_REQ_EN;
372 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
373 }
374
375 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
376 {
377 struct device *dev = &pcie->pdev->dev;
378 u32 reg;
379 unsigned int status;
380 char *strcomp_status, *str_posted;
381
382 reg = advk_readl(pcie, PIO_STAT);
383 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
384 PIO_COMPLETION_STATUS_SHIFT;
385
386 if (!status)
387 return;
388
389 switch (status) {
390 case PIO_COMPLETION_STATUS_UR:
391 strcomp_status = "UR";
392 break;
393 case PIO_COMPLETION_STATUS_CRS:
394 strcomp_status = "CRS";
395 break;
396 case PIO_COMPLETION_STATUS_CA:
397 strcomp_status = "CA";
398 break;
399 default:
400 strcomp_status = "Unknown";
401 break;
402 }
403
404 if (reg & PIO_NON_POSTED_REQ)
405 str_posted = "Non-posted";
406 else
407 str_posted = "Posted";
408
409 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
410 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
411 }
412
413 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
414 {
415 struct device *dev = &pcie->pdev->dev;
416 unsigned long timeout;
417
418 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
419
420 while (time_before(jiffies, timeout)) {
421 u32 start, isr;
422
423 start = advk_readl(pcie, PIO_START);
424 isr = advk_readl(pcie, PIO_ISR);
425 if (!start && isr)
426 return 0;
427 }
428
429 dev_err(dev, "config read/write timed out\n");
430 return -ETIMEDOUT;
431 }
432
433 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
434 int where, int size, u32 *val)
435 {
436 struct advk_pcie *pcie = bus->sysdata;
437 u32 reg;
438 int ret;
439
440 if (PCI_SLOT(devfn) != 0) {
441 *val = 0xffffffff;
442 return PCIBIOS_DEVICE_NOT_FOUND;
443 }
444
445 /* Start PIO */
446 advk_writel(pcie, 0, PIO_START);
447 advk_writel(pcie, 1, PIO_ISR);
448
449 /* Program the control register */
450 reg = advk_readl(pcie, PIO_CTRL);
451 reg &= ~PIO_CTRL_TYPE_MASK;
452 if (bus->number == pcie->root_bus_nr)
453 reg |= PCIE_CONFIG_RD_TYPE0;
454 else
455 reg |= PCIE_CONFIG_RD_TYPE1;
456 advk_writel(pcie, reg, PIO_CTRL);
457
458 /* Program the address registers */
459 reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
460 advk_writel(pcie, reg, PIO_ADDR_LS);
461 advk_writel(pcie, 0, PIO_ADDR_MS);
462
463 /* Program the data strobe */
464 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
465
466 /* Start the transfer */
467 advk_writel(pcie, 1, PIO_START);
468
469 ret = advk_pcie_wait_pio(pcie);
470 if (ret < 0)
471 return PCIBIOS_SET_FAILED;
472
473 advk_pcie_check_pio_status(pcie);
474
475 /* Get the read result */
476 *val = advk_readl(pcie, PIO_RD_DATA);
477 if (size == 1)
478 *val = (*val >> (8 * (where & 3))) & 0xff;
479 else if (size == 2)
480 *val = (*val >> (8 * (where & 3))) & 0xffff;
481
482 return PCIBIOS_SUCCESSFUL;
483 }
484
485 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
486 int where, int size, u32 val)
487 {
488 struct advk_pcie *pcie = bus->sysdata;
489 u32 reg;
490 u32 data_strobe = 0x0;
491 int offset;
492 int ret;
493
494 if (PCI_SLOT(devfn) != 0)
495 return PCIBIOS_DEVICE_NOT_FOUND;
496
497 if (where % size)
498 return PCIBIOS_SET_FAILED;
499
500 /* Start PIO */
501 advk_writel(pcie, 0, PIO_START);
502 advk_writel(pcie, 1, PIO_ISR);
503
504 /* Program the control register */
505 reg = advk_readl(pcie, PIO_CTRL);
506 reg &= ~PIO_CTRL_TYPE_MASK;
507 if (bus->number == pcie->root_bus_nr)
508 reg |= PCIE_CONFIG_WR_TYPE0;
509 else
510 reg |= PCIE_CONFIG_WR_TYPE1;
511 advk_writel(pcie, reg, PIO_CTRL);
512
513 /* Program the address registers */
514 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
515 advk_writel(pcie, reg, PIO_ADDR_LS);
516 advk_writel(pcie, 0, PIO_ADDR_MS);
517
518 /* Calculate the write strobe */
519 offset = where & 0x3;
520 reg = val << (8 * offset);
521 data_strobe = GENMASK(size - 1, 0) << offset;
522
523 /* Program the data register */
524 advk_writel(pcie, reg, PIO_WR_DATA);
525
526 /* Program the data strobe */
527 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
528
529 /* Start the transfer */
530 advk_writel(pcie, 1, PIO_START);
531
532 ret = advk_pcie_wait_pio(pcie);
533 if (ret < 0)
534 return PCIBIOS_SET_FAILED;
535
536 advk_pcie_check_pio_status(pcie);
537
538 return PCIBIOS_SUCCESSFUL;
539 }
540
541 static struct pci_ops advk_pcie_ops = {
542 .read = advk_pcie_rd_conf,
543 .write = advk_pcie_wr_conf,
544 };
545
546 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
547 struct msi_msg *msg)
548 {
549 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
550 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
551
552 msg->address_lo = lower_32_bits(msi_msg);
553 msg->address_hi = upper_32_bits(msi_msg);
554 msg->data = data->irq;
555 }
556
557 static int advk_msi_set_affinity(struct irq_data *irq_data,
558 const struct cpumask *mask, bool force)
559 {
560 return -EINVAL;
561 }
562
563 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
564 unsigned int virq,
565 unsigned int nr_irqs, void *args)
566 {
567 struct advk_pcie *pcie = domain->host_data;
568 int hwirq, i;
569
570 mutex_lock(&pcie->msi_used_lock);
571 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
572 0, nr_irqs, 0);
573 if (hwirq >= MSI_IRQ_NUM) {
574 mutex_unlock(&pcie->msi_used_lock);
575 return -ENOSPC;
576 }
577
578 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
579 mutex_unlock(&pcie->msi_used_lock);
580
581 for (i = 0; i < nr_irqs; i++)
582 irq_domain_set_info(domain, virq + i, hwirq + i,
583 &pcie->msi_bottom_irq_chip,
584 domain->host_data, handle_simple_irq,
585 NULL, NULL);
586
587 return hwirq;
588 }
589
590 static void advk_msi_irq_domain_free(struct irq_domain *domain,
591 unsigned int virq, unsigned int nr_irqs)
592 {
593 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
594 struct advk_pcie *pcie = domain->host_data;
595
596 mutex_lock(&pcie->msi_used_lock);
597 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
598 mutex_unlock(&pcie->msi_used_lock);
599 }
600
601 static const struct irq_domain_ops advk_msi_domain_ops = {
602 .alloc = advk_msi_irq_domain_alloc,
603 .free = advk_msi_irq_domain_free,
604 };
605
606 static void advk_pcie_irq_mask(struct irq_data *d)
607 {
608 struct advk_pcie *pcie = d->domain->host_data;
609 irq_hw_number_t hwirq = irqd_to_hwirq(d);
610 u32 mask;
611
612 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
613 mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
614 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
615 }
616
617 static void advk_pcie_irq_unmask(struct irq_data *d)
618 {
619 struct advk_pcie *pcie = d->domain->host_data;
620 irq_hw_number_t hwirq = irqd_to_hwirq(d);
621 u32 mask;
622
623 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
624 mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
625 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
626 }
627
628 static int advk_pcie_irq_map(struct irq_domain *h,
629 unsigned int virq, irq_hw_number_t hwirq)
630 {
631 struct advk_pcie *pcie = h->host_data;
632
633 advk_pcie_irq_mask(irq_get_irq_data(virq));
634 irq_set_status_flags(virq, IRQ_LEVEL);
635 irq_set_chip_and_handler(virq, &pcie->irq_chip,
636 handle_level_irq);
637 irq_set_chip_data(virq, pcie);
638
639 return 0;
640 }
641
642 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
643 .map = advk_pcie_irq_map,
644 .xlate = irq_domain_xlate_onecell,
645 };
646
647 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
648 {
649 struct device *dev = &pcie->pdev->dev;
650 struct device_node *node = dev->of_node;
651 struct irq_chip *bottom_ic, *msi_ic;
652 struct msi_domain_info *msi_di;
653 phys_addr_t msi_msg_phys;
654
655 mutex_init(&pcie->msi_used_lock);
656
657 bottom_ic = &pcie->msi_bottom_irq_chip;
658
659 bottom_ic->name = "MSI";
660 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
661 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
662
663 msi_ic = &pcie->msi_irq_chip;
664 msi_ic->name = "advk-MSI";
665
666 msi_di = &pcie->msi_domain_info;
667 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
668 MSI_FLAG_MULTI_PCI_MSI;
669 msi_di->chip = msi_ic;
670
671 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
672
673 advk_writel(pcie, lower_32_bits(msi_msg_phys),
674 PCIE_MSI_ADDR_LOW_REG);
675 advk_writel(pcie, upper_32_bits(msi_msg_phys),
676 PCIE_MSI_ADDR_HIGH_REG);
677
678 pcie->msi_inner_domain =
679 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
680 &advk_msi_domain_ops, pcie);
681 if (!pcie->msi_inner_domain)
682 return -ENOMEM;
683
684 pcie->msi_domain =
685 pci_msi_create_irq_domain(of_node_to_fwnode(node),
686 msi_di, pcie->msi_inner_domain);
687 if (!pcie->msi_domain) {
688 irq_domain_remove(pcie->msi_inner_domain);
689 return -ENOMEM;
690 }
691
692 return 0;
693 }
694
695 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
696 {
697 irq_domain_remove(pcie->msi_domain);
698 irq_domain_remove(pcie->msi_inner_domain);
699 }
700
701 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
702 {
703 struct device *dev = &pcie->pdev->dev;
704 struct device_node *node = dev->of_node;
705 struct device_node *pcie_intc_node;
706 struct irq_chip *irq_chip;
707
708 pcie_intc_node = of_get_next_child(node, NULL);
709 if (!pcie_intc_node) {
710 dev_err(dev, "No PCIe Intc node found\n");
711 return -ENODEV;
712 }
713
714 irq_chip = &pcie->irq_chip;
715
716 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
717 dev_name(dev));
718 if (!irq_chip->name) {
719 of_node_put(pcie_intc_node);
720 return -ENOMEM;
721 }
722
723 irq_chip->irq_mask = advk_pcie_irq_mask;
724 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
725 irq_chip->irq_unmask = advk_pcie_irq_unmask;
726
727 pcie->irq_domain =
728 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
729 &advk_pcie_irq_domain_ops, pcie);
730 if (!pcie->irq_domain) {
731 dev_err(dev, "Failed to get a INTx IRQ domain\n");
732 of_node_put(pcie_intc_node);
733 return -ENOMEM;
734 }
735
736 return 0;
737 }
738
739 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
740 {
741 irq_domain_remove(pcie->irq_domain);
742 }
743
744 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
745 {
746 u32 msi_val, msi_mask, msi_status, msi_idx;
747 u16 msi_data;
748
749 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
750 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
751 msi_status = msi_val & ~msi_mask;
752
753 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
754 if (!(BIT(msi_idx) & msi_status))
755 continue;
756
757 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
758 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
759 generic_handle_irq(msi_data);
760 }
761
762 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
763 PCIE_ISR0_REG);
764 }
765
766 static void advk_pcie_handle_int(struct advk_pcie *pcie)
767 {
768 u32 val, mask, status;
769 int i, virq;
770
771 val = advk_readl(pcie, PCIE_ISR0_REG);
772 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
773 status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
774
775 if (!status) {
776 advk_writel(pcie, val, PCIE_ISR0_REG);
777 return;
778 }
779
780 /* Process MSI interrupts */
781 if (status & PCIE_ISR0_MSI_INT_PENDING)
782 advk_pcie_handle_msi(pcie);
783
784 /* Process legacy interrupts */
785 for (i = 0; i < PCI_NUM_INTX; i++) {
786 if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
787 continue;
788
789 advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
790 PCIE_ISR0_REG);
791
792 virq = irq_find_mapping(pcie->irq_domain, i);
793 generic_handle_irq(virq);
794 }
795 }
796
797 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
798 {
799 struct advk_pcie *pcie = arg;
800 u32 status;
801
802 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
803 if (!(status & PCIE_IRQ_CORE_INT))
804 return IRQ_NONE;
805
806 advk_pcie_handle_int(pcie);
807
808 /* Clear interrupt */
809 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
810
811 return IRQ_HANDLED;
812 }
813
814 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
815 {
816 int err, res_valid = 0;
817 struct device *dev = &pcie->pdev->dev;
818 struct device_node *np = dev->of_node;
819 struct resource_entry *win, *tmp;
820 resource_size_t iobase;
821
822 INIT_LIST_HEAD(&pcie->resources);
823
824 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
825 &iobase);
826 if (err)
827 return err;
828
829 err = devm_request_pci_bus_resources(dev, &pcie->resources);
830 if (err)
831 goto out_release_res;
832
833 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
834 struct resource *res = win->res;
835
836 switch (resource_type(res)) {
837 case IORESOURCE_IO:
838 advk_pcie_set_ob_win(pcie, 1,
839 upper_32_bits(res->start),
840 lower_32_bits(res->start),
841 0, 0xF8000000, 0,
842 lower_32_bits(res->start),
843 OB_PCIE_IO);
844 err = pci_remap_iospace(res, iobase);
845 if (err) {
846 dev_warn(dev, "error %d: failed to map resource %pR\n",
847 err, res);
848 resource_list_destroy_entry(win);
849 }
850 break;
851 case IORESOURCE_MEM:
852 advk_pcie_set_ob_win(pcie, 0,
853 upper_32_bits(res->start),
854 lower_32_bits(res->start),
855 0x0, 0xF8000000, 0,
856 lower_32_bits(res->start),
857 (2 << 20) | OB_PCIE_MEM);
858 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
859 break;
860 case IORESOURCE_BUS:
861 pcie->root_bus_nr = res->start;
862 break;
863 }
864 }
865
866 if (!res_valid) {
867 dev_err(dev, "non-prefetchable memory resource required\n");
868 err = -EINVAL;
869 goto out_release_res;
870 }
871
872 return 0;
873
874 out_release_res:
875 pci_free_resource_list(&pcie->resources);
876 return err;
877 }
878
879 static int advk_pcie_probe(struct platform_device *pdev)
880 {
881 struct device *dev = &pdev->dev;
882 struct advk_pcie *pcie;
883 struct resource *res;
884 struct pci_bus *bus, *child;
885 struct pci_host_bridge *bridge;
886 int ret, irq;
887
888 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
889 if (!bridge)
890 return -ENOMEM;
891
892 pcie = pci_host_bridge_priv(bridge);
893 pcie->pdev = pdev;
894
895 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
896 pcie->base = devm_ioremap_resource(dev, res);
897 if (IS_ERR(pcie->base))
898 return PTR_ERR(pcie->base);
899
900 irq = platform_get_irq(pdev, 0);
901 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
902 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
903 pcie);
904 if (ret) {
905 dev_err(dev, "Failed to register interrupt\n");
906 return ret;
907 }
908
909 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
910 if (ret) {
911 dev_err(dev, "Failed to parse resources\n");
912 return ret;
913 }
914
915 advk_pcie_setup_hw(pcie);
916
917 ret = advk_pcie_init_irq_domain(pcie);
918 if (ret) {
919 dev_err(dev, "Failed to initialize irq\n");
920 return ret;
921 }
922
923 ret = advk_pcie_init_msi_irq_domain(pcie);
924 if (ret) {
925 dev_err(dev, "Failed to initialize irq\n");
926 advk_pcie_remove_irq_domain(pcie);
927 return ret;
928 }
929
930 list_splice_init(&pcie->resources, &bridge->windows);
931 bridge->dev.parent = dev;
932 bridge->sysdata = pcie;
933 bridge->busnr = 0;
934 bridge->ops = &advk_pcie_ops;
935 bridge->map_irq = of_irq_parse_and_map_pci;
936 bridge->swizzle_irq = pci_common_swizzle;
937
938 ret = pci_scan_root_bus_bridge(bridge);
939 if (ret < 0) {
940 advk_pcie_remove_msi_irq_domain(pcie);
941 advk_pcie_remove_irq_domain(pcie);
942 return ret;
943 }
944
945 bus = bridge->bus;
946
947 pci_bus_assign_resources(bus);
948
949 list_for_each_entry(child, &bus->children, node)
950 pcie_bus_configure_settings(child);
951
952 pci_bus_add_devices(bus);
953 return 0;
954 }
955
956 static const struct of_device_id advk_pcie_of_match_table[] = {
957 { .compatible = "marvell,armada-3700-pcie", },
958 {},
959 };
960
961 static struct platform_driver advk_pcie_driver = {
962 .driver = {
963 .name = "advk-pcie",
964 .of_match_table = advk_pcie_of_match_table,
965 /* Driver unloading/unbinding currently not supported */
966 .suppress_bind_attrs = true,
967 },
968 .probe = advk_pcie_probe,
969 };
970 builtin_platform_driver(advk_pcie_driver);
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