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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / pci / host / pci-mvebu.c
blob5d4dccfc9d8133cf8cfc66cc9f3bb8536863e780
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/init.h>
14 #include <linux/mbus.h>
15 #include <linux/msi.h>
16 #include <linux/slab.h>
17 #include <linux/platform_device.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23
24 /*
25 * PCIe unit register offsets.
26 */
27 #define PCIE_DEV_ID_OFF 0x0000
28 #define PCIE_CMD_OFF 0x0004
29 #define PCIE_DEV_REV_OFF 0x0008
30 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
31 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
32 #define PCIE_CAP_PCIEXP 0x0060
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_RC_RTSTA 0x1a14
61 #define PCIE_DEBUG_CTRL 0x1a60
62 #define PCIE_DEBUG_SOFT_RESET BIT(20)
63
64 enum {
65 PCISWCAP = PCI_BRIDGE_CONTROL + 2,
66 PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID,
67 PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP,
68 PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL,
69 PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP,
70 PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL,
71 PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP,
72 PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL,
73 PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL,
74 PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA,
75 PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2,
76 PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2,
77 PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2,
78 PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2,
79 PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2,
80 PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2,
81 };
82
83 /* PCI configuration space of a PCI-to-PCI bridge */
84 struct mvebu_sw_pci_bridge {
85 u16 vendor;
86 u16 device;
87 u16 command;
88 u16 status;
89 u16 class;
90 u8 interface;
91 u8 revision;
92 u8 bist;
93 u8 header_type;
94 u8 latency_timer;
95 u8 cache_line_size;
96 u32 bar[2];
97 u8 primary_bus;
98 u8 secondary_bus;
99 u8 subordinate_bus;
100 u8 secondary_latency_timer;
101 u8 iobase;
102 u8 iolimit;
103 u16 secondary_status;
104 u16 membase;
105 u16 memlimit;
106 u16 iobaseupper;
107 u16 iolimitupper;
108 u32 romaddr;
109 u8 intline;
110 u8 intpin;
111 u16 bridgectrl;
112
113 /* PCI express capability */
114 u32 pcie_sltcap;
115 u16 pcie_devctl;
116 u16 pcie_rtctl;
117 };
118
119 struct mvebu_pcie_port;
120
121 /* Structure representing all PCIe interfaces */
122 struct mvebu_pcie {
123 struct platform_device *pdev;
124 struct mvebu_pcie_port *ports;
125 struct msi_controller *msi;
126 struct resource io;
127 struct resource realio;
128 struct resource mem;
129 struct resource busn;
130 int nports;
131 };
132
133 struct mvebu_pcie_window {
134 phys_addr_t base;
135 phys_addr_t remap;
136 size_t size;
137 };
138
139 /* Structure representing one PCIe interface */
140 struct mvebu_pcie_port {
141 char *name;
142 void __iomem *base;
143 u32 port;
144 u32 lane;
145 int devfn;
146 unsigned int mem_target;
147 unsigned int mem_attr;
148 unsigned int io_target;
149 unsigned int io_attr;
150 struct clk *clk;
151 struct gpio_desc *reset_gpio;
152 char *reset_name;
153 struct mvebu_sw_pci_bridge bridge;
154 struct device_node *dn;
155 struct mvebu_pcie *pcie;
156 struct mvebu_pcie_window memwin;
157 struct mvebu_pcie_window iowin;
158 u32 saved_pcie_stat;
159 };
160
161 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
162 {
163 writel(val, port->base + reg);
164 }
165
166 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
167 {
168 return readl(port->base + reg);
169 }
170
171 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
172 {
173 return port->io_target != -1 && port->io_attr != -1;
174 }
175
176 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
177 {
178 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
179 }
180
181 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
182 {
183 u32 stat;
184
185 stat = mvebu_readl(port, PCIE_STAT_OFF);
186 stat &= ~PCIE_STAT_BUS;
187 stat |= nr << 8;
188 mvebu_writel(port, stat, PCIE_STAT_OFF);
189 }
190
191 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
192 {
193 u32 stat;
194
195 stat = mvebu_readl(port, PCIE_STAT_OFF);
196 stat &= ~PCIE_STAT_DEV;
197 stat |= nr << 16;
198 mvebu_writel(port, stat, PCIE_STAT_OFF);
199 }
200
201 /*
202 * Setup PCIE BARs and Address Decode Wins:
203 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
204 * WIN[0-3] -> DRAM bank[0-3]
205 */
206 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
207 {
208 const struct mbus_dram_target_info *dram;
209 u32 size;
210 int i;
211
212 dram = mv_mbus_dram_info();
213
214 /* First, disable and clear BARs and windows. */
215 for (i = 1; i < 3; i++) {
216 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
217 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
218 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
219 }
220
221 for (i = 0; i < 5; i++) {
222 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
223 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
224 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
225 }
226
227 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
228 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
229 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
230
231 /* Setup windows for DDR banks. Count total DDR size on the fly. */
232 size = 0;
233 for (i = 0; i < dram->num_cs; i++) {
234 const struct mbus_dram_window *cs = dram->cs + i;
235
236 mvebu_writel(port, cs->base & 0xffff0000,
237 PCIE_WIN04_BASE_OFF(i));
238 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
239 mvebu_writel(port,
240 ((cs->size - 1) & 0xffff0000) |
241 (cs->mbus_attr << 8) |
242 (dram->mbus_dram_target_id << 4) | 1,
243 PCIE_WIN04_CTRL_OFF(i));
244
245 size += cs->size;
246 }
247
248 /* Round up 'size' to the nearest power of two. */
249 if ((size & (size - 1)) != 0)
250 size = 1 << fls(size);
251
252 /* Setup BAR[1] to all DRAM banks. */
253 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
254 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
255 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
256 PCIE_BAR_CTRL_OFF(1));
257 }
258
259 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
260 {
261 u32 cmd, mask;
262
263 /* Point PCIe unit MBUS decode windows to DRAM space. */
264 mvebu_pcie_setup_wins(port);
265
266 /* Master + slave enable. */
267 cmd = mvebu_readl(port, PCIE_CMD_OFF);
268 cmd |= PCI_COMMAND_IO;
269 cmd |= PCI_COMMAND_MEMORY;
270 cmd |= PCI_COMMAND_MASTER;
271 mvebu_writel(port, cmd, PCIE_CMD_OFF);
272
273 /* Enable interrupt lines A-D. */
274 mask = mvebu_readl(port, PCIE_MASK_OFF);
275 mask |= PCIE_MASK_ENABLE_INTS;
276 mvebu_writel(port, mask, PCIE_MASK_OFF);
277 }
278
279 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
280 struct pci_bus *bus,
281 u32 devfn, int where, int size, u32 *val)
282 {
283 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
284
285 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
286 PCIE_CONF_ADDR_OFF);
287
288 switch (size) {
289 case 1:
290 *val = readb_relaxed(conf_data + (where & 3));
291 break;
292 case 2:
293 *val = readw_relaxed(conf_data + (where & 2));
294 break;
295 case 4:
296 *val = readl_relaxed(conf_data);
297 break;
298 }
299
300 return PCIBIOS_SUCCESSFUL;
301 }
302
303 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
304 struct pci_bus *bus,
305 u32 devfn, int where, int size, u32 val)
306 {
307 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
308
309 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
310 PCIE_CONF_ADDR_OFF);
311
312 switch (size) {
313 case 1:
314 writeb(val, conf_data + (where & 3));
315 break;
316 case 2:
317 writew(val, conf_data + (where & 2));
318 break;
319 case 4:
320 writel(val, conf_data);
321 break;
322 default:
323 return PCIBIOS_BAD_REGISTER_NUMBER;
324 }
325
326 return PCIBIOS_SUCCESSFUL;
327 }
328
329 /*
330 * Remove windows, starting from the largest ones to the smallest
331 * ones.
332 */
333 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
334 phys_addr_t base, size_t size)
335 {
336 while (size) {
337 size_t sz = 1 << (fls(size) - 1);
338
339 mvebu_mbus_del_window(base, sz);
340 base += sz;
341 size -= sz;
342 }
343 }
344
345 /*
346 * MBus windows can only have a power of two size, but PCI BARs do not
347 * have this constraint. Therefore, we have to split the PCI BAR into
348 * areas each having a power of two size. We start from the largest
349 * one (i.e highest order bit set in the size).
350 */
351 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
352 unsigned int target, unsigned int attribute,
353 phys_addr_t base, size_t size,
354 phys_addr_t remap)
355 {
356 size_t size_mapped = 0;
357
358 while (size) {
359 size_t sz = 1 << (fls(size) - 1);
360 int ret;
361
362 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
363 sz, remap);
364 if (ret) {
365 phys_addr_t end = base + sz - 1;
366
367 dev_err(&port->pcie->pdev->dev,
368 "Could not create MBus window at [mem %pa-%pa]: %d\n",
369 &base, &end, ret);
370 mvebu_pcie_del_windows(port, base - size_mapped,
371 size_mapped);
372 return;
373 }
374
375 size -= sz;
376 size_mapped += sz;
377 base += sz;
378 if (remap != MVEBU_MBUS_NO_REMAP)
379 remap += sz;
380 }
381 }
382
383 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
384 unsigned int target, unsigned int attribute,
385 const struct mvebu_pcie_window *desired,
386 struct mvebu_pcie_window *cur)
387 {
388 if (desired->base == cur->base && desired->remap == cur->remap &&
389 desired->size == cur->size)
390 return;
391
392 if (cur->size != 0) {
393 mvebu_pcie_del_windows(port, cur->base, cur->size);
394 cur->size = 0;
395 cur->base = 0;
396
397 /*
398 * If something tries to change the window while it is enabled
399 * the change will not be done atomically. That would be
400 * difficult to do in the general case.
401 */
402 }
403
404 if (desired->size == 0)
405 return;
406
407 mvebu_pcie_add_windows(port, target, attribute, desired->base,
408 desired->size, desired->remap);
409 *cur = *desired;
410 }
411
412 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
413 {
414 struct mvebu_pcie_window desired = {};
415
416 /* Are the new iobase/iolimit values invalid? */
417 if (port->bridge.iolimit < port->bridge.iobase ||
418 port->bridge.iolimitupper < port->bridge.iobaseupper ||
419 !(port->bridge.command & PCI_COMMAND_IO)) {
420 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
421 &desired, &port->iowin);
422 return;
423 }
424
425 if (!mvebu_has_ioport(port)) {
426 dev_WARN(&port->pcie->pdev->dev,
427 "Attempt to set IO when IO is disabled\n");
428 return;
429 }
430
431 /*
432 * We read the PCI-to-PCI bridge emulated registers, and
433 * calculate the base address and size of the address decoding
434 * window to setup, according to the PCI-to-PCI bridge
435 * specifications. iobase is the bus address, port->iowin_base
436 * is the CPU address.
437 */
438 desired.remap = ((port->bridge.iobase & 0xF0) << 8) |
439 (port->bridge.iobaseupper << 16);
440 desired.base = port->pcie->io.start + desired.remap;
441 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
442 (port->bridge.iolimitupper << 16)) -
443 desired.remap) +
444 1;
445
446 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
447 &port->iowin);
448 }
449
450 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
451 {
452 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
453
454 /* Are the new membase/memlimit values invalid? */
455 if (port->bridge.memlimit < port->bridge.membase ||
456 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
457 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
458 &desired, &port->memwin);
459 return;
460 }
461
462 /*
463 * We read the PCI-to-PCI bridge emulated registers, and
464 * calculate the base address and size of the address decoding
465 * window to setup, according to the PCI-to-PCI bridge
466 * specifications.
467 */
468 desired.base = ((port->bridge.membase & 0xFFF0) << 16);
469 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
470 desired.base + 1;
471
472 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
473 &port->memwin);
474 }
475
476 /*
477 * Initialize the configuration space of the PCI-to-PCI bridge
478 * associated with the given PCIe interface.
479 */
480 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
481 {
482 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
483
484 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
485
486 bridge->class = PCI_CLASS_BRIDGE_PCI;
487 bridge->vendor = PCI_VENDOR_ID_MARVELL;
488 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
489 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
490 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
491 bridge->cache_line_size = 0x10;
492
493 /* We support 32 bits I/O addressing */
494 bridge->iobase = PCI_IO_RANGE_TYPE_32;
495 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
496
497 /* Add capabilities */
498 bridge->status = PCI_STATUS_CAP_LIST;
499 }
500
501 /*
502 * Read the configuration space of the PCI-to-PCI bridge associated to
503 * the given PCIe interface.
504 */
505 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
506 unsigned int where, int size, u32 *value)
507 {
508 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
509
510 switch (where & ~3) {
511 case PCI_VENDOR_ID:
512 *value = bridge->device << 16 | bridge->vendor;
513 break;
514
515 case PCI_COMMAND:
516 *value = bridge->command | bridge->status << 16;
517 break;
518
519 case PCI_CLASS_REVISION:
520 *value = bridge->class << 16 | bridge->interface << 8 |
521 bridge->revision;
522 break;
523
524 case PCI_CACHE_LINE_SIZE:
525 *value = bridge->bist << 24 | bridge->header_type << 16 |
526 bridge->latency_timer << 8 | bridge->cache_line_size;
527 break;
528
529 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
530 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
531 break;
532
533 case PCI_PRIMARY_BUS:
534 *value = (bridge->secondary_latency_timer << 24 |
535 bridge->subordinate_bus << 16 |
536 bridge->secondary_bus << 8 |
537 bridge->primary_bus);
538 break;
539
540 case PCI_IO_BASE:
541 if (!mvebu_has_ioport(port))
542 *value = bridge->secondary_status << 16;
543 else
544 *value = (bridge->secondary_status << 16 |
545 bridge->iolimit << 8 |
546 bridge->iobase);
547 break;
548
549 case PCI_MEMORY_BASE:
550 *value = (bridge->memlimit << 16 | bridge->membase);
551 break;
552
553 case PCI_PREF_MEMORY_BASE:
554 *value = 0;
555 break;
556
557 case PCI_IO_BASE_UPPER16:
558 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
559 break;
560
561 case PCI_CAPABILITY_LIST:
562 *value = PCISWCAP;
563 break;
564
565 case PCI_ROM_ADDRESS1:
566 *value = 0;
567 break;
568
569 case PCI_INTERRUPT_LINE:
570 /* LINE PIN MIN_GNT MAX_LAT */
571 *value = 0;
572 break;
573
574 case PCISWCAP_EXP_LIST_ID:
575 /* Set PCIe v2, root port, slot support */
576 *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
577 PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
578 break;
579
580 case PCISWCAP_EXP_DEVCAP:
581 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
582 break;
583
584 case PCISWCAP_EXP_DEVCTL:
585 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
586 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
587 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
588 *value |= bridge->pcie_devctl;
589 break;
590
591 case PCISWCAP_EXP_LNKCAP:
592 /*
593 * PCIe requires the clock power management capability to be
594 * hard-wired to zero for downstream ports
595 */
596 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
597 ~PCI_EXP_LNKCAP_CLKPM;
598 break;
599
600 case PCISWCAP_EXP_LNKCTL:
601 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
602 break;
603
604 case PCISWCAP_EXP_SLTCAP:
605 *value = bridge->pcie_sltcap;
606 break;
607
608 case PCISWCAP_EXP_SLTCTL:
609 *value = PCI_EXP_SLTSTA_PDS << 16;
610 break;
611
612 case PCISWCAP_EXP_RTCTL:
613 *value = bridge->pcie_rtctl;
614 break;
615
616 case PCISWCAP_EXP_RTSTA:
617 *value = mvebu_readl(port, PCIE_RC_RTSTA);
618 break;
619
620 /* PCIe requires the v2 fields to be hard-wired to zero */
621 case PCISWCAP_EXP_DEVCAP2:
622 case PCISWCAP_EXP_DEVCTL2:
623 case PCISWCAP_EXP_LNKCAP2:
624 case PCISWCAP_EXP_LNKCTL2:
625 case PCISWCAP_EXP_SLTCAP2:
626 case PCISWCAP_EXP_SLTCTL2:
627 default:
628 /*
629 * PCI defines configuration read accesses to reserved or
630 * unimplemented registers to read as zero and complete
631 * normally.
632 */
633 *value = 0;
634 return PCIBIOS_SUCCESSFUL;
635 }
636
637 if (size == 2)
638 *value = (*value >> (8 * (where & 3))) & 0xffff;
639 else if (size == 1)
640 *value = (*value >> (8 * (where & 3))) & 0xff;
641
642 return PCIBIOS_SUCCESSFUL;
643 }
644
645 /* Write to the PCI-to-PCI bridge configuration space */
646 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
647 unsigned int where, int size, u32 value)
648 {
649 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
650 u32 mask, reg;
651 int err;
652
653 if (size == 4)
654 mask = 0x0;
655 else if (size == 2)
656 mask = ~(0xffff << ((where & 3) * 8));
657 else if (size == 1)
658 mask = ~(0xff << ((where & 3) * 8));
659 else
660 return PCIBIOS_BAD_REGISTER_NUMBER;
661
662 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
663 if (err)
664 return err;
665
666 value = (reg & mask) | value << ((where & 3) * 8);
667
668 switch (where & ~3) {
669 case PCI_COMMAND:
670 {
671 u32 old = bridge->command;
672
673 if (!mvebu_has_ioport(port))
674 value &= ~PCI_COMMAND_IO;
675
676 bridge->command = value & 0xffff;
677 if ((old ^ bridge->command) & PCI_COMMAND_IO)
678 mvebu_pcie_handle_iobase_change(port);
679 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
680 mvebu_pcie_handle_membase_change(port);
681 break;
682 }
683
684 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
685 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
686 break;
687
688 case PCI_IO_BASE:
689 /*
690 * We also keep bit 1 set, it is a read-only bit that
691 * indicates we support 32 bits addressing for the
692 * I/O
693 */
694 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
695 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
696 mvebu_pcie_handle_iobase_change(port);
697 break;
698
699 case PCI_MEMORY_BASE:
700 bridge->membase = value & 0xffff;
701 bridge->memlimit = value >> 16;
702 mvebu_pcie_handle_membase_change(port);
703 break;
704
705 case PCI_IO_BASE_UPPER16:
706 bridge->iobaseupper = value & 0xffff;
707 bridge->iolimitupper = value >> 16;
708 mvebu_pcie_handle_iobase_change(port);
709 break;
710
711 case PCI_PRIMARY_BUS:
712 bridge->primary_bus = value & 0xff;
713 bridge->secondary_bus = (value >> 8) & 0xff;
714 bridge->subordinate_bus = (value >> 16) & 0xff;
715 bridge->secondary_latency_timer = (value >> 24) & 0xff;
716 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
717 break;
718
719 case PCISWCAP_EXP_DEVCTL:
720 /*
721 * Armada370 data says these bits must always
722 * be zero when in root complex mode.
723 */
724 value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
725 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
726
727 /*
728 * If the mask is 0xffff0000, then we only want to write
729 * the device control register, rather than clearing the
730 * RW1C bits in the device status register. Mask out the
731 * status register bits.
732 */
733 if (mask == 0xffff0000)
734 value &= 0xffff;
735
736 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
737 break;
738
739 case PCISWCAP_EXP_LNKCTL:
740 /*
741 * If we don't support CLKREQ, we must ensure that the
742 * CLKREQ enable bit always reads zero. Since we haven't
743 * had this capability, and it's dependent on board wiring,
744 * disable it for the time being.
745 */
746 value &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
747
748 /*
749 * If the mask is 0xffff0000, then we only want to write
750 * the link control register, rather than clearing the
751 * RW1C bits in the link status register. Mask out the
752 * RW1C status register bits.
753 */
754 if (mask == 0xffff0000)
755 value &= ~((PCI_EXP_LNKSTA_LABS |
756 PCI_EXP_LNKSTA_LBMS) << 16);
757
758 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
759 break;
760
761 case PCISWCAP_EXP_RTSTA:
762 mvebu_writel(port, value, PCIE_RC_RTSTA);
763 break;
764
765 default:
766 break;
767 }
768
769 return PCIBIOS_SUCCESSFUL;
770 }
771
772 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
773 {
774 return sys->private_data;
775 }
776
777 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
778 struct pci_bus *bus,
779 int devfn)
780 {
781 int i;
782
783 for (i = 0; i < pcie->nports; i++) {
784 struct mvebu_pcie_port *port = &pcie->ports[i];
785
786 if (bus->number == 0 && port->devfn == devfn)
787 return port;
788 if (bus->number != 0 &&
789 bus->number >= port->bridge.secondary_bus &&
790 bus->number <= port->bridge.subordinate_bus)
791 return port;
792 }
793
794 return NULL;
795 }
796
797 /* PCI configuration space write function */
798 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
799 int where, int size, u32 val)
800 {
801 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
802 struct mvebu_pcie_port *port;
803 int ret;
804
805 port = mvebu_pcie_find_port(pcie, bus, devfn);
806 if (!port)
807 return PCIBIOS_DEVICE_NOT_FOUND;
808
809 /* Access the emulated PCI-to-PCI bridge */
810 if (bus->number == 0)
811 return mvebu_sw_pci_bridge_write(port, where, size, val);
812
813 if (!mvebu_pcie_link_up(port))
814 return PCIBIOS_DEVICE_NOT_FOUND;
815
816 /* Access the real PCIe interface */
817 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
818 where, size, val);
819
820 return ret;
821 }
822
823 /* PCI configuration space read function */
824 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
825 int size, u32 *val)
826 {
827 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
828 struct mvebu_pcie_port *port;
829 int ret;
830
831 port = mvebu_pcie_find_port(pcie, bus, devfn);
832 if (!port) {
833 *val = 0xffffffff;
834 return PCIBIOS_DEVICE_NOT_FOUND;
835 }
836
837 /* Access the emulated PCI-to-PCI bridge */
838 if (bus->number == 0)
839 return mvebu_sw_pci_bridge_read(port, where, size, val);
840
841 if (!mvebu_pcie_link_up(port)) {
842 *val = 0xffffffff;
843 return PCIBIOS_DEVICE_NOT_FOUND;
844 }
845
846 /* Access the real PCIe interface */
847 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
848 where, size, val);
849
850 return ret;
851 }
852
853 static struct pci_ops mvebu_pcie_ops = {
854 .read = mvebu_pcie_rd_conf,
855 .write = mvebu_pcie_wr_conf,
856 };
857
858 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
859 {
860 struct mvebu_pcie *pcie = sys_to_pcie(sys);
861 int err, i;
862
863 pcie->mem.name = "PCI MEM";
864 pcie->realio.name = "PCI I/O";
865
866 if (resource_size(&pcie->realio) != 0)
867 pci_add_resource_offset(&sys->resources, &pcie->realio,
868 sys->io_offset);
869
870 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
871 pci_add_resource(&sys->resources, &pcie->busn);
872
873 err = devm_request_pci_bus_resources(&pcie->pdev->dev, &sys->resources);
874 if (err)
875 return 0;
876
877 for (i = 0; i < pcie->nports; i++) {
878 struct mvebu_pcie_port *port = &pcie->ports[i];
879
880 if (!port->base)
881 continue;
882 mvebu_pcie_setup_hw(port);
883 }
884
885 return 1;
886 }
887
888 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
889 const struct resource *res,
890 resource_size_t start,
891 resource_size_t size,
892 resource_size_t align)
893 {
894 if (dev->bus->number != 0)
895 return start;
896
897 /*
898 * On the PCI-to-PCI bridge side, the I/O windows must have at
899 * least a 64 KB size and the memory windows must have at
900 * least a 1 MB size. Moreover, MBus windows need to have a
901 * base address aligned on their size, and their size must be
902 * a power of two. This means that if the BAR doesn't have a
903 * power of two size, several MBus windows will actually be
904 * created. We need to ensure that the biggest MBus window
905 * (which will be the first one) is aligned on its size, which
906 * explains the rounddown_pow_of_two() being done here.
907 */
908 if (res->flags & IORESOURCE_IO)
909 return round_up(start, max_t(resource_size_t, SZ_64K,
910 rounddown_pow_of_two(size)));
911 else if (res->flags & IORESOURCE_MEM)
912 return round_up(start, max_t(resource_size_t, SZ_1M,
913 rounddown_pow_of_two(size)));
914 else
915 return start;
916 }
917
918 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
919 {
920 struct hw_pci hw;
921
922 memset(&hw, 0, sizeof(hw));
923
924 #ifdef CONFIG_PCI_MSI
925 hw.msi_ctrl = pcie->msi;
926 #endif
927
928 hw.nr_controllers = 1;
929 hw.private_data = (void **)&pcie;
930 hw.setup = mvebu_pcie_setup;
931 hw.map_irq = of_irq_parse_and_map_pci;
932 hw.ops = &mvebu_pcie_ops;
933 hw.align_resource = mvebu_pcie_align_resource;
934
935 pci_common_init_dev(&pcie->pdev->dev, &hw);
936 }
937
938 /*
939 * Looks up the list of register addresses encoded into the reg =
940 * <...> property for one that matches the given port/lane. Once
941 * found, maps it.
942 */
943 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
944 struct device_node *np,
945 struct mvebu_pcie_port *port)
946 {
947 struct resource regs;
948 int ret = 0;
949
950 ret = of_address_to_resource(np, 0, &regs);
951 if (ret)
952 return ERR_PTR(ret);
953
954 return devm_ioremap_resource(&pdev->dev, &regs);
955 }
956
957 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
958 #define DT_TYPE_IO 0x1
959 #define DT_TYPE_MEM32 0x2
960 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
961 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
962
963 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
964 unsigned long type,
965 unsigned int *tgt,
966 unsigned int *attr)
967 {
968 const int na = 3, ns = 2;
969 const __be32 *range;
970 int rlen, nranges, rangesz, pna, i;
971
972 *tgt = -1;
973 *attr = -1;
974
975 range = of_get_property(np, "ranges", &rlen);
976 if (!range)
977 return -EINVAL;
978
979 pna = of_n_addr_cells(np);
980 rangesz = pna + na + ns;
981 nranges = rlen / sizeof(__be32) / rangesz;
982
983 for (i = 0; i < nranges; i++, range += rangesz) {
984 u32 flags = of_read_number(range, 1);
985 u32 slot = of_read_number(range + 1, 1);
986 u64 cpuaddr = of_read_number(range + na, pna);
987 unsigned long rtype;
988
989 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
990 rtype = IORESOURCE_IO;
991 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
992 rtype = IORESOURCE_MEM;
993 else
994 continue;
995
996 if (slot == PCI_SLOT(devfn) && type == rtype) {
997 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
998 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
999 return 0;
1000 }
1001 }
1002
1003 return -ENOENT;
1004 }
1005
1006 #ifdef CONFIG_PM_SLEEP
1007 static int mvebu_pcie_suspend(struct device *dev)
1008 {
1009 struct mvebu_pcie *pcie;
1010 int i;
1011
1012 pcie = dev_get_drvdata(dev);
1013 for (i = 0; i < pcie->nports; i++) {
1014 struct mvebu_pcie_port *port = pcie->ports + i;
1015 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
1016 }
1017
1018 return 0;
1019 }
1020
1021 static int mvebu_pcie_resume(struct device *dev)
1022 {
1023 struct mvebu_pcie *pcie;
1024 int i;
1025
1026 pcie = dev_get_drvdata(dev);
1027 for (i = 0; i < pcie->nports; i++) {
1028 struct mvebu_pcie_port *port = pcie->ports + i;
1029 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
1030 mvebu_pcie_setup_hw(port);
1031 }
1032
1033 return 0;
1034 }
1035 #endif
1036
1037 static void mvebu_pcie_port_clk_put(void *data)
1038 {
1039 struct mvebu_pcie_port *port = data;
1040
1041 clk_put(port->clk);
1042 }
1043
1044 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
1045 struct mvebu_pcie_port *port, struct device_node *child)
1046 {
1047 struct device *dev = &pcie->pdev->dev;
1048 enum of_gpio_flags flags;
1049 int reset_gpio, ret;
1050
1051 port->pcie = pcie;
1052
1053 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
1054 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
1055 child);
1056 goto skip;
1057 }
1058
1059 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
1060 port->lane = 0;
1061
1062 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
1063 port->lane);
1064 if (!port->name) {
1065 ret = -ENOMEM;
1066 goto err;
1067 }
1068
1069 port->devfn = of_pci_get_devfn(child);
1070 if (port->devfn < 0)
1071 goto skip;
1072
1073 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
1074 &port->mem_target, &port->mem_attr);
1075 if (ret < 0) {
1076 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
1077 port->name);
1078 goto skip;
1079 }
1080
1081 if (resource_size(&pcie->io) != 0) {
1082 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
1083 &port->io_target, &port->io_attr);
1084 } else {
1085 port->io_target = -1;
1086 port->io_attr = -1;
1087 }
1088
1089 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
1090 if (reset_gpio == -EPROBE_DEFER) {
1091 ret = reset_gpio;
1092 goto err;
1093 }
1094
1095 if (gpio_is_valid(reset_gpio)) {
1096 unsigned long gpio_flags;
1097
1098 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
1099 port->name);
1100 if (!port->reset_name) {
1101 ret = -ENOMEM;
1102 goto err;
1103 }
1104
1105 if (flags & OF_GPIO_ACTIVE_LOW) {
1106 dev_info(dev, "%pOF: reset gpio is active low\n",
1107 child);
1108 gpio_flags = GPIOF_ACTIVE_LOW |
1109 GPIOF_OUT_INIT_LOW;
1110 } else {
1111 gpio_flags = GPIOF_OUT_INIT_HIGH;
1112 }
1113
1114 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
1115 port->reset_name);
1116 if (ret) {
1117 if (ret == -EPROBE_DEFER)
1118 goto err;
1119 goto skip;
1120 }
1121
1122 port->reset_gpio = gpio_to_desc(reset_gpio);
1123 }
1124
1125 port->clk = of_clk_get_by_name(child, NULL);
1126 if (IS_ERR(port->clk)) {
1127 dev_err(dev, "%s: cannot get clock\n", port->name);
1128 goto skip;
1129 }
1130
1131 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
1132 if (ret < 0) {
1133 clk_put(port->clk);
1134 goto err;
1135 }
1136
1137 return 1;
1138
1139 skip:
1140 ret = 0;
1141
1142 /* In the case of skipping, we need to free these */
1143 devm_kfree(dev, port->reset_name);
1144 port->reset_name = NULL;
1145 devm_kfree(dev, port->name);
1146 port->name = NULL;
1147
1148 err:
1149 return ret;
1150 }
1151
1152 /*
1153 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
1154 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
1155 * of the PCI Express Card Electromechanical Specification, 1.1.
1156 */
1157 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
1158 {
1159 int ret;
1160
1161 ret = clk_prepare_enable(port->clk);
1162 if (ret < 0)
1163 return ret;
1164
1165 if (port->reset_gpio) {
1166 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
1167
1168 of_property_read_u32(port->dn, "reset-delay-us",
1169 &reset_udelay);
1170
1171 udelay(100);
1172
1173 gpiod_set_value_cansleep(port->reset_gpio, 0);
1174 msleep(reset_udelay / 1000);
1175 }
1176
1177 return 0;
1178 }
1179
1180 /*
1181 * Power down a PCIe port. Strictly, PCIe requires us to place the card
1182 * in D3hot state before asserting PERST#.
1183 */
1184 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
1185 {
1186 gpiod_set_value_cansleep(port->reset_gpio, 1);
1187
1188 clk_disable_unprepare(port->clk);
1189 }
1190
1191 static int mvebu_pcie_probe(struct platform_device *pdev)
1192 {
1193 struct device *dev = &pdev->dev;
1194 struct mvebu_pcie *pcie;
1195 struct device_node *np = dev->of_node;
1196 struct device_node *child;
1197 int num, i, ret;
1198
1199 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1200 if (!pcie)
1201 return -ENOMEM;
1202
1203 pcie->pdev = pdev;
1204 platform_set_drvdata(pdev, pcie);
1205
1206 /* Get the PCIe memory and I/O aperture */
1207 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
1208 if (resource_size(&pcie->mem) == 0) {
1209 dev_err(dev, "invalid memory aperture size\n");
1210 return -EINVAL;
1211 }
1212
1213 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
1214
1215 if (resource_size(&pcie->io) != 0) {
1216 pcie->realio.flags = pcie->io.flags;
1217 pcie->realio.start = PCIBIOS_MIN_IO;
1218 pcie->realio.end = min_t(resource_size_t,
1219 IO_SPACE_LIMIT,
1220 resource_size(&pcie->io));
1221 } else
1222 pcie->realio = pcie->io;
1223
1224 /* Get the bus range */
1225 ret = of_pci_parse_bus_range(np, &pcie->busn);
1226 if (ret) {
1227 dev_err(dev, "failed to parse bus-range property: %d\n", ret);
1228 return ret;
1229 }
1230
1231 num = of_get_available_child_count(np);
1232
1233 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
1234 if (!pcie->ports)
1235 return -ENOMEM;
1236
1237 i = 0;
1238 for_each_available_child_of_node(np, child) {
1239 struct mvebu_pcie_port *port = &pcie->ports[i];
1240
1241 ret = mvebu_pcie_parse_port(pcie, port, child);
1242 if (ret < 0) {
1243 of_node_put(child);
1244 return ret;
1245 } else if (ret == 0) {
1246 continue;
1247 }
1248
1249 port->dn = child;
1250 i++;
1251 }
1252 pcie->nports = i;
1253
1254 for (i = 0; i < pcie->nports; i++) {
1255 struct mvebu_pcie_port *port = &pcie->ports[i];
1256
1257 child = port->dn;
1258 if (!child)
1259 continue;
1260
1261 ret = mvebu_pcie_powerup(port);
1262 if (ret < 0)
1263 continue;
1264
1265 port->base = mvebu_pcie_map_registers(pdev, child, port);
1266 if (IS_ERR(port->base)) {
1267 dev_err(dev, "%s: cannot map registers\n", port->name);
1268 port->base = NULL;
1269 mvebu_pcie_powerdown(port);
1270 continue;
1271 }
1272
1273 mvebu_pcie_set_local_dev_nr(port, 1);
1274 mvebu_sw_pci_bridge_init(port);
1275 }
1276
1277 pcie->nports = i;
1278
1279 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1280 pci_ioremap_io(i, pcie->io.start + i);
1281
1282 mvebu_pcie_enable(pcie);
1283
1284 platform_set_drvdata(pdev, pcie);
1285
1286 return 0;
1287 }
1288
1289 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1290 { .compatible = "marvell,armada-xp-pcie", },
1291 { .compatible = "marvell,armada-370-pcie", },
1292 { .compatible = "marvell,dove-pcie", },
1293 { .compatible = "marvell,kirkwood-pcie", },
1294 {},
1295 };
1296
1297 static const struct dev_pm_ops mvebu_pcie_pm_ops = {
1298 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
1299 };
1300
1301 static struct platform_driver mvebu_pcie_driver = {
1302 .driver = {
1303 .name = "mvebu-pcie",
1304 .of_match_table = mvebu_pcie_of_match_table,
1305 /* driver unloading/unbinding currently not supported */
1306 .suppress_bind_attrs = true,
1307 .pm = &mvebu_pcie_pm_ops,
1308 },
1309 .probe = mvebu_pcie_probe,
1310 };
1311 builtin_platform_driver(mvebu_pcie_driver);
CRIS linux kernel tree